Module Name: src
Committed By: reinoud
Date: Sat Mar 22 16:39:20 UTC 2014
Modified Files:
src/sys/arch/arm/cortex: pl310_reg.h
Log Message:
Add defines for the PL310's L2C_PREFETCH_CTL and L2C_POWER_CTL registers as
per r3p2 spec.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/cortex/pl310_reg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/pl310_reg.h
diff -u src/sys/arch/arm/cortex/pl310_reg.h:1.2 src/sys/arch/arm/cortex/pl310_reg.h:1.3
--- src/sys/arch/arm/cortex/pl310_reg.h:1.2 Fri Sep 7 11:49:00 2012
+++ src/sys/arch/arm/cortex/pl310_reg.h Sat Mar 22 16:39:20 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: pl310_reg.h,v 1.2 2012/09/07 11:49:00 matt Exp $ */
+/* $NetBSD: pl310_reg.h,v 1.3 2014/03/22 16:39:20 reinoud Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -134,6 +134,21 @@
#define L2C_DEBUG_CTL 0xf40
#define L2C_PREFETCH_CTL 0xf60
+#define PREFETCHCTL_DBLLINEF_EN __BIT(30)
+#define PREFETCHCTL_INSTRPREF_EN __BIT(29)
+#define PREFETCHCTL_DATAPREF_EN __BIT(28)
+#define PREFETCHCTL_DBLLINEF_WRAP_DA __BIT(27)
+#define PREFETCHCTL_PREF_DROP_EN __BIT(24)
+#define PREFETCHCTL_INCRDBL_LINEF_EN __BIT(23)
+#define PREFETCHCTL_NOSAMEID_EXCL_SEQ_EN __BIT(21)
+#define PREFETCHCTL_PREFETCH_OFFSET_0 0
+#define PREFETCHCTL_PREFETCH_OFFSET_7 7
+#define PREFETCHCTL_PREFETCH_OFFSET_15 15
+#define PREFETCHCTL_PREFETCH_OFFSET_23 23
+#define PREFETCHCTL_PREFETCH_OFFSET_31 31
+
#define L2C_POWER_CTL 0xf80
+#define POWERCTL_DYNCLKGATE __BIT(1)
+#define POWERCTL_STANDBY __BIT(0)
#endif /* _ARM_CORTEX_PL310_REG_H_ */
