Module Name: src
Committed By: skrll
Date: Fri Mar 28 21:32:41 UTC 2014
Modified Files:
src/common/lib/libc/arch/arm/atomic: membar_ops.S
Log Message:
Ensure SBZ register is zero
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/common/lib/libc/arch/arm/atomic/membar_ops.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/common/lib/libc/arch/arm/atomic/membar_ops.S
diff -u src/common/lib/libc/arch/arm/atomic/membar_ops.S:1.5 src/common/lib/libc/arch/arm/atomic/membar_ops.S:1.6
--- src/common/lib/libc/arch/arm/atomic/membar_ops.S:1.5 Tue Mar 4 16:15:28 2014
+++ src/common/lib/libc/arch/arm/atomic/membar_ops.S Fri Mar 28 21:32:41 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: membar_ops.S,v 1.5 2014/03/04 16:15:28 matt Exp $ */
+/* $NetBSD: membar_ops.S,v 1.6 2014/03/28 21:32:41 skrll Exp $ */
/*-
* Copyright (c) 2008 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -36,6 +36,7 @@ ENTRY_NP(_membar_producer)
#ifdef _ARM_ARCH_7
dsb
#else
+ mov r0, #0
mcr p15, 0, r0, c7, c10, 4 /* Data Synchronization Barrier */
#endif
RET
@@ -48,6 +49,7 @@ ENTRY_NP(_membar_sync)
#ifdef _ARM_ARCH_7
dmb
#else
+ mov r0, #0
mcr p15, 0, r0, c7, c10, 5 /* Data Memory Barrier */
#endif
RET
