Module Name: src
Committed By: matt
Date: Sat Mar 29 23:33:20 UTC 2014
Modified Files:
src/sys/arch/arm/include: armreg.h
Log Message:
Add scr inline
To generate a diff of this commit:
cvs rdiff -u -r1.94 -r1.95 src/sys/arch/arm/include/armreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/include/armreg.h
diff -u src/sys/arch/arm/include/armreg.h:1.94 src/sys/arch/arm/include/armreg.h:1.95
--- src/sys/arch/arm/include/armreg.h:1.94 Wed Mar 26 01:14:52 2014
+++ src/sys/arch/arm/include/armreg.h Sat Mar 29 23:33:20 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.94 2014/03/26 01:14:52 matt Exp $ */
+/* $NetBSD: armreg.h,v 1.95 2014/03/29 23:33:20 matt Exp $ */
/*
* Copyright (c) 1998, 2001 Ben Harris
@@ -902,6 +902,7 @@ ARMREG_READ_INLINE(auxctl, "p15,0,%0,c1,
ARMREG_WRITE_INLINE(auxctl, "p15,0,%0,c1,c0,1") /* Auxiliary Control Register */
ARMREG_READ_INLINE(cpacr, "p15,0,%0,c1,c0,2") /* Co-Processor Access Control Register */
ARMREG_WRITE_INLINE(cpacr, "p15,0,%0,c1,c0,2") /* Co-Processor Access Control Register */
+ARMREG_READ_INLINE(scr, "p15,0,%0,c1,c1,0") /* Secure Configuration Register */
ARMREG_READ_INLINE(nsacr, "p15,0,%0,c1,c1,2") /* Non-Secure Access Control Register */
/* cp15 c2 registers */
ARMREG_READ_INLINE(ttbr, "p15,0,%0,c2,c0,0") /* Translation Table Base Register 0 */
