Module Name: src Committed By: skrll Date: Thu Apr 3 06:34:58 UTC 2014
Modified Files: src/sys/external/bsd/dwc2/dist: dwc2_core.c dwc2_core.h dwc2_coreintr.c dwc2_hcd.c dwc2_hcd.h dwc2_hcdddma.c dwc2_hcdintr.c dwc2_hcdqueue.c Log Message: Merge conflicts. To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/external/bsd/dwc2/dist/dwc2_core.c \ src/sys/external/bsd/dwc2/dist/dwc2_hcdddma.c cvs rdiff -u -r1.4 -r1.5 src/sys/external/bsd/dwc2/dist/dwc2_core.h cvs rdiff -u -r1.6 -r1.7 src/sys/external/bsd/dwc2/dist/dwc2_coreintr.c cvs rdiff -u -r1.11 -r1.12 src/sys/external/bsd/dwc2/dist/dwc2_hcd.c cvs rdiff -u -r1.7 -r1.8 src/sys/external/bsd/dwc2/dist/dwc2_hcd.h \ src/sys/external/bsd/dwc2/dist/dwc2_hcdintr.c cvs rdiff -u -r1.8 -r1.9 src/sys/external/bsd/dwc2/dist/dwc2_hcdqueue.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/external/bsd/dwc2/dist/dwc2_core.c diff -u src/sys/external/bsd/dwc2/dist/dwc2_core.c:1.5 src/sys/external/bsd/dwc2/dist/dwc2_core.c:1.6 --- src/sys/external/bsd/dwc2/dist/dwc2_core.c:1.5 Fri Mar 21 09:19:10 2014 +++ src/sys/external/bsd/dwc2/dist/dwc2_core.c Thu Apr 3 06:34:58 2014 @@ -1,4 +1,4 @@ -/* $NetBSD: dwc2_core.c,v 1.5 2014/03/21 09:19:10 skrll Exp $ */ +/* $NetBSD: dwc2_core.c,v 1.6 2014/04/03 06:34:58 skrll Exp $ */ /* * core.c - DesignWare HS OTG Controller common routines @@ -43,7 +43,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: dwc2_core.c,v 1.5 2014/03/21 09:19:10 skrll Exp $"); +__KERNEL_RCSID(0, "$NetBSD: dwc2_core.c,v 1.6 2014/04/03 06:34:58 skrll Exp $"); #include <sys/types.h> #include <sys/bus.h> @@ -125,7 +125,7 @@ static void dwc2_init_fs_ls_pclk_sel(str * Do core a soft reset of the core. Be careful with this because it * resets all the internal state machines of the core. */ -static void dwc2_core_reset(struct dwc2_hsotg *hsotg) +static int dwc2_core_reset(struct dwc2_hsotg *hsotg) { u32 greset; int count = 0; @@ -140,7 +140,7 @@ static void dwc2_core_reset(struct dwc2_ dev_warn(hsotg->dev, "%s() HANG! AHB Idle GRSTCTL=%0x\n", __func__, greset); - return; + return -EBUSY; } } while (!(greset & GRSTCTL_AHBIDLE)); @@ -155,7 +155,7 @@ static void dwc2_core_reset(struct dwc2_ dev_warn(hsotg->dev, "%s() HANG! Soft Reset GRSTCTL=%0x\n", __func__, greset); - break; + return -EBUSY; } } while (greset & GRSTCTL_CSFTRST); @@ -164,11 +164,14 @@ static void dwc2_core_reset(struct dwc2_ * not stay in host mode after a connector ID change! */ usleep_range(150000, 200000); + + return 0; } -static void dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) +static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) { u32 usbcfg, i2cctl; + int retval = 0; /* * core_init() is now called on every switch so only call the @@ -181,7 +184,12 @@ static void dwc2_fs_phy_init(struct dwc2 DWC2_WRITE_4(hsotg, GUSBCFG, usbcfg); /* Reset after a PHY select */ - dwc2_core_reset(hsotg); + retval = dwc2_core_reset(hsotg); + if (retval) { + dev_err(hsotg->dev, "%s() Reset failed, aborting", + __func__); + return retval; + } } /* @@ -209,14 +217,17 @@ static void dwc2_fs_phy_init(struct dwc2 i2cctl |= GI2CCTL_I2CEN; DWC2_WRITE_4(hsotg, GI2CCTL, i2cctl); } + + return retval; } -static void dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) +static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) { u32 usbcfg; + int retval = 0; if (!select_phy) - return; + return 0; usbcfg = DWC2_READ_4(hsotg, GUSBCFG); @@ -249,20 +260,32 @@ static void dwc2_hs_phy_init(struct dwc2 DWC2_WRITE_4(hsotg, GUSBCFG, usbcfg); /* Reset after setting the PHY parameters */ - dwc2_core_reset(hsotg); + retval = dwc2_core_reset(hsotg); + if (retval) { + dev_err(hsotg->dev, "%s() Reset failed, aborting", + __func__); + return retval; + } + + return retval; } -static void dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) +static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) { u32 usbcfg; + int retval = 0; if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL && hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) { /* If FS mode with FS PHY */ - dwc2_fs_phy_init(hsotg, select_phy); + retval = dwc2_fs_phy_init(hsotg, select_phy); + if (retval) + return retval; } else { /* High speed PHY */ - dwc2_hs_phy_init(hsotg, select_phy); + retval = dwc2_hs_phy_init(hsotg, select_phy); + if (retval) + return retval; } if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && @@ -279,6 +302,8 @@ static void dwc2_phy_init(struct dwc2_hs usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M; DWC2_WRITE_4(hsotg, GUSBCFG, usbcfg); } + + return retval; } static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg) @@ -393,12 +418,19 @@ int dwc2_core_init(struct dwc2_hsotg *hs DWC2_WRITE_4(hsotg, GUSBCFG, usbcfg); /* Reset the Controller */ - dwc2_core_reset(hsotg); + retval = dwc2_core_reset(hsotg); + if (retval) { + dev_err(hsotg->dev, "%s(): Reset failed, aborting\n", + __func__); + return retval; + } /* * This needs to happen in FS mode before any other programming occurs */ - dwc2_phy_init(hsotg, select_phy); + retval = dwc2_phy_init(hsotg, select_phy); + if (retval) + return retval; /* Program the GAHBCFG Register */ retval = dwc2_gahbcfg_init(hsotg); @@ -452,9 +484,6 @@ void dwc2_enable_host_interrupts(struct DWC2_WRITE_4(hsotg, GINTMSK, 0); DWC2_WRITE_4(hsotg, HAINTMSK, 0); - /* Clear any pending interrupts */ - DWC2_WRITE_4(hsotg, GINTSTS, 0xffffffff); - /* Enable the common interrupts */ dwc2_enable_common_interrupts(hsotg); @@ -1912,13 +1941,12 @@ void dwc2_flush_rx_fifo(struct dwc2_hsot udelay(1); } -#define DWC2_PARAM_TEST(a, b, c) ((a) < (b) || (a) > (c)) +#define DWC2_OUT_OF_BOUNDS(a, b, c) ((a) < (b) || (a) > (c)) /* Parameter access functions */ -int dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val) +void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val) { int valid = 1; - int retval = 0; switch (val) { case DWC2_CAP_PARAM_HNP_SRP_CAPABLE: @@ -1964,17 +1992,14 @@ int dwc2_set_param_otg_cap(struct dwc2_h break; } dev_dbg(hsotg->dev, "Setting otg_cap to %d\n", val); - retval = -EINVAL; } hsotg->core_params->otg_cap = val; - return retval; } -int dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val) +void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val) { int valid = 1; - int retval = 0; if (val > 0 && hsotg->hw_params.arch == GHWCFG2_SLAVE_ONLY_ARCH) valid = 0; @@ -1988,17 +2013,14 @@ int dwc2_set_param_dma_enable(struct dwc val); val = hsotg->hw_params.arch != GHWCFG2_SLAVE_ONLY_ARCH; dev_dbg(hsotg->dev, "Setting dma_enable to %d\n", val); - retval = -EINVAL; } hsotg->core_params->dma_enable = val; - return retval; } -int dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val) +void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val) { int valid = 1; - int retval = 0; if (val > 0 && (hsotg->core_params->dma_enable <= 0 || !hsotg->hw_params.dma_desc_enable)) @@ -2014,19 +2036,15 @@ int dwc2_set_param_dma_desc_enable(struc val = (hsotg->core_params->dma_enable > 0 && hsotg->hw_params.dma_desc_enable); dev_dbg(hsotg->dev, "Setting dma_desc_enable to %d\n", val); - retval = -EINVAL; } hsotg->core_params->dma_desc_enable = val; - return retval; } -int dwc2_set_param_host_support_fs_ls_low_power(struct dwc2_hsotg *hsotg, - int val) +void dwc2_set_param_host_support_fs_ls_low_power(struct dwc2_hsotg *hsotg, + int val) { - int retval = 0; - - if (DWC2_PARAM_TEST(val, 0, 1)) { + if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { if (val >= 0) { dev_err(hsotg->dev, "Wrong value for host_support_fs_low_power\n"); @@ -2036,17 +2054,14 @@ int dwc2_set_param_host_support_fs_ls_lo val = 0; dev_dbg(hsotg->dev, "Setting host_support_fs_low_power to %d\n", val); - retval = -EINVAL; } hsotg->core_params->host_support_fs_ls_low_power = val; - return retval; } -int dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, int val) +void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, int val) { int valid = 1; - int retval = 0; if (val > 0 && !hsotg->hw_params.enable_dynamic_fifo) valid = 0; @@ -2060,17 +2075,14 @@ int dwc2_set_param_enable_dynamic_fifo(s val); val = hsotg->hw_params.enable_dynamic_fifo; dev_dbg(hsotg->dev, "Setting enable_dynamic_fifo to %d\n", val); - retval = -EINVAL; } hsotg->core_params->enable_dynamic_fifo = val; - return retval; } -int dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val) +void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val) { int valid = 1; - int retval = 0; if (val < 16 || val > hsotg->hw_params.host_rx_fifo_size) valid = 0; @@ -2082,17 +2094,14 @@ int dwc2_set_param_host_rx_fifo_size(str val); val = hsotg->hw_params.host_rx_fifo_size; dev_dbg(hsotg->dev, "Setting host_rx_fifo_size to %d\n", val); - retval = -EINVAL; } hsotg->core_params->host_rx_fifo_size = val; - return retval; } -int dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val) +void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val) { int valid = 1; - int retval = 0; if (val < 16 || val > hsotg->hw_params.host_nperio_tx_fifo_size) valid = 0; @@ -2105,17 +2114,14 @@ int dwc2_set_param_host_nperio_tx_fifo_s val = hsotg->hw_params.host_nperio_tx_fifo_size; dev_dbg(hsotg->dev, "Setting host_nperio_tx_fifo_size to %d\n", val); - retval = -EINVAL; } hsotg->core_params->host_nperio_tx_fifo_size = val; - return retval; } -int dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val) +void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val) { int valid = 1; - int retval = 0; if (val < 16 || val > hsotg->hw_params.host_perio_tx_fifo_size) valid = 0; @@ -2128,17 +2134,14 @@ int dwc2_set_param_host_perio_tx_fifo_si val = hsotg->hw_params.host_perio_tx_fifo_size; dev_dbg(hsotg->dev, "Setting host_perio_tx_fifo_size to %d\n", val); - retval = -EINVAL; } hsotg->core_params->host_perio_tx_fifo_size = val; - return retval; } -int dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val) +void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val) { int valid = 1; - int retval = 0; if (val < 2047 || val > hsotg->hw_params.max_transfer_size) valid = 0; @@ -2150,17 +2153,14 @@ int dwc2_set_param_max_transfer_size(str val); val = hsotg->hw_params.max_transfer_size; dev_dbg(hsotg->dev, "Setting max_transfer_size to %d\n", val); - retval = -EINVAL; } hsotg->core_params->max_transfer_size = val; - return retval; } -int dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val) +void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val) { int valid = 1; - int retval = 0; if (val < 15 || val > hsotg->hw_params.max_packet_count) valid = 0; @@ -2172,17 +2172,14 @@ int dwc2_set_param_max_packet_count(stru val); val = hsotg->hw_params.max_packet_count; dev_dbg(hsotg->dev, "Setting max_packet_count to %d\n", val); - retval = -EINVAL; } hsotg->core_params->max_packet_count = val; - return retval; } -int dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val) +void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val) { int valid = 1; - int retval = 0; if (val < 1 || val > hsotg->hw_params.host_channels) valid = 0; @@ -2194,38 +2191,26 @@ int dwc2_set_param_host_channels(struct val); val = hsotg->hw_params.host_channels; dev_dbg(hsotg->dev, "Setting host_channels to %d\n", val); - retval = -EINVAL; } hsotg->core_params->host_channels = val; - return retval; } -int dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val) +void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val) { -#ifndef NO_FS_PHY_HW_CHECKS int valid = 0; u32 hs_phy_type, fs_phy_type; -#endif - int retval = 0; - if (DWC2_PARAM_TEST(val, DWC2_PHY_TYPE_PARAM_FS, - DWC2_PHY_TYPE_PARAM_ULPI)) { + if (DWC2_OUT_OF_BOUNDS(val, DWC2_PHY_TYPE_PARAM_FS, + DWC2_PHY_TYPE_PARAM_ULPI)) { if (val >= 0) { dev_err(hsotg->dev, "Wrong value for phy_type\n"); dev_err(hsotg->dev, "phy_type must be 0, 1 or 2\n"); } -#ifndef NO_FS_PHY_HW_CHECKS valid = 0; -#else - val = DWC2_PHY_TYPE_PARAM_FS; - dev_dbg(hsotg->dev, "Setting phy_type to %d\n", val); - retval = -EINVAL; -#endif } -#ifndef NO_FS_PHY_HW_CHECKS hs_phy_type = hsotg->hw_params.hs_phy_type; fs_phy_type = hsotg->hw_params.fs_phy_type; if (val == DWC2_PHY_TYPE_PARAM_UTMI && @@ -2254,12 +2239,9 @@ int dwc2_set_param_phy_type(struct dwc2_ val = DWC2_PHY_TYPE_PARAM_ULPI; } dev_dbg(hsotg->dev, "Setting phy_type to %d\n", val); - retval = -EINVAL; } -#endif hsotg->core_params->phy_type = val; - return retval; } static int dwc2_get_param_phy_type(struct dwc2_hsotg *hsotg) @@ -2267,12 +2249,11 @@ static int dwc2_get_param_phy_type(struc return hsotg->core_params->phy_type; } -int dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val) +void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val) { int valid = 1; - int retval = 0; - if (DWC2_PARAM_TEST(val, 0, 1)) { + if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { if (val >= 0) { dev_err(hsotg->dev, "Wrong value for speed parameter\n"); dev_err(hsotg->dev, "max_speed parameter must be 0 or 1\n"); @@ -2292,20 +2273,17 @@ int dwc2_set_param_speed(struct dwc2_hso val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS ? DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH; dev_dbg(hsotg->dev, "Setting speed to %d\n", val); - retval = -EINVAL; } hsotg->core_params->speed = val; - return retval; } -int dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, int val) +void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, int val) { int valid = 1; - int retval = 0; - if (DWC2_PARAM_TEST(val, DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ, - DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)) { + if (DWC2_OUT_OF_BOUNDS(val, DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ, + DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)) { if (val >= 0) { dev_err(hsotg->dev, "Wrong value for host_ls_low_power_phy_clk parameter\n"); @@ -2329,36 +2307,28 @@ int dwc2_set_param_host_ls_low_power_phy : DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ; dev_dbg(hsotg->dev, "Setting host_ls_low_power_phy_clk to %d\n", val); - retval = -EINVAL; } hsotg->core_params->host_ls_low_power_phy_clk = val; - return retval; } -int dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val) +void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val) { - int retval = 0; - - if (DWC2_PARAM_TEST(val, 0, 1)) { + if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { if (val >= 0) { dev_err(hsotg->dev, "Wrong value for phy_ulpi_ddr\n"); dev_err(hsotg->dev, "phy_upli_ddr must be 0 or 1\n"); } val = 0; dev_dbg(hsotg->dev, "Setting phy_upli_ddr to %d\n", val); - retval = -EINVAL; } hsotg->core_params->phy_ulpi_ddr = val; - return retval; } -int dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val) +void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val) { - int retval = 0; - - if (DWC2_PARAM_TEST(val, 0, 1)) { + if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { if (val >= 0) { dev_err(hsotg->dev, "Wrong value for phy_ulpi_ext_vbus\n"); @@ -2367,17 +2337,14 @@ int dwc2_set_param_phy_ulpi_ext_vbus(str } val = 0; dev_dbg(hsotg->dev, "Setting phy_ulpi_ext_vbus to %d\n", val); - retval = -EINVAL; } hsotg->core_params->phy_ulpi_ext_vbus = val; - return retval; } -int dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val) +void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val) { int valid = 0; - int retval = 0; switch (hsotg->hw_params.utmi_phy_data_width) { case GHWCFG4_UTMI_PHY_DATA_WIDTH_8: @@ -2400,72 +2367,52 @@ int dwc2_set_param_phy_utmi_width(struct val = (hsotg->hw_params.utmi_phy_data_width == GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16; dev_dbg(hsotg->dev, "Setting phy_utmi_width to %d\n", val); - retval = -EINVAL; } hsotg->core_params->phy_utmi_width = val; - return retval; } -int dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val) +void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val) { - int retval = 0; - - if (DWC2_PARAM_TEST(val, 0, 1)) { + if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { if (val >= 0) { dev_err(hsotg->dev, "Wrong value for ulpi_fs_ls\n"); dev_err(hsotg->dev, "ulpi_fs_ls must be 0 or 1\n"); } val = 0; dev_dbg(hsotg->dev, "Setting ulpi_fs_ls to %d\n", val); - retval = -EINVAL; } hsotg->core_params->ulpi_fs_ls = val; - return retval; } -int dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val) +void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val) { - int retval = 0; - - if (DWC2_PARAM_TEST(val, 0, 1)) { + if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { if (val >= 0) { dev_err(hsotg->dev, "Wrong value for ts_dline\n"); dev_err(hsotg->dev, "ts_dline must be 0 or 1\n"); } val = 0; dev_dbg(hsotg->dev, "Setting ts_dline to %d\n", val); - retval = -EINVAL; } hsotg->core_params->ts_dline = val; - return retval; } -int dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val) +void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val) { -#ifndef NO_FS_PHY_HW_CHECKS int valid = 1; -#endif - int retval = 0; - if (DWC2_PARAM_TEST(val, 0, 1)) { + if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { if (val >= 0) { dev_err(hsotg->dev, "Wrong value for i2c_enable\n"); dev_err(hsotg->dev, "i2c_enable must be 0 or 1\n"); } -#ifndef NO_FS_PHY_HW_CHECKS valid = 0; -#else - val = 0; - dev_dbg(hsotg->dev, "Setting i2c_enable to %d\n", val); - retval = -EINVAL; -#endif } -#ifndef NO_FS_PHY_HW_CHECKS if (val == 1 && !(hsotg->hw_params.i2c_enable)) valid = 0; @@ -2476,20 +2423,16 @@ int dwc2_set_param_i2c_enable(struct dwc val); val = hsotg->hw_params.i2c_enable; dev_dbg(hsotg->dev, "Setting i2c_enable to %d\n", val); - retval = -EINVAL; } -#endif hsotg->core_params->i2c_enable = val; - return retval; } -int dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, int val) +void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, int val) { int valid = 1; - int retval = 0; - if (DWC2_PARAM_TEST(val, 0, 1)) { + if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { if (val >= 0) { dev_err(hsotg->dev, "Wrong value for en_multiple_tx_fifo,\n"); @@ -2509,19 +2452,16 @@ int dwc2_set_param_en_multiple_tx_fifo(s val); val = hsotg->hw_params.en_multiple_tx_fifo; dev_dbg(hsotg->dev, "Setting en_multiple_tx_fifo to %d\n", val); - retval = -EINVAL; } hsotg->core_params->en_multiple_tx_fifo = val; - return retval; } -int dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val) +void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val) { int valid = 1; - int retval = 0; - if (DWC2_PARAM_TEST(val, 0, 1)) { + if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { if (val >= 0) { dev_err(hsotg->dev, "'%d' invalid for parameter reload_ctl\n", val); @@ -2540,28 +2480,23 @@ int dwc2_set_param_reload_ctl(struct dwc val); val = hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_92a; dev_dbg(hsotg->dev, "Setting reload_ctl to %d\n", val); - retval = -EINVAL; } hsotg->core_params->reload_ctl = val; - return retval; } -int dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val) +void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val) { if (val != -1) hsotg->core_params->ahbcfg = val; else hsotg->core_params->ahbcfg = GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT; - return 0; } -int dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val) +void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val) { - int retval = 0; - - if (DWC2_PARAM_TEST(val, 0, 1)) { + if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { if (val >= 0) { dev_err(hsotg->dev, "'%d' invalid for parameter otg_ver\n", val); @@ -2570,11 +2505,71 @@ int dwc2_set_param_otg_ver(struct dwc2_h } val = 0; dev_dbg(hsotg->dev, "Setting otg_ver to %d\n", val); - retval = -EINVAL; } hsotg->core_params->otg_ver = val; - return retval; +} + +static void dwc2_set_param_uframe_sched(struct dwc2_hsotg *hsotg, int val) +{ + if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { + if (val >= 0) { + dev_err(hsotg->dev, + "'%d' invalid for parameter uframe_sched\n", + val); + dev_err(hsotg->dev, "uframe_sched must be 0 or 1\n"); + } + val = 1; + dev_dbg(hsotg->dev, "Setting uframe_sched to %d\n", val); + } + + hsotg->core_params->uframe_sched = val; +} + +/* + * This function is called during module intialization to pass module parameters + * for the DWC_otg core. + */ +void dwc2_set_parameters(struct dwc2_hsotg *hsotg, + const struct dwc2_core_params *params) +{ + dev_dbg(hsotg->dev, "%s()\n", __func__); + + dwc2_set_param_otg_cap(hsotg, params->otg_cap); + dwc2_set_param_dma_enable(hsotg, params->dma_enable); + dwc2_set_param_dma_desc_enable(hsotg, params->dma_desc_enable); + dwc2_set_param_host_support_fs_ls_low_power(hsotg, + params->host_support_fs_ls_low_power); + dwc2_set_param_enable_dynamic_fifo(hsotg, + params->enable_dynamic_fifo); + dwc2_set_param_host_rx_fifo_size(hsotg, + params->host_rx_fifo_size); + dwc2_set_param_host_nperio_tx_fifo_size(hsotg, + params->host_nperio_tx_fifo_size); + dwc2_set_param_host_perio_tx_fifo_size(hsotg, + params->host_perio_tx_fifo_size); + dwc2_set_param_max_transfer_size(hsotg, + params->max_transfer_size); + dwc2_set_param_max_packet_count(hsotg, + params->max_packet_count); + dwc2_set_param_host_channels(hsotg, params->host_channels); + dwc2_set_param_phy_type(hsotg, params->phy_type); + dwc2_set_param_speed(hsotg, params->speed); + dwc2_set_param_host_ls_low_power_phy_clk(hsotg, + params->host_ls_low_power_phy_clk); + dwc2_set_param_phy_ulpi_ddr(hsotg, params->phy_ulpi_ddr); + dwc2_set_param_phy_ulpi_ext_vbus(hsotg, + params->phy_ulpi_ext_vbus); + dwc2_set_param_phy_utmi_width(hsotg, params->phy_utmi_width); + dwc2_set_param_ulpi_fs_ls(hsotg, params->ulpi_fs_ls); + dwc2_set_param_ts_dline(hsotg, params->ts_dline); + dwc2_set_param_i2c_enable(hsotg, params->i2c_enable); + dwc2_set_param_en_multiple_tx_fifo(hsotg, + params->en_multiple_tx_fifo); + dwc2_set_param_reload_ctl(hsotg, params->reload_ctl); + dwc2_set_param_ahbcfg(hsotg, params->ahbcfg); + dwc2_set_param_otg_ver(hsotg, params->otg_ver); + dwc2_set_param_uframe_sched(hsotg, params->uframe_sched); } /** @@ -2735,88 +2730,17 @@ int dwc2_get_hwparams(struct dwc2_hsotg return 0; } -int dwc2_set_param_uframe_sched(struct dwc2_hsotg *hsotg, int val) -{ - int retval = 0; - - if (DWC2_PARAM_TEST(val, 0, 1)) { - if (val >= 0) { - dev_err(hsotg->dev, - "'%d' invalid for parameter uframe_sched\n", - val); - dev_err(hsotg->dev, "uframe_sched must be 0 or 1\n"); - } - val = 1; - dev_dbg(hsotg->dev, "Setting uframe_sched to %d\n", val); - retval = -EINVAL; - } - - hsotg->core_params->uframe_sched = val; - return retval; -} - -/* - * This function is called during module intialization to pass module parameters - * for the DWC_otg core. It returns non-0 if any parameters are invalid. - */ -int dwc2_set_parameters(struct dwc2_hsotg *hsotg, - const struct dwc2_core_params *params) -{ - int retval = 0; - - dev_dbg(hsotg->dev, "%s()\n", __func__); - - retval |= dwc2_set_param_otg_cap(hsotg, params->otg_cap); - retval |= dwc2_set_param_dma_enable(hsotg, params->dma_enable); - retval |= dwc2_set_param_dma_desc_enable(hsotg, - params->dma_desc_enable); - retval |= dwc2_set_param_host_support_fs_ls_low_power(hsotg, - params->host_support_fs_ls_low_power); - retval |= dwc2_set_param_enable_dynamic_fifo(hsotg, - params->enable_dynamic_fifo); - retval |= dwc2_set_param_host_rx_fifo_size(hsotg, - params->host_rx_fifo_size); - retval |= dwc2_set_param_host_nperio_tx_fifo_size(hsotg, - params->host_nperio_tx_fifo_size); - retval |= dwc2_set_param_host_perio_tx_fifo_size(hsotg, - params->host_perio_tx_fifo_size); - retval |= dwc2_set_param_max_transfer_size(hsotg, - params->max_transfer_size); - retval |= dwc2_set_param_max_packet_count(hsotg, - params->max_packet_count); - retval |= dwc2_set_param_host_channels(hsotg, params->host_channels); - retval |= dwc2_set_param_phy_type(hsotg, params->phy_type); - retval |= dwc2_set_param_speed(hsotg, params->speed); - retval |= dwc2_set_param_host_ls_low_power_phy_clk(hsotg, - params->host_ls_low_power_phy_clk); - retval |= dwc2_set_param_phy_ulpi_ddr(hsotg, params->phy_ulpi_ddr); - retval |= dwc2_set_param_phy_ulpi_ext_vbus(hsotg, - params->phy_ulpi_ext_vbus); - retval |= dwc2_set_param_phy_utmi_width(hsotg, params->phy_utmi_width); - retval |= dwc2_set_param_ulpi_fs_ls(hsotg, params->ulpi_fs_ls); - retval |= dwc2_set_param_ts_dline(hsotg, params->ts_dline); - retval |= dwc2_set_param_i2c_enable(hsotg, params->i2c_enable); - retval |= dwc2_set_param_en_multiple_tx_fifo(hsotg, - params->en_multiple_tx_fifo); - retval |= dwc2_set_param_reload_ctl(hsotg, params->reload_ctl); - retval |= dwc2_set_param_ahbcfg(hsotg, params->ahbcfg); - retval |= dwc2_set_param_otg_ver(hsotg, params->otg_ver); - retval |= dwc2_set_param_uframe_sched(hsotg, params->uframe_sched); - - return retval; -} - u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg) { - return (u16)(hsotg->core_params->otg_ver == 1 ? 0x0200 : 0x0103); + return hsotg->core_params->otg_ver == 1 ? 0x0200 : 0x0103; } -int dwc2_check_core_status(struct dwc2_hsotg *hsotg) +bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg) { if (DWC2_READ_4(hsotg, GSNPSID) == 0xffffffff) - return -1; + return false; else - return 0; + return true; } /** Index: src/sys/external/bsd/dwc2/dist/dwc2_hcdddma.c diff -u src/sys/external/bsd/dwc2/dist/dwc2_hcdddma.c:1.5 src/sys/external/bsd/dwc2/dist/dwc2_hcdddma.c:1.6 --- src/sys/external/bsd/dwc2/dist/dwc2_hcdddma.c:1.5 Sat Dec 14 09:58:03 2013 +++ src/sys/external/bsd/dwc2/dist/dwc2_hcdddma.c Thu Apr 3 06:34:58 2014 @@ -1,4 +1,4 @@ -/* $NetBSD: dwc2_hcdddma.c,v 1.5 2013/12/14 09:58:03 skrll Exp $ */ +/* $NetBSD: dwc2_hcdddma.c,v 1.6 2014/04/03 06:34:58 skrll Exp $ */ /* * hcd_ddma.c - DesignWare HS OTG Controller descriptor DMA routines @@ -40,7 +40,7 @@ * This file contains the Descriptor DMA implementation for Host mode */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: dwc2_hcdddma.c,v 1.5 2013/12/14 09:58:03 skrll Exp $"); +__KERNEL_RCSID(0, "$NetBSD: dwc2_hcdddma.c,v 1.6 2014/04/03 06:34:58 skrll Exp $"); #include <sys/param.h> #include <sys/types.h> @@ -641,8 +641,8 @@ static void dwc2_fill_host_dma_desc(stru struct dwc2_hcd_dma_desc *dma_desc = &qh->desc_list[n_desc]; int len = chan->xfer_len; - if (len > MAX_DMA_DESC_SIZE) - len = MAX_DMA_DESC_SIZE - chan->max_packet + 1; + if (len > MAX_DMA_DESC_SIZE - (chan->max_packet - 1)) + len = MAX_DMA_DESC_SIZE - (chan->max_packet - 1); if (chan->ep_is_in) { int num_packets; @@ -1123,8 +1123,10 @@ static void dwc2_complete_non_isoc_xfer_ for (i = 0; i < qtd->n_desc; i++) { if (dwc2_process_non_isoc_desc(hsotg, chan, chnum, qtd, desc_num, halt_status, - &xfer_done)) + &xfer_done)) { + qtd = NULL; break; + } desc_num++; } } Index: src/sys/external/bsd/dwc2/dist/dwc2_core.h diff -u src/sys/external/bsd/dwc2/dist/dwc2_core.h:1.4 src/sys/external/bsd/dwc2/dist/dwc2_core.h:1.5 --- src/sys/external/bsd/dwc2/dist/dwc2_core.h:1.4 Sat Oct 5 06:51:43 2013 +++ src/sys/external/bsd/dwc2/dist/dwc2_core.h Thu Apr 3 06:34:58 2014 @@ -1,4 +1,4 @@ -/* $NetBSD: dwc2_core.h,v 1.4 2013/10/05 06:51:43 skrll Exp $ */ +/* $NetBSD: dwc2_core.h,v 1.5 2014/04/03 06:34:58 skrll Exp $ */ /* * core.h - DesignWare HS OTG Controller common declarations @@ -545,7 +545,7 @@ extern void dwc2_enable_host_interrupts( extern void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg); extern u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg); -extern int dwc2_check_core_status(struct dwc2_hsotg *hsotg); +extern bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); /* * Common core Functions. @@ -572,7 +572,7 @@ extern irqreturn_t dwc2_handle_common_in * 1 - SRP Only capable * 2 - No HNP/SRP capable */ -extern int dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val); +extern void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val); #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 @@ -584,7 +584,7 @@ extern int dwc2_set_param_otg_cap(struct * 0 - Slave * 1 - DMA (default, if available) */ -extern int dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val); +extern void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val); /* * When DMA mode is enabled specifies whether to use @@ -594,7 +594,7 @@ extern int dwc2_set_param_dma_enable(str * 0 - address DMA * 1 - DMA Descriptor(default, if available) */ -extern int dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val); +extern void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val); /* * Specifies the maximum speed of operation in host and device mode. @@ -604,7 +604,7 @@ extern int dwc2_set_param_dma_desc_enabl * 0 - High Speed (default) * 1 - Full Speed */ -extern int dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val); +extern void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val); #define DWC2_SPEED_PARAM_HIGH 0 #define DWC2_SPEED_PARAM_FULL 1 @@ -615,8 +615,8 @@ extern int dwc2_set_param_speed(struct d * 0 - Don't support low power mode (default) * 1 - Support low power mode */ -extern int dwc2_set_param_host_support_fs_ls_low_power(struct dwc2_hsotg *hsotg, - int val); +extern void dwc2_set_param_host_support_fs_ls_low_power( + struct dwc2_hsotg *hsotg, int val); /* * Specifies the PHY clock rate in low power mode when connected to a @@ -627,8 +627,8 @@ extern int dwc2_set_param_host_support_f * 0 - 48 MHz * 1 - 6 MHz */ -extern int dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, - int val); +extern void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, + int val); #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1 @@ -636,50 +636,50 @@ extern int dwc2_set_param_host_ls_low_po * 0 - Use cC FIFO size parameters * 1 - Allow dynamic FIFO sizing (default) */ -extern int dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, - int val); +extern void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, + int val); /* * Number of 4-byte words in the Rx FIFO in host mode when dynamic * FIFO sizing is enabled. * 16 to 32768 (default 1024) */ -extern int dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val); +extern void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val); /* * Number of 4-byte words in the non-periodic Tx FIFO in host mode * when Dynamic FIFO sizing is enabled in the core. * 16 to 32768 (default 256) */ -extern int dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, - int val); +extern void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, + int val); /* * Number of 4-byte words in the host periodic Tx FIFO when dynamic * FIFO sizing is enabled. * 16 to 32768 (default 256) */ -extern int dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, - int val); +extern void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, + int val); /* * The maximum transfer size supported in bytes. * 2047 to 65,535 (default 65,535) */ -extern int dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val); +extern void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val); /* * The maximum number of packets in a transfer. * 15 to 511 (default 511) */ -extern int dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val); +extern void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val); /* * The number of host channel registers to use. * 1 to 16 (default 11) * Note: The FPGA configuration supports a maximum of 11 host channels. */ -extern int dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val); +extern void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val); /* * Specifies the type of PHY interface to use. By default, the driver @@ -689,7 +689,7 @@ extern int dwc2_set_param_host_channels( * 1 - UTMI+ (default) * 2 - ULPI */ -extern int dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val); +extern void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val); #define DWC2_PHY_TYPE_PARAM_FS 0 #define DWC2_PHY_TYPE_PARAM_UTMI 1 #define DWC2_PHY_TYPE_PARAM_ULPI 2 @@ -705,7 +705,7 @@ extern int dwc2_set_param_phy_type(struc * * 8 or 16 bits (default 16) */ -extern int dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val); +extern void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val); /* * Specifies whether the ULPI operates at double or single @@ -717,13 +717,13 @@ extern int dwc2_set_param_phy_utmi_width * 1 - double data rate ULPI interface with 4 bit wide data * bus */ -extern int dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val); +extern void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val); /* * Specifies whether to use the internal or external supply to * drive the vbus with a ULPI phy. */ -extern int dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val); +extern void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val); #define DWC2_PHY_ULPI_INTERNAL_VBUS 0 #define DWC2_PHY_ULPI_EXTERNAL_VBUS 1 @@ -733,11 +733,11 @@ extern int dwc2_set_param_phy_ulpi_ext_v * 0 - No (default) * 1 - Yes */ -extern int dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val); +extern void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val); -extern int dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val); +extern void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val); -extern int dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val); +extern void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val); /* * Specifies whether dedicated transmit FIFOs are @@ -745,16 +745,14 @@ extern int dwc2_set_param_ts_dline(struc * 0 - No * 1 - Yes */ -extern int dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, - int val); - -extern int dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val); +extern void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, + int val); -extern int dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val); +extern void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val); -extern int dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val); +extern void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val); -extern int dwc2_set_param_uframe_sched(struct dwc2_hsotg *hsotg, int val); +extern void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val); /* * Dump core registers and SPRAM Index: src/sys/external/bsd/dwc2/dist/dwc2_coreintr.c diff -u src/sys/external/bsd/dwc2/dist/dwc2_coreintr.c:1.6 src/sys/external/bsd/dwc2/dist/dwc2_coreintr.c:1.7 --- src/sys/external/bsd/dwc2/dist/dwc2_coreintr.c:1.6 Fri Mar 21 09:19:10 2014 +++ src/sys/external/bsd/dwc2/dist/dwc2_coreintr.c Thu Apr 3 06:34:58 2014 @@ -1,4 +1,4 @@ -/* $NetBSD: dwc2_coreintr.c,v 1.6 2014/03/21 09:19:10 skrll Exp $ */ +/* $NetBSD: dwc2_coreintr.c,v 1.7 2014/04/03 06:34:58 skrll Exp $ */ /* * core_intr.c - DesignWare HS OTG Controller common interrupt handling @@ -41,7 +41,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: dwc2_coreintr.c,v 1.6 2014/03/21 09:19:10 skrll Exp $"); +__KERNEL_RCSID(0, "$NetBSD: dwc2_coreintr.c,v 1.7 2014/04/03 06:34:58 skrll Exp $"); #include <sys/param.h> #include <sys/kernel.h> @@ -67,7 +67,6 @@ __KERNEL_RCSID(0, "$NetBSD: dwc2_coreint #ifdef DWC2_DEBUG static const char *dwc2_op_state_str(struct dwc2_hsotg *hsotg) { -#ifdef DEBUG switch (hsotg->op_state) { case OTG_STATE_A_HOST: return "a_host"; @@ -82,9 +81,26 @@ static const char *dwc2_op_state_str(str default: return "unknown"; } -#else - return ""; -#endif +} + +/** + * dwc2_handle_usb_port_intr - handles OTG PRTINT interrupts. + * When the PRTINT interrupt fires, there are certain status bits in the Host + * Port that needs to get cleared. + * + * @hsotg: Programming view of DWC_otg controller + */ +static void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg) +{ + u32 hprt0 = DWC2_READ_4(hsotg, HPRT0); + + if (hprt0 & HPRT0_ENACHG) { + hprt0 &= ~HPRT0_ENA; + DWC2_WRITE_4(hsotg, HPRT0, hprt0); + } + + /* Clear interrupt */ + DWC2_WRITE_4(hsotg, GINTSTS, GINTSTS_PRTINT); } #endif @@ -434,12 +450,10 @@ static u32 dwc2_read_common_intr(struct gintmsk = DWC2_READ_4(hsotg, GINTMSK); gahbcfg = DWC2_READ_4(hsotg, GAHBCFG); -#ifdef DEBUG /* If any common interrupts set */ if (gintsts & gintmsk_common) dev_dbg(hsotg->dev, "gintsts=%08x gintmsk=%08x\n", gintsts, gintmsk); -#endif if (gahbcfg & GAHBCFG_GLBL_INTR_EN) return gintsts & gintmsk & gintmsk_common; @@ -466,8 +480,8 @@ irqreturn_t dwc2_handle_common_intr(void u32 gintsts; irqreturn_t retval = IRQ_NONE; - if (dwc2_check_core_status(hsotg) < 0) { - dev_warn(hsotg->dev, "Controller is disconnected\n"); + if (!dwc2_is_controller_alive(hsotg)) { + dev_warn(hsotg->dev, "Controller is dead\n"); goto out; } @@ -500,8 +514,7 @@ irqreturn_t dwc2_handle_common_intr(void if (dwc2_is_device_mode(hsotg)) { dev_dbg(hsotg->dev, " --Port interrupt received in Device mode--\n"); - gintsts = GINTSTS_PRTINT; - DWC2_WRITE_4(hsotg, GINTSTS, gintsts); + dwc2_handle_usb_port_intr(hsotg); retval = IRQ_HANDLED; } } Index: src/sys/external/bsd/dwc2/dist/dwc2_hcd.c diff -u src/sys/external/bsd/dwc2/dist/dwc2_hcd.c:1.11 src/sys/external/bsd/dwc2/dist/dwc2_hcd.c:1.12 --- src/sys/external/bsd/dwc2/dist/dwc2_hcd.c:1.11 Fri Mar 21 09:19:10 2014 +++ src/sys/external/bsd/dwc2/dist/dwc2_hcd.c Thu Apr 3 06:34:58 2014 @@ -1,4 +1,4 @@ -/* $NetBSD: dwc2_hcd.c,v 1.11 2014/03/21 09:19:10 skrll Exp $ */ +/* $NetBSD: dwc2_hcd.c,v 1.12 2014/04/03 06:34:58 skrll Exp $ */ /* * hcd.c - DesignWare HS OTG Controller host-mode routines @@ -42,7 +42,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: dwc2_hcd.c,v 1.11 2014/03/21 09:19:10 skrll Exp $"); +__KERNEL_RCSID(0, "$NetBSD: dwc2_hcd.c,v 1.12 2014/04/03 06:34:58 skrll Exp $"); #include <sys/types.h> #include <sys/kmem.h> @@ -400,7 +400,7 @@ dwc2_hcd_urb_enqueue(struct dwc2_hsotg * dwc2_hcd_qtd_init(qtd, urb); retval = dwc2_hcd_qtd_add(hsotg, qtd, (struct dwc2_qh **)ep_handle, mem_flags); - if (retval < 0) { + if (retval) { dev_err(hsotg->dev, "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n", retval); @@ -409,7 +409,7 @@ dwc2_hcd_urb_enqueue(struct dwc2_hsotg * } intr_mask = DWC2_READ_4(hsotg, GINTMSK); - if (!(intr_mask & GINTSTS_SOF) && retval == 0) { + if (!(intr_mask & GINTSTS_SOF)) { enum dwc2_transaction_type tr_type; if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK && @@ -425,7 +425,7 @@ dwc2_hcd_urb_enqueue(struct dwc2_hsotg * dwc2_hcd_queue_transactions(hsotg, tr_type); } - return retval; + return 0; } /* Must be called with interrupt disabled and spinlock held */ @@ -1745,7 +1745,7 @@ int dwc2_hcd_get_frame_number(struct dwc int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg) { - return (hsotg->op_state == OTG_STATE_B_HOST); + return hsotg->op_state == OTG_STATE_B_HOST; } struct dwc2_hcd_urb * Index: src/sys/external/bsd/dwc2/dist/dwc2_hcd.h diff -u src/sys/external/bsd/dwc2/dist/dwc2_hcd.h:1.7 src/sys/external/bsd/dwc2/dist/dwc2_hcd.h:1.8 --- src/sys/external/bsd/dwc2/dist/dwc2_hcd.h:1.7 Tue Nov 12 15:13:14 2013 +++ src/sys/external/bsd/dwc2/dist/dwc2_hcd.h Thu Apr 3 06:34:58 2014 @@ -1,4 +1,4 @@ -/* $NetBSD: dwc2_hcd.h,v 1.7 2013/11/12 15:13:14 skrll Exp $ */ +/* $NetBSD: dwc2_hcd.h,v 1.8 2014/04/03 06:34:58 skrll Exp $ */ /* * hcd.h - DesignWare HS OTG Controller host-mode declarations @@ -460,8 +460,8 @@ static inline u8 dwc2_hcd_is_pipe_out(st extern int dwc2_hcd_init(struct dwc2_hsotg *hsotg, const struct dwc2_core_params *params); extern void dwc2_hcd_remove(struct dwc2_hsotg *hsotg); -extern int dwc2_set_parameters(struct dwc2_hsotg *hsotg, - const struct dwc2_core_params *params); +extern void dwc2_set_parameters(struct dwc2_hsotg *hsotg, + const struct dwc2_core_params *params); extern void dwc2_set_all_params(struct dwc2_core_params *params, int value); extern int dwc2_get_hwparams(struct dwc2_hsotg *hsotg); Index: src/sys/external/bsd/dwc2/dist/dwc2_hcdintr.c diff -u src/sys/external/bsd/dwc2/dist/dwc2_hcdintr.c:1.7 src/sys/external/bsd/dwc2/dist/dwc2_hcdintr.c:1.8 --- src/sys/external/bsd/dwc2/dist/dwc2_hcdintr.c:1.7 Fri Mar 21 09:19:10 2014 +++ src/sys/external/bsd/dwc2/dist/dwc2_hcdintr.c Thu Apr 3 06:34:58 2014 @@ -1,4 +1,4 @@ -/* $NetBSD: dwc2_hcdintr.c,v 1.7 2014/03/21 09:19:10 skrll Exp $ */ +/* $NetBSD: dwc2_hcdintr.c,v 1.8 2014/04/03 06:34:58 skrll Exp $ */ /* * hcd_intr.c - DesignWare HS OTG Controller host-mode interrupt handling @@ -40,7 +40,7 @@ * This file contains the interrupt handlers for Host mode */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: dwc2_hcdintr.c,v 1.7 2014/03/21 09:19:10 skrll Exp $"); +__KERNEL_RCSID(0, "$NetBSD: dwc2_hcdintr.c,v 1.8 2014/04/03 06:34:58 skrll Exp $"); #include <sys/types.h> #include <sys/pool.h> @@ -941,7 +941,7 @@ static int dwc2_xfercomp_isoc_split_in(s frame_desc->actual_length += len; - if (chan->align_buf && len) { + if (chan->align_buf) { dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__); usb_syncmem(qtd->urb->usbdma, 0, qtd->urb->length, BUS_DMASYNC_POSTREAD); @@ -981,8 +981,8 @@ static void dwc2_hc_xfercomp_intr(struct struct dwc2_qtd *qtd) { struct dwc2_hcd_urb *urb = qtd->urb; - int pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info); enum dwc2_halt_status halt_status = DWC2_HC_XFER_COMPLETE; + int pipe_type; int urb_xfer_done; if (dbg_hc(chan)) @@ -990,6 +990,11 @@ static void dwc2_hc_xfercomp_intr(struct "--Host Channel %d Interrupt: Transfer Complete--\n", chnum); + if (!urb) + goto handle_xfercomp_done; + + pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info); + if (hsotg->core_params->dma_desc_enable > 0) { dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, halt_status); if (pipe_type == USB_ENDPOINT_XFER_ISOC) @@ -1011,9 +1016,6 @@ static void dwc2_hc_xfercomp_intr(struct } } - if (!urb) - goto handle_xfercomp_done; - /* Update the QTD and URB states */ switch (pipe_type) { case USB_ENDPOINT_XFER_CONTROL: @@ -1111,7 +1113,7 @@ static void dwc2_hc_stall_intr(struct dw struct dwc2_qtd *qtd) { struct dwc2_hcd_urb *urb = qtd->urb; - int pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info); + int pipe_type; dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: STALL Received--\n", chnum); @@ -1125,6 +1127,8 @@ static void dwc2_hc_stall_intr(struct dw if (!urb) goto handle_stall_halt; + pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info); + if (pipe_type == USB_ENDPOINT_XFER_CONTROL) dwc2_host_complete(hsotg, qtd, -EPIPE); @@ -2060,8 +2064,8 @@ irqreturn_t dwc2_handle_hcd_intr(struct u32 gintsts, dbg_gintsts; irqreturn_t retval = IRQ_NONE; - if (dwc2_check_core_status(hsotg) < 0) { - dev_warn(hsotg->dev, "Controller is disconnected\n"); + if (!dwc2_is_controller_alive(hsotg)) { + dev_warn(hsotg->dev, "Controller is dead\n"); return retval; } Index: src/sys/external/bsd/dwc2/dist/dwc2_hcdqueue.c diff -u src/sys/external/bsd/dwc2/dist/dwc2_hcdqueue.c:1.8 src/sys/external/bsd/dwc2/dist/dwc2_hcdqueue.c:1.9 --- src/sys/external/bsd/dwc2/dist/dwc2_hcdqueue.c:1.8 Fri Mar 21 09:19:10 2014 +++ src/sys/external/bsd/dwc2/dist/dwc2_hcdqueue.c Thu Apr 3 06:34:58 2014 @@ -1,4 +1,4 @@ -/* $NetBSD: dwc2_hcdqueue.c,v 1.8 2014/03/21 09:19:10 skrll Exp $ */ +/* $NetBSD: dwc2_hcdqueue.c,v 1.9 2014/04/03 06:34:58 skrll Exp $ */ /* * hcd_queue.c - DesignWare HS OTG Controller host queuing routines @@ -42,7 +42,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: dwc2_hcdqueue.c,v 1.8 2014/03/21 09:19:10 skrll Exp $"); +__KERNEL_RCSID(0, "$NetBSD: dwc2_hcdqueue.c,v 1.9 2014/04/03 06:34:58 skrll Exp $"); #include <sys/types.h> #include <sys/kmem.h> @@ -366,7 +366,7 @@ static int dwc2_find_single_uframe(struc return i; } } - return -1; + return -ENOSPC; } /* @@ -425,7 +425,7 @@ static int dwc2_find_multi_uframe(struct continue; } } - return -1; + return -ENOSPC; } static int dwc2_find_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) @@ -499,12 +499,12 @@ static int dwc2_schedule_periodic(struct frame = status - 1; /* Set the new frame up */ - if (frame > -1) { + if (frame >= 0) { qh->sched_frame &= ~0x7; qh->sched_frame |= (frame & 7); } - if (status != -1) + if (status > 0) status = 0; } else { status = dwc2_periodic_channel_available(hsotg); @@ -591,7 +591,7 @@ static void dwc2_deschedule_periodic(str */ int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) { - int status = 0; + int status; u32 intr_mask; if (dbg_qh(qh)) @@ -599,26 +599,26 @@ int dwc2_hcd_qh_add(struct dwc2_hsotg *h if (!list_empty(&qh->qh_list_entry)) /* QH already in a schedule */ - return status; + return 0; /* Add the new QH to the appropriate schedule */ if (dwc2_qh_is_non_per(qh)) { /* Always start in inactive schedule */ list_add_tail(&qh->qh_list_entry, &hsotg->non_periodic_sched_inactive); - } else { - status = dwc2_schedule_periodic(hsotg, qh); - if (status == 0) { - if (!hsotg->periodic_qh_count) { - intr_mask = DWC2_READ_4(hsotg, GINTMSK); - intr_mask |= GINTSTS_SOF; - DWC2_WRITE_4(hsotg, GINTMSK, intr_mask); - } - hsotg->periodic_qh_count++; - } + return 0; + } + status = dwc2_schedule_periodic(hsotg, qh); + if (status) + return status; + if (!hsotg->periodic_qh_count) { + intr_mask = DWC2_READ_4(hsotg, GINTMSK); + intr_mask |= GINTSTS_SOF; + DWC2_WRITE_4(hsotg, GINTMSK, intr_mask); } + hsotg->periodic_qh_count++; - return status; + return 0; } /** @@ -643,14 +643,14 @@ void dwc2_hcd_qh_unlink(struct dwc2_hsot hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; list_del_init(&qh->qh_list_entry); - } else { - dwc2_deschedule_periodic(hsotg, qh); - hsotg->periodic_qh_count--; - if (!hsotg->periodic_qh_count) { - intr_mask = DWC2_READ_4(hsotg, GINTMSK); - intr_mask &= ~GINTSTS_SOF; - DWC2_WRITE_4(hsotg, GINTMSK, intr_mask); - } + return; + } + dwc2_deschedule_periodic(hsotg, qh); + hsotg->periodic_qh_count--; + if (!hsotg->periodic_qh_count) { + intr_mask = DWC2_READ_4(hsotg, GINTMSK); + intr_mask &= ~GINTSTS_SOF; + DWC2_WRITE_4(hsotg, GINTMSK, intr_mask); } } @@ -705,6 +705,8 @@ static void dwc2_sched_periodic_split(st void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, int sched_next_periodic_split) { + u16 frame_number; + if (dbg_qh(qh)) dev_vdbg(hsotg->dev, "%s()\n", __func__); @@ -713,37 +715,36 @@ void dwc2_hcd_qh_deactivate(struct dwc2_ if (!list_empty(&qh->qtd_list)) /* Add back to inactive non-periodic schedule */ dwc2_hcd_qh_add(hsotg, qh); - } else { - u16 frame_number = dwc2_hcd_get_frame_number(hsotg); + return; + } - if (qh->do_split) { - dwc2_sched_periodic_split(hsotg, qh, frame_number, - sched_next_periodic_split); - } else { - qh->sched_frame = dwc2_frame_num_inc(qh->sched_frame, - qh->interval); - if (dwc2_frame_num_le(qh->sched_frame, frame_number)) - qh->sched_frame = frame_number; - } + frame_number = dwc2_hcd_get_frame_number(hsotg); - if (list_empty(&qh->qtd_list)) { - dwc2_hcd_qh_unlink(hsotg, qh); - } else { - /* - * Remove from periodic_sched_queued and move to - * appropriate queue - */ - if ((hsotg->core_params->uframe_sched > 0 && - dwc2_frame_num_le(qh->sched_frame, frame_number)) - || (hsotg->core_params->uframe_sched <= 0 && - qh->sched_frame == frame_number)) - list_move(&qh->qh_list_entry, - &hsotg->periodic_sched_ready); - else - list_move(&qh->qh_list_entry, - &hsotg->periodic_sched_inactive); - } + if (qh->do_split) { + dwc2_sched_periodic_split(hsotg, qh, frame_number, + sched_next_periodic_split); + } else { + qh->sched_frame = dwc2_frame_num_inc(qh->sched_frame, + qh->interval); + if (dwc2_frame_num_le(qh->sched_frame, frame_number)) + qh->sched_frame = frame_number; } + + if (list_empty(&qh->qtd_list)) { + dwc2_hcd_qh_unlink(hsotg, qh); + return; + } + /* + * Remove from periodic_sched_queued and move to + * appropriate queue + */ + if ((hsotg->core_params->uframe_sched > 0 && + dwc2_frame_num_le(qh->sched_frame, frame_number)) || + (hsotg->core_params->uframe_sched <= 0 && + qh->sched_frame == frame_number)) + list_move(&qh->qh_list_entry, &hsotg->periodic_sched_ready); + else + list_move(&qh->qh_list_entry, &hsotg->periodic_sched_inactive); } /**