CVS commit: src/sys/arch/arm/arm32

[Matt Thomas]

Module Name:    src
Committed By:   matt
Date:           Fri Apr 11 02:39:03 UTC 2014

Modified Files:
        src/sys/arch/arm/arm32: arm32_tlb.c

Log Message:
Deal with ASID tagged VIVT icaches (not that we have any cpus with them but...)


To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/arm32/arm32_tlb.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.


Modified files:

Index: src/sys/arch/arm/arm32/arm32_tlb.c
diff -u src/sys/arch/arm/arm32/arm32_tlb.c:1.1 src/sys/arch/arm/arm32/arm32_tlb.c:1.2
--- src/sys/arch/arm/arm32/arm32_tlb.c:1.1	Fri Mar 28 21:51:21 2014
+++ src/sys/arch/arm/arm32/arm32_tlb.c	Fri Apr 11 02:39:03 2014
@@ -27,7 +27,7 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: arm32_tlb.c,v 1.1 2014/03/28 21:51:21 matt Exp $");
+__KERNEL_RCSID(1, "$NetBSD: arm32_tlb.c,v 1.2 2014/04/11 02:39:03 matt Exp $");
 
 #include <sys/param.h>
 #include <sys/types.h>
@@ -58,9 +58,18 @@ tlb_set_asid(tlb_asid_t asid)
 void
 tlb_invalidate_all(void)
 {
+	const bool vivt_icache_p = arm_pcache.icache_type == CACHE_TYPE_VIVT;
 	arm_dsb();
 	armreg_tlbiall_write(0);
 	arm_isb();
+	if (__predict_false(vivt_icache_p)) {
+		if (arm_has_tlbiasid_p) {
+			armreg_icialluis_write(0);
+		} else {
+			armreg_iciallu_write(0);
+		}
+	}
+	arm_isb();
 }
 
 void
@@ -72,13 +81,22 @@ tlb_invalidate_globals(void)
 void
 tlb_invalidate_asids(tlb_asid_t lo, tlb_asid_t hi)
 {
+	const bool vivt_icache_p = arm_pcache.icache_type == CACHE_TYPE_VIVT;
 	arm_dsb();
 	if (arm_has_tlbiasid_p) {
-		armreg_tlbiall_write(0);
-	} else {
 		for (; lo <= hi; lo++) {
 			armreg_tlbiasid_write(lo);
 		}
+		arm_isb();
+		if (__predict_false(vivt_icache_p)) {
+			armreg_icialluis_write(0);
+		}
+	} else {
+		armreg_tlbiall_write(0);
+		arm_isb();
+		if (__predict_false(vivt_icache_p)) {
+			armreg_iciallu_write(0);
+		}
 	}
 	arm_isb();
 }