Module Name: src
Committed By: msaitoh
Date: Fri Apr 11 04:42:34 UTC 2014
Modified Files:
src/sys/dev/pci: if_wmreg.h
Log Message:
Fix the definition of CTRL_GIO_M_DIS. This bit is not bit 3 but bit 2.
Reported by pooka@.
To generate a diff of this commit:
cvs rdiff -u -r1.55 -r1.56 src/sys/dev/pci/if_wmreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/pci/if_wmreg.h
diff -u src/sys/dev/pci/if_wmreg.h:1.55 src/sys/dev/pci/if_wmreg.h:1.56
--- src/sys/dev/pci/if_wmreg.h:1.55 Sun Dec 29 21:28:41 2013
+++ src/sys/dev/pci/if_wmreg.h Fri Apr 11 04:42:34 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: if_wmreg.h,v 1.55 2013/12/29 21:28:41 msaitoh Exp $ */
+/* $NetBSD: if_wmreg.h,v 1.56 2014/04/11 04:42:34 msaitoh Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@@ -209,8 +209,8 @@ struct livengood_tcpip_ctxdesc {
#define CTRL_FD (1U << 0) /* full duplex */
#define CTRL_BEM (1U << 1) /* big-endian mode */
#define CTRL_PRIOR (1U << 2) /* 0 = receive, 1 = fair */
+#define CTRL_GIO_M_DIS (1U << 2) /* disabl PCI master access */
#define CTRL_LRST (1U << 3) /* link reset */
-#define CTRL_GIO_M_DIS (1U << 3) /* disabl PCI master access */
#define CTRL_ASDE (1U << 5) /* auto speed detect enable */
#define CTRL_SLU (1U << 6) /* set link up */
#define CTRL_ILOS (1U << 7) /* invert loss of signal */
