Module Name: src
Committed By: matt
Date: Wed Apr 16 07:29:52 UTC 2014
Modified Files:
src/sys/arch/arm/include/arm32: pmap.h
Log Message:
Make to flush the secondary cache when syncing PTEs when the Sheeva L2 cache
is used.
To generate a diff of this commit:
cvs rdiff -u -r1.131 -r1.132 src/sys/arch/arm/include/arm32/pmap.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/include/arm32/pmap.h
diff -u src/sys/arch/arm/include/arm32/pmap.h:1.131 src/sys/arch/arm/include/arm32/pmap.h:1.132
--- src/sys/arch/arm/include/arm32/pmap.h:1.131 Fri Apr 11 04:19:47 2014
+++ src/sys/arch/arm/include/arm32/pmap.h Wed Apr 16 07:29:52 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.h,v 1.131 2014/04/11 04:19:47 matt Exp $ */
+/* $NetBSD: pmap.h,v 1.132 2014/04/16 07:29:52 matt Exp $ */
/*
* Copyright (c) 2002, 2003 Wasabi Systems, Inc.
@@ -503,8 +503,13 @@ extern int pmap_needs_pte_sync;
static inline void
pmap_ptesync(pt_entry_t *ptep, size_t cnt)
{
- if (PMAP_NEEDS_PTE_SYNC)
+ if (PMAP_NEEDS_PTE_SYNC) {
cpu_dcache_wb_range((vaddr_t)ptep, cnt * sizeof(pt_entry_t));
+#ifdef SHEEVA_L2_CACHE
+ cpu_sdcache_wb_range((vaddr_t)ptep, -1,
+ cnt * sizeof(pt_entry_t));
+#endif
+ }
#if ARM_MMU_V7 > 0
__asm("dsb");
#endif
