Module Name: src
Committed By: hkenken
Date: Fri Jul 25 07:49:56 UTC 2014
Modified Files:
src/sys/arch/arm/imx: files.imx51 imx51_ccm.c imx51_ccmreg.h
imx51_ccmvar.h imx51_clock.c imx51_dpllreg.h imx51_gpio.c
imx51_iomuxreg.h imx51_tzic.c imx51_uart.c imx51_usb.c imx51reg.h
imxclock.c imxsdmareg.h imxusb.c imxusbreg.h imxusbvar.h
Added Files:
src/sys/arch/arm/imx: imx50_iomuxreg.h
Log Message:
Add support i.MX50x
* i.MX50 series is e-ink e-reader processor.
To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/arm/imx/files.imx51
cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/imx/imx50_iomuxreg.h
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/imx/imx51_ccm.c \
src/sys/arch/arm/imx/imxusb.c
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/imx/imx51_ccmreg.h \
src/sys/arch/arm/imx/imx51_clock.c src/sys/arch/arm/imx/imx51reg.h
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/imx/imx51_ccmvar.h \
src/sys/arch/arm/imx/imx51_gpio.c src/sys/arch/arm/imx/imx51_iomuxreg.h \
src/sys/arch/arm/imx/imx51_uart.c
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/imx/imx51_dpllreg.h \
src/sys/arch/arm/imx/imx51_usb.c src/sys/arch/arm/imx/imxsdmareg.h \
src/sys/arch/arm/imx/imxusbreg.h src/sys/arch/arm/imx/imxusbvar.h
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/arm/imx/imx51_tzic.c \
src/sys/arch/arm/imx/imxclock.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/imx/files.imx51
diff -u src/sys/arch/arm/imx/files.imx51:1.10 src/sys/arch/arm/imx/files.imx51:1.11
--- src/sys/arch/arm/imx/files.imx51:1.10 Fri Jul 25 07:07:47 2014
+++ src/sys/arch/arm/imx/files.imx51 Fri Jul 25 07:49:56 2014
@@ -1,10 +1,11 @@
-# $NetBSD: files.imx51,v 1.10 2014/07/25 07:07:47 hkenken Exp $
+# $NetBSD: files.imx51,v 1.11 2014/07/25 07:49:56 hkenken Exp $
#
# Configuration info for the Freescale i.MX5x
#
defparam opt_imx.h MEMSIZE
defflag opt_imx.h IMX51
+defflag opt_imx.h IMX50
define bus_dma_generic
@@ -32,7 +33,8 @@ file arch/arm/imx/imx51_clock.c
# Clock Control Module
device imxccm
attach imxccm at axi
-file arch/arm/imx/imx51_ccm.c imxccm needs-flag
+file arch/arm/imx/imx51_ccm.c imxccm needs-flag
+defflag opt_imx51clk.h IMXCCMDEBUG
# frequency of external low frequency clock
# typically 32000, 32768, or 38400.
@@ -63,6 +65,12 @@ device imxiomux : bus_space_generic
attach imxiomux at axi
file arch/arm/imx/imx51_iomux.c imxiomux
+# EPDC controller
+# device epdc : bus_dma_generic, wsemuldisplaydev, rasops16, rasops8, rasops4, rasops_rotation, vcons
+# file arch/arm/imx/imx50_epdc.c epdc needs-flag
+# defflag opt_imx50_epdc.h IMXEPDCCONSOLE
+# defparam opt_imx50_epdc.h EPDC_DEBUG
+
# IPU v3 controller
device ipu : bus_dma_generic, wsemuldisplaydev, rasops16, rasops8, rasops4, rasops_rotation, vcons
file arch/arm/imx/imx51_ipuv3.c ipu needs-flag
Index: src/sys/arch/arm/imx/imx51_ccm.c
diff -u src/sys/arch/arm/imx/imx51_ccm.c:1.5 src/sys/arch/arm/imx/imx51_ccm.c:1.6
--- src/sys/arch/arm/imx/imx51_ccm.c:1.5 Sat Mar 22 09:46:33 2014
+++ src/sys/arch/arm/imx/imx51_ccm.c Fri Jul 25 07:49:56 2014
@@ -1,6 +1,7 @@
-/* $NetBSD: imx51_ccm.c,v 1.5 2014/03/22 09:46:33 hkenken Exp $ */
+/* $NetBSD: imx51_ccm.c,v 1.6 2014/07/25 07:49:56 hkenken Exp $ */
+
/*
- * Copyright (c) 2010, 2011, 2012 Genetec Corporation. All rights reserved.
+ * Copyright (c) 2010-2012, 2014 Genetec Corporation. All rights reserved.
* Written by Hashimoto Kenichi for Genetec Corporation.
*
* Redistribution and use in source and binary forms, with or without
@@ -26,11 +27,16 @@
*/
/*
- * Clock Controller Module (CCM)
+ * Clock Controller Module (CCM) for i.MX5
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: imx51_ccm.c,v 1.5 2014/03/22 09:46:33 hkenken Exp $");
+__KERNEL_RCSID(0, "$NetBSD: imx51_ccm.c,v 1.6 2014/07/25 07:49:56 hkenken Exp $");
+
+#include "opt_imx.h"
+#include "opt_imx51clk.h"
+
+#include "locators.h"
#include <sys/types.h>
#include <sys/time.h>
@@ -47,11 +53,6 @@ __KERNEL_RCSID(0, "$NetBSD: imx51_ccm.c,
#include <arm/imx/imx51var.h>
#include <arm/imx/imx51reg.h>
-#include "opt_imx51clk.h"
-#include "locators.h"
-
-//#define IMXCCMDEBUG
-
#ifndef IMX51_OSC_FREQ
#define IMX51_OSC_FREQ (24 * 1000 * 1000) /* 24MHz */
#endif
@@ -70,6 +71,9 @@ struct imxccm_softc {
struct imxccm_softc *ccm_softc;
static uint64_t imx51_get_pll_freq(u_int);
+#if IMX50
+static uint64_t imx51_get_pfd_freq(u_int);
+#endif
static int imxccm_match(device_t, cfdata_t, void *);
static void imxccm_attach(device_t, device_t, void *);
@@ -122,16 +126,21 @@ imxccm_attach(device_t parent, device_t
imx51_get_pll_freq(2);
imx51_get_pll_freq(3);
-
aprint_verbose_dev(self, "CPU clock=%d, UART clock=%d\n",
imx51_get_clock(IMX51CLK_ARM_ROOT),
imx51_get_clock(IMX51CLK_UART_CLK_ROOT));
- aprint_verbose_dev(self,
+ aprint_verbose_dev(self, "PLL1 clock=%d, PLL2 clock=%d, PLL3 clock=%d\n",
+ imx51_get_clock(IMX51CLK_PLL1),
+ imx51_get_clock(IMX51CLK_PLL2),
+ imx51_get_clock(IMX51CLK_PLL3));
+ aprint_verbose_dev(self,
"mainbus clock=%d, ahb clock=%d ipg clock=%d perclk=%d\n",
imx51_get_clock(IMX51CLK_MAIN_BUS_CLK),
imx51_get_clock(IMX51CLK_AHB_CLK_ROOT),
imx51_get_clock(IMX51CLK_IPG_CLK_ROOT),
imx51_get_clock(IMX51CLK_PERCLK_ROOT));
+ aprint_verbose_dev(self, "ESDHC1 clock=%d\n",
+ imx51_get_clock(IMX51CLK_ESDHC1_CLK_ROOT));
}
@@ -165,17 +174,17 @@ imx51_get_clock(enum imx51_clock clk)
/* FALLTHROUGH */
case IMX51CLK_PLL1STEP:
ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR);
- switch (__SHIFTOUT(ccsr, CCSR_STEP_SEL_MASK)) {
+ switch (__SHIFTOUT(ccsr, CCSR_STEP_SEL)) {
case 0:
return imx51_get_clock(IMX51CLK_LP_APM);
case 1:
return 0; /* XXX PLL bypass clock */
case 2:
return ccm_softc->sc_pll[2-1].pll_freq /
- (1 + __SHIFTOUT(ccsr, CCSR_PLL2_DIV_PODF_MASK));
+ (1 + __SHIFTOUT(ccsr, CCSR_PLL2_DIV_PODF));
case 3:
return ccm_softc->sc_pll[3-1].pll_freq /
- (1 + __SHIFTOUT(ccsr, CCSR_PLL3_DIV_PODF_MASK));
+ (1 + __SHIFTOUT(ccsr, CCSR_PLL3_DIV_PODF));
}
/*NOTREACHED*/
case IMX51CLK_PLL2SW:
@@ -202,11 +211,27 @@ imx51_get_clock(enum imx51_clock clk)
/* ... */
case IMX51CLK_MAIN_BUS_CLK_SRC:
cbcdr = bus_space_read_4(iot, ioh, CCMC_CBCDR);
+#if IMX50
+ switch (__SHIFTOUT(cbcdr, CBCDR_PERIPH_CLK_SEL)) {
+ case 0:
+ freq = imx51_get_clock(IMX51CLK_PLL1SW);
+ break;
+ case 1:
+ freq = imx51_get_clock(IMX51CLK_PLL2SW);
+ break;
+ case 2:
+ freq = imx51_get_clock(IMX51CLK_PLL3SW);
+ break;
+ case 3:
+ freq = imx51_get_clock(IMX51CLK_LP_APM);
+ break;
+ }
+#else
if ((cbcdr & CBCDR_PERIPH_CLK_SEL) == 0)
freq = imx51_get_clock(IMX51CLK_PLL2SW);
else {
cbcmr = bus_space_read_4(iot, ioh, CCMC_CBCMR);
- switch (__SHIFTOUT(cbcmr, CBCMR_PERIPH_APM_SEL_MASK)) {
+ switch (__SHIFTOUT(cbcmr, CBCMR_PERIPH_APM_SEL)) {
case 0:
freq = imx51_get_clock(IMX51CLK_PLL1SW);
break;
@@ -221,27 +246,36 @@ imx51_get_clock(enum imx51_clock clk)
break;
}
}
+#endif
return freq;
case IMX51CLK_MAIN_BUS_CLK:
freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK_SRC);
cdcr = bus_space_read_4(iot, ioh, CCMC_CDCR);
- return freq / __SHIFTOUT(cdcr, CDCR_PERIPH_CLK_DVFS_PODF_MASK);
+ if (cdcr & CDCR_SW_PERIPH_CLK_DIV_REQ)
+ return freq / (1 + __SHIFTOUT(cdcr, CDCR_PERIPH_CLK_DVFS_PODF));
+ else
+ return freq;
case IMX51CLK_AHB_CLK_ROOT:
freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK);
cbcdr = bus_space_read_4(iot, ioh, CCMC_CBCDR);
- return freq / (1 + __SHIFTOUT(cbcdr, CBCDR_AHB_PODF_MASK));
+ return freq / (1 + __SHIFTOUT(cbcdr, CBCDR_AHB_PODF));
case IMX51CLK_IPG_CLK_ROOT:
freq = imx51_get_clock(IMX51CLK_AHB_CLK_ROOT);
cbcdr = bus_space_read_4(iot, ioh, CCMC_CBCDR);
- return freq / (1 + __SHIFTOUT(cbcdr, CBCDR_IPG_PODF_MASK));
+ return freq / (1 + __SHIFTOUT(cbcdr, CBCDR_IPG_PODF));
case IMX51CLK_PERCLK_ROOT:
cbcmr = bus_space_read_4(iot, ioh, CCMC_CBCMR);
if (cbcmr & CBCMR_PERCLK_IPG_SEL)
return imx51_get_clock(IMX51CLK_IPG_CLK_ROOT);
if (cbcmr & CBCMR_PERCLK_LP_APM_SEL)
freq = imx51_get_clock(IMX51CLK_LP_APM);
- else
+ else {
+#ifdef IMX50
+ freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK);
+#else
freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK_SRC);
+#endif
+ }
cbcdr = bus_space_read_4(iot, ioh, CCMC_CBCDR);
@@ -249,9 +283,9 @@ imx51_get_clock(enum imx51_clock clk)
printf("cbcmr=%x cbcdr=%x\n", cbcmr, cbcdr);
#endif
- freq /= 1 + __SHIFTOUT(cbcdr, CBCDR_PERCLK_PRED1_MASK);
- freq /= 1 + __SHIFTOUT(cbcdr, CBCDR_PERCLK_PRED2_MASK);
- freq /= 1 + __SHIFTOUT(cbcdr, CBCDR_PERCLK_PODF_MASK);
+ freq /= 1 + __SHIFTOUT(cbcdr, CBCDR_PERCLK_PRED1);
+ freq /= 1 + __SHIFTOUT(cbcdr, CBCDR_PERCLK_PRED2);
+ freq /= 1 + __SHIFTOUT(cbcdr, CBCDR_PERCLK_PODF);
return freq;
case IMX51CLK_UART_CLK_ROOT:
cscdr1 = bus_space_read_4(iot, ioh, CCMC_CSCDR1);
@@ -261,7 +295,7 @@ imx51_get_clock(enum imx51_clock clk)
printf("cscdr1=%x cscmr1=%x\n", cscdr1, cscmr1);
#endif
- sel = __SHIFTOUT(cscmr1, CSCMR1_UART_CLK_SEL_MASK);
+ sel = __SHIFTOUT(cscmr1, CSCMR1_UART_CLK_SEL);
switch (sel) {
case 0:
@@ -274,11 +308,11 @@ imx51_get_clock(enum imx51_clock clk)
break;
}
- return freq / (1 + __SHIFTOUT(cscdr1, CSCDR1_UART_CLK_PRED_MASK)) /
- (1 + __SHIFTOUT(cscdr1, CSCDR1_UART_CLK_PODF_MASK));
+ return freq / (1 + __SHIFTOUT(cscdr1, CSCDR1_UART_CLK_PRED)) /
+ (1 + __SHIFTOUT(cscdr1, CSCDR1_UART_CLK_PODF));
case IMX51CLK_IPU_HSP_CLK_ROOT:
cbcmr = bus_space_read_4(iot, ioh, CCMC_CBCMR);
- switch (__SHIFTOUT(cbcmr, CBCMR_IPU_HSP_CLK_SEL_MASK)) {
+ switch (__SHIFTOUT(cbcmr, CBCMR_IPU_HSP_CLK_SEL)) {
case 0:
freq = imx51_get_clock(IMX51CLK_ARM_AXI_A_CLK);
break;
@@ -294,6 +328,7 @@ imx51_get_clock(enum imx51_clock clk)
break;
}
return freq;
+#ifdef IMX50
case IMX51CLK_ESDHC2_CLK_ROOT:
case IMX51CLK_ESDHC4_CLK_ROOT:
cscmr1 = bus_space_read_4(iot, ioh, CCMC_CSCMR1);
@@ -331,6 +366,18 @@ imx51_get_clock(enum imx51_clock clk)
case 3:
freq = imx51_get_clock(IMX51CLK_LP_APM);
break;
+ case 4:
+ /* PFD0 XXX */
+ break;
+ case 5:
+ /* PFD1 XXX */
+ break;
+ case 6:
+ /* PFD4 XXX */
+ break;
+ case 7:
+ /* osc_clk XXX */
+ break;
}
if (clk == IMX51CLK_ESDHC1_CLK_ROOT)
@@ -340,6 +387,54 @@ imx51_get_clock(enum imx51_clock clk)
freq = freq / (1 + __SHIFTOUT(cscdr1, CSCDR1_ESDHC3_CLK_PRED)) /
(1 + __SHIFTOUT(cscdr1, CSCDR1_ESDHC3_CLK_PODF));
return freq;
+#else
+ case IMX51CLK_ESDHC3_CLK_ROOT:
+ case IMX51CLK_ESDHC4_CLK_ROOT:
+ cscmr1 = bus_space_read_4(iot, ioh, CCMC_CSCMR1);
+
+ sel = 0;
+ if (clk == IMX51CLK_ESDHC3_CLK_ROOT)
+ sel = __SHIFTOUT(cscmr1, CSCMR1_ESDHC3_CLK_SEL);
+ else if (clk == IMX51CLK_ESDHC4_CLK_ROOT)
+ sel = __SHIFTOUT(cscmr1, CSCMR1_ESDHC4_CLK_SEL);
+
+ if (sel == 0)
+ freq = imx51_get_clock(IMX51CLK_ESDHC1_CLK_ROOT);
+ else
+ freq = imx51_get_clock(IMX51CLK_ESDHC2_CLK_ROOT);
+
+ return freq;
+ case IMX51CLK_ESDHC1_CLK_ROOT:
+ case IMX51CLK_ESDHC2_CLK_ROOT:
+
+ cscdr1 = bus_space_read_4(iot, ioh, CCMC_CSCDR1);
+ cscmr1 = bus_space_read_4(iot, ioh, CCMC_CSCMR1);
+
+ sel = 0;
+ if (clk == IMX51CLK_ESDHC1_CLK_ROOT)
+ sel = __SHIFTOUT(cscmr1, CSCMR1_ESDHC1_CLK_SEL);
+ else if (clk == IMX51CLK_ESDHC2_CLK_ROOT)
+ sel = __SHIFTOUT(cscmr1, CSCMR1_ESDHC2_CLK_SEL);
+
+ switch (sel) {
+ case 0:
+ case 1:
+ case 2:
+ freq = imx51_get_clock(IMX51CLK_PLL1SW + sel);
+ break;
+ case 3:
+ freq = imx51_get_clock(IMX51CLK_LP_APM);
+ break;
+ }
+
+ if (clk == IMX51CLK_ESDHC1_CLK_ROOT)
+ freq = freq / (1 + __SHIFTOUT(cscdr1, CSCDR1_ESDHC1_CLK_PRED)) /
+ (1 + __SHIFTOUT(cscdr1, CSCDR1_ESDHC1_CLK_PODF));
+ else if (clk == IMX51CLK_ESDHC2_CLK_ROOT)
+ freq = freq / (1 + __SHIFTOUT(cscdr1, CSCDR1_ESDHC2_CLK_PRED)) /
+ (1 + __SHIFTOUT(cscdr1, CSCDR1_ESDHC2_CLK_PODF));
+ return freq;
+#endif
case IMX51CLK_CSPI_CLK_ROOT:
cscmr1 = bus_space_read_4(iot, ioh, CCMC_CSCMR1);
cscdr2 = bus_space_read_4(iot, ioh, CCMC_CSCDR2);
@@ -360,6 +455,18 @@ imx51_get_clock(enum imx51_clock clk)
(1 + __SHIFTOUT(cscdr2, CSCDR2_ECSPI_CLK_PODF));
return freq;
+#if IMX50
+ case IMX50CLK_PFD0_CLK_ROOT:
+ case IMX50CLK_PFD1_CLK_ROOT:
+ case IMX50CLK_PFD2_CLK_ROOT:
+ case IMX50CLK_PFD3_CLK_ROOT:
+ case IMX50CLK_PFD4_CLK_ROOT:
+ case IMX50CLK_PFD5_CLK_ROOT:
+ case IMX50CLK_PFD6_CLK_ROOT:
+ case IMX50CLK_PFD7_CLK_ROOT:
+ freq = imx51_get_pfd_freq(clk - IMX50CLK_PFD0_CLK_ROOT);
+ return freq;
+#endif
default:
aprint_error_dev(ccm_softc->sc_dev,
"clock %d: not supported yet\n", clk);
@@ -367,6 +474,13 @@ imx51_get_clock(enum imx51_clock clk)
}
}
+#ifdef IMX50
+static uint64_t
+imx51_get_pfd_freq(u_int pfd_no)
+{
+ return 480000000;
+}
+#endif
static uint64_t
imx51_get_pll_freq(u_int pll_no)
@@ -399,8 +513,8 @@ imx51_get_pll_freq(u_int pll_no)
dp_mfn = bus_space_read_4(iot, ioh, DPLL_DP_MFN);
}
- pdf = dp_op & DP_OP_PDF_MASK;
- mfi = max(5, __SHIFTOUT(dp_op, DP_OP_MFI_MASK));
+ pdf = dp_op & DP_OP_PDF;
+ mfi = max(5, __SHIFTOUT(dp_op, DP_OP_MFI));
mfd = dp_mfd;
if (dp_mfn & __BIT(26))
/* 27bit signed value */
@@ -408,7 +522,7 @@ imx51_get_pll_freq(u_int pll_no)
else
mfn = dp_mfn;
- switch (dp_ctrl & DP_CTL_REF_CLK_SEL_MASK) {
+ switch (dp_ctrl & DP_CTL_REF_CLK_SEL) {
case DP_CTL_REF_CLK_SEL_COSC:
/* Internal Oscillator */
ref = IMX51_OSC_FREQ;
@@ -475,4 +589,100 @@ imx51_clk_gating(int clk_src, int mode)
reg &= ~(0x03 << field * 2);
reg |= bit;
bus_space_write_4(iot, ioh, CCMC_CCGR(group), reg);
+
+#ifdef IMX50
+ switch (clk_src) {
+ case CCGR_EPDC_AXI_CLK:
+ reg = bus_space_read_4(iot, ioh, CCMC_EPDC_AXI);
+ reg &= ~EPDC_AXI_CLKGATE;
+ reg |= EPDC_AXI_CLKGATE_ALLWAYS;
+ bus_space_write_4(iot, ioh, CCMC_EPDC_AXI, reg);
+
+ /* enable auto-slow */
+ reg |= EPDC_ASM_EN;
+ reg |= __SHIFTIN(5, EPDC_ASM_SLOW_DIV);
+ bus_space_write_4(iot, ioh, CCMC_EPDC_AXI, reg);
+
+ break;
+ case CCGR_EPDC_PIX_CLK:
+ reg = bus_space_read_4(iot, ioh, CCMC_EPDC_PIX);
+ reg &= ~EPDC_PIX_CLKGATE;
+ reg |= EPDC_PIX_CLKGATE_ALLWAYS;
+ bus_space_write_4(iot, ioh, CCMC_EPDC_PIX, reg);
+
+ break;
+ }
+#endif
+}
+
+void
+imx51_clk_rate(int clk_src, int clk_base, int rate)
+{
+#ifdef IMX50
+ bus_space_tag_t iot = ccm_softc->sc_iot;
+ bus_space_handle_t ioh = ccm_softc->sc_ioh;
+ uint32_t reg;
+ int div;
+ uint64_t freq = 0;
+
+ switch (clk_src) {
+ case CCGR_EPDC_AXI_CLK:
+ reg = bus_space_read_4(iot, ioh, CCMC_CLKSEQ_BYPASS);
+ reg &= ~CLKSEQ_EPDC_AXI_CLK;
+ reg |= __SHIFTIN(clk_base, CLKSEQ_EPDC_AXI_CLK);
+ bus_space_write_4(iot, ioh, CCMC_CLKSEQ_BYPASS, reg);
+
+ switch (clk_base) {
+ case CLKSEQ_XTAL:
+ freq = 24000000;
+ break;
+ case CLKSEQ_PFDx:
+ freq = imx51_get_clock(IMX50CLK_PFD3_CLK_ROOT);
+ break;
+ case CLKSEQ_PLL1:
+ freq = imx51_get_clock(IMX51CLK_PLL1);
+ break;
+ }
+
+ div = max(1, freq / rate);
+
+ reg = bus_space_read_4(iot, ioh, CCMC_EPDC_AXI);
+ reg &= ~EPDC_AXI_DIV;
+ reg |= __SHIFTIN(div, EPDC_AXI_DIV);
+ bus_space_write_4(iot, ioh, CCMC_EPDC_AXI, reg);
+ while (bus_space_read_4(iot, ioh, CCMC_CSR2) & CSR2_EPDC_AXI_BUSY)
+ ; /* wait */
+ break;
+ case CCGR_EPDC_PIX_CLK:
+ reg = bus_space_read_4(iot, ioh, CCMC_CLKSEQ_BYPASS);
+ reg &= ~CLKSEQ_EPDC_PIX_CLK;
+ reg |= __SHIFTIN(clk_base, CLKSEQ_EPDC_PIX_CLK);
+ bus_space_write_4(iot, ioh, CCMC_CLKSEQ_BYPASS, reg);
+
+ switch (clk_base) {
+ case CLKSEQ_XTAL:
+ freq = 24000000;
+ break;
+ case CLKSEQ_PFDx:
+ freq = imx51_get_clock(IMX50CLK_PFD5_CLK_ROOT);
+ break;
+ case CLKSEQ_PLL1:
+ freq = imx51_get_clock(IMX51CLK_PLL1);
+ break;
+ case CLKSEQ_CAMP1:
+ /* XXX */
+ freq = 0;
+ break;
+ }
+
+ div = freq / rate;
+ reg = bus_space_read_4(iot, ioh, CCMC_EPDC_PIX);
+ reg &= ~EPDC_PIX_CLK_PRED;
+ reg |= __SHIFTIN(div, EPDC_PIX_CLK_PRED);
+ bus_space_write_4(iot, ioh, CCMC_EPDC_PIX, reg);
+ while (bus_space_read_4(iot, ioh, CCMC_CSR2) & CSR2_EPDC_PIX_BUSY)
+ ; /* wait */
+ break;
+ }
+#endif
}
Index: src/sys/arch/arm/imx/imxusb.c
diff -u src/sys/arch/arm/imx/imxusb.c:1.5 src/sys/arch/arm/imx/imxusb.c:1.6
--- src/sys/arch/arm/imx/imxusb.c:1.5 Mon Oct 7 17:36:40 2013
+++ src/sys/arch/arm/imx/imxusb.c Fri Jul 25 07:49:56 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: imxusb.c,v 1.5 2013/10/07 17:36:40 matt Exp $ */
+/* $NetBSD: imxusb.c,v 1.6 2014/07/25 07:49:56 hkenken Exp $ */
/*
* Copyright (c) 2009, 2010 Genetec Corporation. All rights reserved.
* Written by Hashimoto Kenichi and Hiroyuki Bessho for Genetec Corporation.
@@ -25,7 +25,9 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: imxusb.c,v 1.5 2013/10/07 17:36:40 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: imxusb.c,v 1.6 2014/07/25 07:49:56 hkenken Exp $");
+
+#include "opt_imx.h"
#include <sys/param.h>
#include <sys/systm.h>
@@ -117,9 +119,8 @@ imxehci_attach(device_t parent, device_t
aprint_normal_dev(self,
"i.MX USB Controller id=%d revision=%d HCI revision=0x%x\n",
- id & (uint32_t)IMXUSB_ID_ID_MASK,
- (id & (uint32_t)IMXUSB_ID_REVISION_MASK) >>
- IMXUSB_ID_REVISION_SHIFT,
+ (int)__SHIFTOUT(id, IMXUSB_ID_ID),
+ (int)__SHIFTOUT(id, IMXUSB_ID_REVISION),
hcirev);
hwhost = bus_space_read_4(iot, sc->sc_ioh, IMXUSB_HWHOST);
@@ -129,16 +130,14 @@ imxehci_attach(device_t parent, device_t
comma = "";
if (hwhost & HWHOST_HC) {
- int n_ports = 1 + ((hwhost & HWHOST_NPORT_MASK) >>
- HWHOST_NPORT_SHIFT);
+ int n_ports = 1 + __SHIFTOUT(hwhost, HWHOST_NPORT);
aprint_normal("%d host port%s",
n_ports, n_ports > 1 ? "s" : "");
comma = ", ";
}
if (hwdevice & HWDEVICE_DC) {
- int n_endpoints = (hwdevice & HWDEVICE_DEVEP_MASK) >>
- HWDEVICE_DEVEP_SHIFT;
+ int n_endpoints = __SHIFTOUT(hwdevice, HWDEVICE_DEVEP);
aprint_normal("%sdevice capable, %d endpoint%s",
comma,
n_endpoints, n_endpoints > 1 ? "s" : "");
@@ -176,7 +175,15 @@ imxehci_attach(device_t parent, device_t
if (usbc->sc_setup_md_hook)
usbc->sc_setup_md_hook(sc, IMXUSB_HOST);
- else if (sc->sc_iftype == IMXUSBC_IF_ULPI) {
+
+ if (sc->sc_iftype == IMXUSBC_IF_ULPI) {
+#if 0
+ if(hsc->sc_bus.usbrev == USBREV_2_0)
+ ulpi_write(hsc, ULPI_FUNCTION_CONTROL + ULPI_REG_CLEAR, (1 << 0));
+ else
+ ulpi_write(hsc, ULPI_FUNCTION_CONTROL + ULPI_REG_SET, (1 << 2));
+#endif
+
imxusb_ulpi_write(sc, ULPI_FUNCTION_CONTROL + ULPI_REG_CLEAR,
OTG_CONTROL_IDPULLUP);
@@ -216,7 +223,23 @@ imxehci_select_interface(struct imxehci_
struct ehci_softc *hsc = &sc->sc_hsc;
reg = EOREAD4(hsc, EHCI_PORTSC(1));
- reg = (reg & ~PORTSC_PTS_MASK) | (interface << PORTSC_PTS_SHIFT);
+ reg &= ~(PORTSC_PTS | PORTSC_PTW);
+ switch (interface) {
+ case IMXUSBC_IF_UTMI_WIDE:
+ reg |= PORTSC_PTW_16;
+ case IMXUSBC_IF_UTMI:
+ reg |= PORTSC_PTS_UTMI;
+ break;
+ case IMXUSBC_IF_PHILIPS:
+ reg |= PORTSC_PTS_PHILIPS;
+ break;
+ case IMXUSBC_IF_ULPI:
+ reg |= PORTSC_PTS_ULPI;
+ break;
+ case IMXUSBC_IF_SERIAL:
+ reg |= PORTSC_PTS_SERIAL;
+ break;
+ }
EOWRITE4(hsc, EHCI_PORTSC(1), reg);
}
@@ -278,12 +301,12 @@ imxusb_ulpi_read(struct imxehci_softc *s
ulpi_wakeup(sc, TIMEOUT);
- data = ULPI_RUN | (addr << ULPI_ADDR_SHIFT);
+ data = ULPI_RUN | __SHIFTIN(addr, ULPI_ADDR);
bus_space_write_4(sc->sc_iot, sc->sc_ioh, IMXUSB_ULPIVIEW, data);
data = ulpi_wait(sc, TIMEOUT);
- return (data & ULPI_DATRD_MASK) >> ULPI_DATRD_SHIFT;
+ return __SHIFTOUT(data, ULPI_DATRD);
}
void
@@ -293,7 +316,7 @@ imxusb_ulpi_write(struct imxehci_softc *
ulpi_wakeup(sc, TIMEOUT);
- reg = ULPI_RUN | ULPI_RW | ((addr) << ULPI_ADDR_SHIFT) | data;
+ reg = ULPI_RUN | ULPI_RW | __SHIFTIN(addr, ULPI_ADDR) | __SHIFTIN(data, ULPI_DATWR);
bus_space_write_4(sc->sc_iot, sc->sc_ioh, IMXUSB_ULPIVIEW, reg);
ulpi_wait(sc, TIMEOUT);
@@ -402,6 +425,6 @@ imxehci_host_mode(struct imxehci_softc *
bus_space_write_4(sc->sc_iot, sc->sc_ioh, IMXUSB_OTGSC, reg);
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, IMXUSB_OTGMODE);
- reg |= USBMODE_HOST;
+ reg |= USBMODE_CM_HOST;
bus_space_write_4(sc->sc_iot, sc->sc_ioh, IMXUSB_OTGMODE, reg);
}
Index: src/sys/arch/arm/imx/imx51_ccmreg.h
diff -u src/sys/arch/arm/imx/imx51_ccmreg.h:1.4 src/sys/arch/arm/imx/imx51_ccmreg.h:1.5
--- src/sys/arch/arm/imx/imx51_ccmreg.h:1.4 Sat Mar 22 09:46:33 2014
+++ src/sys/arch/arm/imx/imx51_ccmreg.h Fri Jul 25 07:49:56 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: imx51_ccmreg.h,v 1.4 2014/03/22 09:46:33 hkenken Exp $ */
+/* $NetBSD: imx51_ccmreg.h,v 1.5 2014/07/25 07:49:56 hkenken Exp $ */
/*
* Copyright (c) 2011, 2012 Genetec Corporation. All rights reserved.
* Written by Hashimoto Kenichi for Genetec Corporation.
@@ -31,8 +31,8 @@
/* register offset address */
-#define CCMC_BASE 0x73fd4000
#define CCMC_IMX6_BASE 0x020c4040
+
#define CCMC_CCR 0x0000
#define CCR_FPM_MULT __BIT(12)
#define CCR_COSC_EN __BIT(12)
@@ -40,91 +40,135 @@
#define CCMC_CSR 0x0008
#define CCMC_CCSR 0x000c
#define CCSR_LP_APM __BIT(9)
-#define CCSR_STEP_SEL_SHIFT 7
-#define CCSR_STEP_SEL_MASK __BITS(8,CCSR_STEP_SEL_SHIFT)
-#define CCSR_PLL2_DIV_PODF_SHIFT 5
-#define CCSR_PLL2_DIV_PODF_MASK __BITS(6, CCSR_PLL2_DIV_PODF_SHIFT)
-#define CCSR_PLL3_DIV_PODF_SHIFT 3
-#define CCSR_PLL3_DIV_PODF_MASK __BITS(4, CCSR_PLL2_DIV_PODF_SHIFT)
+#define CCSR_STEP_SEL __BITS(8, 7)
+#define CCSR_PLL2_DIV_PODF __BITS(6, 5)
+#define CCSR_PLL3_DIV_PODF __BITS(4, 3)
#define CCSR_PLL1_SW_CLK_SEL __BIT(2)
#define CCSR_PLL2_SW_CLK_SEL __BIT(1)
#define CCSR_PLL3_SW_CLK_SEL __BIT(0)
#define CCMC_CACRR 0x0010
#define CCMC_CBCDR 0x0014
#define CBCDR_DDR_HIGH_FREQ_CLK_SEL __BIT(30)
-#define CBCDR_DDR_CLK_PODF_SHIFT 27
-#define CBCDR_DDR_CLK_PODF_MASK __BITS(29, CBCDR_DDR_CLK_PODF_SHIFT)
-#define CDCDR_PERIPH_CLK2 __BITS(29, 27)
+#define CBCDR_DDR_CLK_PODF __BITS(29, 27)
+#ifdef IMX50
+#define CBCDR_PERIPH_CLK_SEL __BITS(26, 25)
+#else
#define CBCDR_EMI_CLK_SEL __BIT(26)
-#define CBCDR_PERIPH_CLK_SEL __BIT(25)
-#define CBCDR_EMI_SLOW_PODF_SHIFT 22
-#define CBCDR_EMI_SLOW_PODF_MASK __BITS(24, CBCDR_EMI_SLOW_PODF_SHIFT)
-#define CBCDR_AXI_B_PODF_SHIFT 19
-#define CBCDR_AXI_B_PODF_MASK __BITS(21, CBCDR_AXI_B_PODF_SHIFT)
-#define CBCDR_AXI_A_PODF_SHIFT 16
-#define CBCDR_AXI_A_PODF_MASK __BITS(28, CBCDR_AXI_A_PODF_SHIFT)
-#define CBCDR_NFC_PODF_SHIFT 13
-#define CBCDR_NFC_PODF_MASK __BITS(15, CBCDR_AXI_A_PODF_SHIFT)
-#define CBCDR_AHB_PODF_SHIFT 10
-#define CBCDR_AHB_PODF_MASK __BITS(12, CBCDR_AHB_PODF_SHIFT)
-#define CBCDR_IPG_PODF_SHIFT 8
-#define CBCDR_IPG_PODF_MASK __BITS(9, CBCDR_IPG_PODF_SHIFT)
-#define CBCDR_PERCLK_PRED1_SHIFT 6
-#define CBCDR_PERCLK_PRED1_MASK __BITS(7, CBCDR_PERCLK_PRED1_SHIFT)
-#define CBCDR_PERCLK_PRED2_SHIFT 3
-#define CBCDR_PERCLK_PRED2_MASK __BITS(5, CBCDR_PERCLK_PRED2_SHIFT)
-#define CBCDR_PERCLK_PODF_SHIFT 0
-#define CBCDR_PERCLK_PODF_MASK __BITS(2, CBCDR_PERCLK_PODF_SHIFT)
-#define CCMC_CBCMR 0x0018
-#define CBCMR_PERIPH_APM_SEL_SHIFT 12
-#define CBCMR_PERIPH_APM_SEL_MASK __BITS(13, CBCMR_PERIPH_APM_SEL_SHIFT)
-#define CBCMR_IPU_HSP_CLK_SEL_SHIFT 6
-#define CBCMR_IPU_HSP_CLK_SEL_MASK __BITS(7, CBCMR_IPU_HSP_CLK_SEL_SHIFT)
+#define CBCDR_PERIPH_CLK_SEL __BIT(25)
+#endif
+#define CBCDR_EMI_SLOW_PODF __BITS(24, 22)
+#define CBCDR_AXI_B_PODF __BITS(21, 19)
+#define CBCDR_AXI_A_PODF __BITS(18, 16)
+#define CBCDR_NFC_PODF __BITS(15, 13)
+#define CBCDR_AHB_PODF __BITS(12, 10)
+#define CBCDR_IPG_PODF __BITS(9, 8)
+#define CBCDR_PERCLK_PRED1 __BITS(7, 6)
+#define CBCDR_PERCLK_PRED2 __BITS(5, 3)
+#define CBCDR_PERCLK_PODF __BITS(2, 0)
+#define CCMC_CBCMR 0x0018
+#define CBCMR_PERIPH_APM_SEL __BITS(13, 12)
+#define CBCMR_IPU_HSP_CLK_SEL __BITS(7, 6)
#define CBCMR_PERCLK_LP_APM_SEL __BIT(1)
#define CBCMR_PERCLK_IPG_SEL __BIT(0)
-#define CCMC_CSCMR1 0x001c
-#define CSCMR1_UART_CLK_SEL_SHIFT 24
-#define CSCMR1_UART_CLK_SEL_MASK __BITS(25, CSCMR1_UART_CLK_SEL_SHIFT)
+#define CCMC_CSCMR1 0x001c
+#define CSCMR1_UART_CLK_SEL __BITS(25, 24)
+#ifdef IMX50
#define CSCMR1_ESDHC1_CLK_SEL __BITS(22, 21)
#define CSCMR1_ESDHC2_CLK_SEL __BIT(20)
#define CSCMR1_ESDHC4_CLK_SEL __BIT(19)
#define CSCMR1_ESDHC3_CLK_SEL __BITS(18, 16)
+#else
+#define CSCMR1_ESDHC1_CLK_SEL __BITS(21, 20)
+#define CSCMR1_ESDHC3_CLK_SEL __BIT(19)
+#define CSCMR1_ESDHC4_CLK_SEL __BIT(18)
+#define CSCMR1_ESDHC2_CLK_SEL __BITS(17, 16)
+#endif
#define CSCMR1_CSPI_CLK_SEL __BITS(5, 4)
-#define CCMC_CSCMR2 0x0020
-#define CCMC_CSCDR1 0x0024
+#define CCMC_CSCMR2 0x0020
+#define CCMC_CSCDR1 0x0024
+#ifdef IMX50
#define CSCDR1_ESDHC3_CLK_PRED __BITS(24, 22)
#define CSCDR1_ESDHC3_CLK_PODF __BITS(21, 19)
+#else
+#define CSCDR1_ESDHC2_CLK_PRED __BITS(24, 22)
+#define CSCDR1_ESDHC2_CLK_PODF __BITS(21, 19)
+#endif
#define CSCDR1_ESDHC1_CLK_PRED __BITS(18, 16)
#define CSCDR1_ESDHC1_CLK_PODF __BITS(13, 11)
-#define CSCDR1_UART_CLK_PRED_SHIFT 3
-#define CSCDR1_UART_CLK_PRED_MASK __BITS(5, CSCDR1_UART_CLK_PRED_SHIFT)
-#define CSCDR1_UART_CLK_PODF_SHIFT 0
-#define CSCDR1_UART_CLK_PODF_MASK __BITS(2, CSCDR1_UART_CLK_PODF_SHIFT)
-#define CCMC_CS1CDR 0x0028
-#define CCMC_CS2CDR 0x002c
-#define CCMC_CDCDR 0x0030
-#define CCMC_CHSCCDR 0x0034 // i.MX6
-#define CCMC_CSCDR2 0x0038
+#define CSCDR1_UART_CLK_PRED __BITS(5, 3)
+#define CSCDR1_UART_CLK_PODF __BITS(2, 0)
+#define CCMC_CS1CDR 0x0028
+#define CCMC_CS2CDR 0x002c
+#define CCMC_CDCDR 0x0030
+#define CDCDR_PERIPH_CLK2 __BITS(29, 27)
+#define CCMC_CHSCCDR 0x0034 // i.MX6
+#define CCMC_CSCDR2 0x0038
#define CSCDR2_ECSPI_CLK_PRED __BITS(27, 25)
#define CSCDR2_ECSPI_CLK_PODF __BITS(24, 19)
-#define CCMC_CSCDR3 0x003c
-#define CCMC_CSCDR4 0x0040
-#define CCMC_CWDR 0x0044
-#define CCMC_CDHIPR 0x0048
-#define CCMC_CDCR 0x004c
-#define CDCR_PERIPH_CLK_DVFS_PODF_SHIFT 0
-#define CDCR_PERIPH_CLK_DVFS_PODF_MASK \
- __BITS(1,CDCR_PERIPH_CLK_DVFS_PODF_SHIFT)
-#define CCMC_CTOR 0x0050
-#define CCMC_CLPCR 0x0054
-#define CCMC_CISR 0x0058
-#define CCMC_CIMR 0x005c
-#define CCMC_CCOSR 0x0060
-#define CCMC_CGPR 0x0064
-#define CCMC_CCGR(n) (0x0068 + (n) * 4)
-#define CCMC_CMEOR 0x0084
+#define CCMC_CSCDR3 0x003c
+#define CCMC_CSCDR4 0x0040
+#define CCMC_CWDR 0x0044
+#define CCMC_CDHIPR 0x0048
+#define CCMC_CDCR 0x004c
+#define CDCR_SW_PERIPH_CLK_DIV_REQ __BIT(6)
+#define CDCR_PERIPH_CLK_DVFS_PODF __BITS(1, 0)
+#define CCMC_CTOR 0x0050
+#define CCMC_CLPCR 0x0054
+#define CCMC_CISR 0x0058
+#define CCMC_CIMR 0x005c
+#define CCMC_CCOSR 0x0060
+#define CCMC_CGPR 0x0064
+#define CCMC_CCGR(n) (0x0068 + (n) * 4)
+#define CCMC_CMEOR 0x0084
+#ifdef IMX50
+#define CCMC_CSR2 0x008C
+#define CSR2_EPDC_ASM_ACTIVE __BIT(13)
+#define CSR2_EPXP_ASM_ACTIVE __BIT(12)
+#define CSR2_ELCDIF_ASM_ACTIVE __BIT(11)
+#define CSR2_SYS_CLK_XTAL_ACTIVE __BIT(10)
+#define CSR2_ELCDIF_PIX_BUSY __BIT(9)
+#define CSR2_EPDC_PIX_BUSY __BIT(8)
+#define CSR2_MSHC_XMSCKI_BUSY __BIT(7)
+#define CSR2_BCH_BUSY __BIT(6)
+#define CSR2_GPMI_BUSY __BIT(5)
+#define CSR2_EPDC_AXI_BUSY __BIT(4)
+#define CSR2_DISPLAY_AXI_BUSY __BIT(3)
+#define CSR2_DDR_CLK_REF_PLL_BUSY __BIT(2)
+#define CSR2_SYS_CLK_REF_PLL_BUSY __BIT(1)
+#define CSR2_SYS_CLK_REF_XTAL_BUSY __BIT(0)
+#define CCMC_CLKSEQ_BYPASS 0x0090
+#define CLKSEQ_ELCDIF_PIX_CLK __BITS(15, 14)
+#define CLKSEQ_EPDC_PIX_CLK __BITS(13, 12)
+#define CLKSEQ_MSHC_XMSCKI_CLK __BITS(11, 10)
+#define CLKSEQ_BCH_CLK __BITS(9, 8)
+#define CLKSEQ_GPMI_CLK __BITS(7, 6)
+#define CLKSEQ_EPDC_AXI_CLK __BITS(5, 4)
+#define CLKSEQ_DISPLAY_AXI_CLK __BITS(3, 2)
+#define CLKSEQ_SYS_CLK __BITS(1, 0)
+#define CLKSEQ_XTAL 0
+#define CLKSEQ_PFDx 1
+#define CLKSEQ_PLL1 2
+#define CLKSEQ_CAMP1 3
+#define CCMC_EPDC_PIX 0x00A0
+#define EPDC_PIX_CLKGATE __BITS(31, 30)
+#define EPDC_PIX_CLKGATE_OFF __SHIFTIN(0, EPDC_AXI_CLKGATE)
+#define EPDC_PIX_CLKGATE_RUNMODE __SHIFTIN(1, EPDC_AXI_CLKGATE)
+#define EPDC_PIX_CLKGATE_ALLWAYS __SHIFTIN(2, EPDC_AXI_CLKGATE)
+#define EPDC_PIX_CLKGATE_EXCEPTSTOP __SHIFTIN(3, EPDC_AXI_CLKGATE)
+#define EPDC_PIX_CLK_PRED __BITS(13, 12)
+#define EPDC_PIX_CLK_PODF __BITS(11, 0)
+#define CCMC_EPDC_AXI 0x00A8
+#define EPDC_AXI_CLKGATE __BITS(31, 30)
+#define EPDC_AXI_CLKGATE_OFF __SHIFTIN(0, EPDC_AXI_CLKGATE)
+#define EPDC_AXI_CLKGATE_RUNMODE __SHIFTIN(1, EPDC_AXI_CLKGATE)
+#define EPDC_AXI_CLKGATE_ALLWAYS __SHIFTIN(2, EPDC_AXI_CLKGATE)
+#define EPDC_AXI_CLKGATE_EXCEPTSTOP __SHIFTIN(3, EPDC_AXI_CLKGATE)
+#define EPDC_ASM_EN __BIT(9)
+#define EPDC_ASM_SLOW_DIV __BITS(8, 6)
+#define EPDC_AXI_DIV __BITS(5, 0)
+#endif
-#define CCMC_SIZE 0x88
+#define CCMC_SIZE 0x0100
/* CCGR Clock Gate Register */
@@ -132,7 +176,15 @@
#define CCMR_CCGR_NGROUPS 7
#define CCMR_CCGR_MODULE(clk) ((clk) / CCMR_CCGR_NSOURCE)
#define __CCGR_NUM(a, b) ((a) * 16 + (b))
+#define CCGR_MODE_CLKOFF 0x0
+#define CCGR_MODE_CLKON 0x2
+#ifdef IMX50
+#define CCGR_USBOH1_CLK __CCGR_NUM(2, 13)
+#define CCGR_USBPHY1_CLK __CCGR_NUM(4, 5)
+#define CCGR_EPDC_PIX_CLK __CCGR_NUM(6, 5)
+#define CCGR_EPDC_AXI_CLK __CCGR_NUM(6, 8)
+#else
#define CCGR_ARM_BUS_CLK __CCGR_NUM(0, 0)
#define CCGR_ARM_AXI_CLK __CCGR_NUM(0, 1)
#define CCGR_ARM_DEBUG_CLK __CCGR_NUM(0, 2)
@@ -209,6 +261,7 @@
#define CCGR_GPU2D_CLK __CCGR_NUM(6, 3)
#define CCGR_SLIMBUS_CLK __CCGR_NUM(6, 4)
#define CCGR_SLIMBUS_SERIAL_CLK __CCGR_NUM(6, 5)
+#endif
#endif /* _IMX51_CCMREG_H */
Index: src/sys/arch/arm/imx/imx51_clock.c
diff -u src/sys/arch/arm/imx/imx51_clock.c:1.4 src/sys/arch/arm/imx/imx51_clock.c:1.5
--- src/sys/arch/arm/imx/imx51_clock.c:1.4 Sat Oct 27 17:17:39 2012
+++ src/sys/arch/arm/imx/imx51_clock.c Fri Jul 25 07:49:56 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: imx51_clock.c,v 1.4 2012/10/27 17:17:39 chs Exp $ */
+/* $NetBSD: imx51_clock.c,v 1.5 2014/07/25 07:49:56 hkenken Exp $ */
/*
* Copyright (c) 2009 Genetec corp. All rights reserved.
* Written by Hashimoto Kenichi for Genetec corp.
@@ -25,7 +25,10 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: imx51_clock.c,v 1.4 2012/10/27 17:17:39 chs Exp $");
+__KERNEL_RCSID(0, "$NetBSD: imx51_clock.c,v 1.5 2014/07/25 07:49:56 hkenken Exp $");
+
+#include "opt_imx.h"
+#include "opt_imx51clk.h"
#include <sys/param.h>
#include <sys/systm.h>
@@ -52,7 +55,6 @@ __KERNEL_RCSID(0, "$NetBSD: imx51_clock.
#include <arm/imx/imxclockvar.h>
#include "imxccm.h" /* if CCM driver is configured into the kernel */
-#include "opt_imx51clk.h"
Index: src/sys/arch/arm/imx/imx51reg.h
diff -u src/sys/arch/arm/imx/imx51reg.h:1.4 src/sys/arch/arm/imx/imx51reg.h:1.5
--- src/sys/arch/arm/imx/imx51reg.h:1.4 Sun Apr 15 16:34:11 2012
+++ src/sys/arch/arm/imx/imx51reg.h Fri Jul 25 07:49:56 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: imx51reg.h,v 1.4 2012/04/15 16:34:11 bsh Exp $ */
+/* $NetBSD: imx51reg.h,v 1.5 2014/07/25 07:49:56 hkenken Exp $ */
/*-
* Copyright (c) 2007 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -31,6 +31,38 @@
#ifndef _ARM_IMX_IMX51REG_H_
#define _ARM_IMX_IMX51REG_H_
+#ifdef IMX50
+#define TZIC_BASE 0x0fffc000
+#define APB_BASE 0x40000000
+#define AIPSTZ1_BASE 0x50000000
+#define AIPSTZ2_BASE 0x60000000
+#define CSD0DDR_BASE 0x70000000
+#else
+#define TZIC_BASE 0xe0000000
+#define AIPSTZ1_BASE 0x70000000
+#define AIPSTZ2_BASE 0x80000000
+#define CSD0DDR_BASE 0x90000000
+#define CSD1DDR_BASE 0xa0000000
+#define CSDDDR_SIZE 0x10000000 /* 256MiB */
+#define CS0_BASE 0xb0000000
+#define CS0_SIZE 0x08000000 /* 128MiB */
+#define CS1_BASE 0xb8000000
+#define CS1_SIZE 0x08000000 /* 128MiB */
+#define CS2_BASE 0xc0000000
+#define CS2_SIZE 0x08000000 /* 128MiB */
+#define CS3_BASE 0xc8000000
+#define CS3_SIZE 0x04000000 /* 64MiB */
+#define CS4_BASE 0xcc000000
+#define CS4_SIZE 0x02000000 /* 32MiB */
+#define CS5_BASE 0xcefe0000
+#define CS5_SIZE 0x00010000 /* 32MiB */
+#define NAND_FLASH_BASE 0xcfff0000 /* internal buffer */
+#define NAND_FLASH_SIZE 0x00010000
+
+#define GPU2D_BASE 0xd0000000
+#define GPU2D_SIZE 0x10000000
+#endif
+
#define BOOTROM_BASE 0x00000000
#define BOOTROM_SIZE 0x9000
@@ -43,6 +75,11 @@
#define GPU_BASE 0x30000000
#define GPU_SIZE 0x10000000
+#ifdef IMX50
+#define EPDC_BASE (APB_BASE + 0x01010000)
+#define EPDC_SIZE 0x2000
+#endif
+
/* Image Prossasing Unit */
#define IPU_BASE 0x40000000
#define IPU_CM_BASE (IPU_BASE + 0x1e000000)
@@ -85,138 +122,160 @@
#define DEBUGROM_BASE 0x60000000
#define DEBUGROM_SIZE 0x1000
-#define ESDHC1_BASE 0x70004000
-#define ESDHC2_BASE 0x70008000
-#define ESDHC3_BASE 0x70020000
-#define ESDHC4_BASE 0x70024000
-#define ESDHC_SIZE 0x4000
-
-#define UART1_BASE 0x73fbc000
-#define UART2_BASE 0x73fc0000
-#define UART3_BASE 0x7000c000
+#define ESDHC1_BASE (AIPSTZ1_BASE + 0x00004000)
+#define ESDHC2_BASE (AIPSTZ1_BASE + 0x00008000)
+#define ESDHC3_BASE (AIPSTZ1_BASE + 0x00020000)
+#define ESDHC4_BASE (AIPSTZ1_BASE + 0x00024000)
+#define ESDHC_SIZE 0x100
+
+#define PWM1_BASE (AIPSTZ1_BASE + 0x03fb4000)
+#define PWM2_BASE (AIPSTZ1_BASE + 0x03fb8000)
+
+#define UART1_BASE (AIPSTZ1_BASE + 0x03fbc000)
+#define UART2_BASE (AIPSTZ1_BASE + 0x03fc0000)
+#define UART3_BASE (AIPSTZ1_BASE + 0x0000c000)
/* register definitions in imxuartreg.h */
-#define ECSPI1_BASE 0x70010000
-#define ECSPI2_BASE 0x83fac000
+#define CCMC_BASE (AIPSTZ1_BASE + 0x03fd4000)
+
+#define ECSPI1_BASE (AIPSTZ1_BASE + 0x00010000)
+#define ECSPI2_BASE (AIPSTZ2_BASE + 0x03fac000)
#define ECSPI_SIZE 0x4000
-#define SSI1_BASE 0x83fcc000
-#define SSI2_BASE 0x70014000
-#define SSI3_BASE 0x83fe8000
+#define SSI1_BASE (AIPSTZ2_BASE + 0x03fcc000)
+#define SSI2_BASE (AIPSTZ1_BASE + 0x00014000)
+#define SSI3_BASE (AIPSTZ2_BASE + 0x03fe8000)
/* register definitions in imxssireg.h */
-#define SPDIF_BASE 0x70028000
+#define SPDIF_BASE (AIPSTZ1_BASE + 0x00028000)
#define SPDIF_SIZE 0x4000
-#define PATA_UDMA_BASE 0x70030000
+#define PATA_UDMA_BASE (AIPSTZ1_BASE + 0x00030000)
#define PATA_UDMA_SIZE 0x4000
-#define PATA_PIO_BASE 0x83fe0000
+#define PATA_PIO_BASE (AIPSTZ2_BASE + 0x03fe0000)
#define PATA_PIO_SIZE 0x4000
-#define SLM_BASE 0x70034000
+#define SLM_BASE (AIPSTZ1_BASE + 0x00034000)
#define SLM_SIZE 0x4000
-#define HSI2C_BASE 0x70038000
+#ifdef IMX50
+#define I2C3_BASE (AIPSTZ1_BASE + 0x00038000)
+#define I2C3_SIZE 0x4000
+#else
+#define HSI2C_BASE (AIPSTZ1_BASE + 0x00038000)
#define HSI2C_SIZE 0x4000
+#endif
-#define SPBA_BASE 0x7003c000
+#define SPBA_BASE (AIPSTZ1_BASE + 0x0003c000)
#define SPBA_SIZE 0x4000
-#define USBOH3_BASE 0x73f80000
-#define USBOH3_PL301_BASE 0x73fc4000
+#define USBOH3_BASE (AIPSTZ1_BASE + 0x03f80000)
+#define USBOH3_PL301_BASE (AIPSTZ1_BASE + 0x03fc4000)
#define USBOH3_EHCI_SIZE 0x200
#define USBOH3_OTG 0x000
#define USBOH3_EHCI(n) (USBOH3_EHCI_SIZE*(n)) /* n=1,2,3 */
/* USB_CTRL register */
-#define USBOH3_USBCTRL 0x800
-#define USBCTRL_OWIR __BIT(31) /* OTG Wakeup interrupt request */
-#define USBCTRL_OSIC_SHIFT 29
-#define USBCTRL_OSIC __BITS(29,30) /* OTG Serial interface configuration */
-#define USBCTRL_OUIE __BIT(28) /* OTG Wake-up interrupt enable */
-#define USBCTRL_OBPAL __BITS(25,26) /* OTG Bypass value */
-#define USBCTRL_OPM __BIT(24) /* OTG Power Mask */
-#define USBCTRL_ICVOL __BIT(23) /* Host1 IC_USB voltage status */
-#define USBCTRL_ICTPIE __BIT(19) /* IC USB TP interrupt enable */
-#define USBCTRL_UBPCKE __BIT(18) /* Bypass clock enable */
-#define USBCTRL_H1TCKOEN __BIT(17) /* Host1 ULPO PHY clock enable */
-#define USBCTRL_ICTPC __BIT(16) /* Clear IC TP interrupt flag */
-#define USBCTRL_H1WIR __BIT(15) /* Host1 wakeup interrupt request */
-#define USBCTRL_H1STC_SHIFT 13
-#define USBCTRL_H1SIC __BITS(13,14) /* Host1 serial interface config */
-#define USBCTRL_H1UIE __BIT(12) /* Host1 ILPI interrupt enable */
-#define USBCTRL_H1WIE __BIT(11) /* Host1 wakeup interrupt enable */
-#define USBCTRL_H1BPVAL __BITS(9,10) /* Host1 bypass value */
-#define USBCTRL_H1PM __BIT(8) /* Host1 power mask */
-#define USBCTRL_OHSTLL __BIT(7) /* OTG ULPI TLL enable */
-#define USBCTRL_H1HSTLL __BIT(6) /* Host1 ULPI TLL enable */
-#define USBCTRL_H1DISFSTTL __BIT(4) /* Host1 serial TLL disable */
-#define USBCTRL_OTCKOEN __BIT(1) /* OTG ULPI PHY clock enable */
-#define USBCTRL_BPE __BIT(0) /* Bypass enable */
-
-#define USBOH3_OTGMIRROR 0x804
-#define USBOH3_PHYCTRL0 0x808
-#define PHYCTRL0_VLOAD __BIT(31)
-#define PHYCTRL0_VCONTROL __BITS(27,30)
-#define PHYCTRL0_CONF2 __BIT(26)
-#define PHYCTRL0_CONF3 __BIT(25)
-#define PHYCTRL0_CHGRDETEN __BIT(24)
-#define PHYCTRL0_CHGRDETON __BIT(23)
-#define PHYCTRL0_VSTATUS __BITS(15,22)
-#define PHYCTRL0_SUSPENDM __BIT(12)
-#define PHYCTRL0_RESET __BIT(11)
-#define PHYCTRL0_UTMI_ON_CLOCK __BIT(10)
+#define USBOH3_USBCTRL 0x800
+#define USBCTRL_OWIR __BIT(31) /* OTG Wakeup interrupt request */
+#define USBCTRL_OSIC __BITS(29,30) /* OTG Serial interface configuration */
+#define USBCTRL_OUIE __BIT(28) /* OTG Wake-up interrupt enable */
+#define USBCTRL_OBPAL __BITS(25,26) /* OTG Bypass value */
+#define USBCTRL_OPM __BIT(24) /* OTG Power Mask */
+#define USBCTRL_ICVOL __BIT(23) /* Host1 IC_USB voltage status */
+#define USBCTRL_ICTPIE __BIT(19) /* IC USB TP interrupt enable */
+#define USBCTRL_UBPCKE __BIT(18) /* Bypass clock enable */
+#define USBCTRL_H1TCKOEN __BIT(17) /* Host1 ULPO PHY clock enable */
+#define USBCTRL_ICTPC __BIT(16) /* Clear IC TP interrupt flag */
+#define USBCTRL_H1WIR __BIT(15) /* Host1 wakeup interrupt request */
+#define USBCTRL_H1SIC __BITS(13,14) /* Host1 serial interface config */
+#define USBCTRL_H1UIE __BIT(12) /* Host1 ILPI interrupt enable */
+#define USBCTRL_H1WIE __BIT(11) /* Host1 wakeup interrupt enable */
+#define USBCTRL_H1BPVAL __BITS(9,10) /* Host1 bypass value */
+#define USBCTRL_H1PM __BIT(8) /* Host1 power mask */
+#define USBCTRL_OHSTLL __BIT(7) /* OTG ULPI TLL enable */
+#define USBCTRL_H1HSTLL __BIT(6) /* Host1 ULPI TLL enable */
+#define USBCTRL_H1DISFSTTL __BIT(4) /* Host1 serial TLL disable */
+#define USBCTRL_OTCKOEN __BIT(1) /* OTG ULPI PHY clock enable */
+#define USBCTRL_BPE __BIT(0) /* Bypass enable */
+#define USBOH3_OTGMIRROR 0x804
+#define USBOH3_PHYCTRL0 0x808
+#define PHYCTRL0_VLOAD __BIT(31)
+#define PHYCTRL0_VCONTROL __BITS(27,30)
+#define PHYCTRL0_CONF2 __BIT(26)
+#define PHYCTRL0_CONF3 __BIT(25)
+#define PHYCTRL0_CHGRDETEN __BIT(24)
+#define PHYCTRL0_CHGRDETON __BIT(23)
+#define PHYCTRL0_VSTATUS __BITS(15,22)
+#define PHYCTRL0_SUSPENDM __BIT(12)
+#define PHYCTRL0_RESET __BIT(11)
+#define PHYCTRL0_UTMI_ON_CLOCK __BIT(10)
#define PHYCTRL0_OTG_OVER_CUR_POL __BIT(9)
#define PHYCTRL0_OTG_OVER_CUR_DIS __BIT(8)
#define PHYCTRL0_OTG_XCVR_CLK_SEL __BIT(7)
+#define PHYCTRL0_H1_OVER_CUR_POL __BIT(6)
+#define PHYCTRL0_H1_OVER_CUR_DIS __BIT(5)
#define PHYCTRL0_H1_XCVR_CLK_SEL __BIT(4)
#define PHYCTRL0_PWR_POL __BIT(3)
#define PHYCTRL0_CHRGDET __BIT(2)
#define PHYCTRL0_CHRGDET_INT_EN __BIT(1)
#define PHYCTRL0_CHRGDET_INT_FLG __BIT(0)
-
-#define USBOH3_PHYCTRL1 0x80c
+#define USBOH3_PHYCTRL1 0x80c
#define PHYCTRL1_PLLDIVVALUE_MASK __BITS(0,1)
#define PHYCTRL1_PLLDIVVALUE_19MHZ 0 /* 19.2MHz */
#define PHYCTRL1_PLLDIVVALUE_24MHZ 1
#define PHYCTRL1_PLLDIVVALUE_26MHZ 2
#define PHYCTRL1_PLLDIVVALUE_27MHZ 3
-#define USBOH3_USBCTRL1 0x810
+#define USBOH3_USBCTRL1 0x810
#define USBCTRL1_UH3_EXT_CLK_EN __BIT(27)
#define USBCTRL1_UH2_EXT_CLK_EN __BIT(26)
#define USBCTRL1_UH1_EXT_CLK_EN __BIT(25)
#define USBCTRL1_OTG_EXT_CLK_EN __BIT(24)
-#define USBOH3_USBCTRL2 0x814
-#define USBOH3_USBCTRL3 0x818
+#define USBOH3_USBCTRL2 0x814
+#define USBOH3_USBCTRL3 0x818
+#define USBOH3_UH1_PHY_CTRL_0 0x81c
+#define USBOH3_UH1_PHY_CTRL_1 0x820
+#define USBOH3_USB_CLKONOFF_CTRL 0x824
+#define USB_CLKONOFF_CTRL_H1_AHBCLK_OFF __BIT(18)
+#define USB_CLKONOFF_CTRL_OTG_AHBCLK_OFF __BIT(17)
-#define USBOH3_SIZE 0x820
+#define USBOH3_SIZE 0x828
/* GPIO module */
-#define GPIO_BASE(n) (0x73f84000 + 0x4000 * ((n)-1))
+#define GPIO_BASE(n) \
+ (AIPSTZ1_BASE + (((n) <= 4) ? \
+ 0x03f84000 + 0x4000 * ((n) - 1) : \
+ 0x03fdc000 + 0x4000 * ((n) - 5)))
#define GPIO1_BASE GPIO_BASE(1)
#define GPIO2_BASE GPIO_BASE(2)
#define GPIO3_BASE GPIO_BASE(3)
#define GPIO4_BASE GPIO_BASE(4)
+#define GPIO5_BASE GPIO_BASE(5)
+#define GPIO6_BASE GPIO_BASE(6)
+#ifdef IMX50
+#define GPIO_NGROUPS 6
+#else
#define GPIO_NGROUPS 4
+#endif
-#define KPP_BASE 0x73f94000
+#define KPP_BASE (AIPSTZ1_BASE + 0x03f94000)
/* register definitions in imxkppreg.h */
-#define WDOG1_BASE 0x73f98000
-#define WDOG2_BASE 0x73f9c000
+#define WDOG1_BASE (AIPSTZ1_BASE + 0x03f98000)
+#define WDOG2_BASE (AIPSTZ1_BASE + 0x03f9c000)
#define WDOG_SIZE 0x000a
-#define GPT_BASE 0x73fa0000
+#define GPT_BASE (AIPSTZ1_BASE + 0x03fa0000)
#define GPT_SIZE 0x4000
-#define SRTC_BASE 0x73fa4000
+#define SRTC_BASE (AIPSTZ1_BASE + 0x03fa4000)
#define SRTC_SIZE 0x4000
/* IO multiplexor */
-#define IOMUXC_BASE 0x73fa8000
+#define IOMUXC_BASE (AIPSTZ1_BASE + 0x03fa8000)
#define IOMUXC_SIZE 0x4000
#define IOMUXC_MUX_CTL 0x001c /* multiprex control */
@@ -237,15 +296,17 @@
#define PAD_CTL_PUE __BIT(6)
#define PAD_CTL_PULL (PAD_CTL_PKE|PAD_CTL_PUE)
#define PAD_CTL_KEEPER (PAD_CTL_PKE|0)
-#define PAD_CTL_PUS_100K_PD (0x0 << 4)
-#define PAD_CTL_PUS_47K_PU (0x1 << 4)
-#define PAD_CTL_PUS_100K_PU (0x2 << 4)
-#define PAD_CTL_PUS_22K_PU (0x3 << 4)
+#define PAD_CTL_PUS_MASK __BITS(5, 4)
+#define PAD_CTL_PUS_100K_PD __SHIFTIN(0x0, PAD_CTL_PUS_MASK)
+#define PAD_CTL_PUS_47K_PU __SHIFTIN(0x1, PAD_CTL_PUS_MASK)
+#define PAD_CTL_PUS_100K_PU __SHIFTIN(0x2, PAD_CTL_PUS_MASK)
+#define PAD_CTL_PUS_22K_PU __SHIFTIN(0x3, PAD_CTL_PUS_MASK)
#define PAD_CTL_ODE __BIT(3) /* opendrain */
-#define PAD_CTL_DSE_LOW (0x0 << 1)
-#define PAD_CTL_DSE_MID (0x1 << 1)
-#define PAD_CTL_DSE_HIGH (0x2 << 1)
-#define PAD_CTL_DSE_MAX (0x3 << 1)
+#define PAD_CTL_DSE_MASK __BITS(2, 1)
+#define PAD_CTL_DSE_LOW __SHIFTIN(0x0, PAD_CTL_DSE_MASK)
+#define PAD_CTL_DSE_MID __SHIFTIN(0x1, PAD_CTL_DSE_MASK)
+#define PAD_CTL_DSE_HIGH __SHIFTIN(0x2, PAD_CTL_DSE_MASK)
+#define PAD_CTL_DSE_MAX __SHIFTIN(0x3, PAD_CTL_DSE_MASK)
#define PAD_CTL_SRE __BIT(0)
#define IOMUXC_INPUT_CTL 0x08c4 /* input control */
#define INPUT_DAISY_0 0
@@ -269,65 +330,60 @@
#define IOMUX_PAD_NONE 0xffff
/* EPIT */
-#define EPIT1_BASE 0x73FAC000
-#define EPIT2_BASE 0x73FB0000
+#define EPIT1_BASE (AIPSTZ1_BASE + 0x03FAC000)
+#define EPIT2_BASE (AIPSTZ1_BASE + 0x03FB0000)
/* register definitions in imxepitreg.h */
-#define PWM1_BASE 0x73fb4000
-#define PWM2_BASE 0x73fb8000
+#define PWM1_BASE (AIPSTZ1_BASE + 0x03fb4000)
+#define PWM2_BASE (AIPSTZ1_BASE + 0x03fb8000)
#define PWM_SIZE 0x4000
-#define SRC_BASE 0x73fd0000
+#define SRC_BASE (AIPSTZ1_BASE + 0x03fd0000)
#define SRC_SIZE 0x4000
-#define CCM_BASE 0x73fd4000
+#define CCM_BASE (AIPSTZ1_BASE + 0x03fd4000)
#define CCM_SIZE 0x0088
-#define GPC_BASE 0x73fd8000
+#define GPC_BASE (AIPSTZ1_BASE + 0x03fd8000)
#define GPC_SIZE 0x4000
-#define DPLLIP1_BASE 0x83f80000
-#define DPLLIP2_BASE 0x83f84000
-#define DPLLIP3_BASE 0x83f88000
-#define DPLLIP_SIZE 0x4000
-
-#define AHBMAX_BASE 0x83f94000
+#define AHBMAX_BASE (AIPSTZ2_BASE + 0x03f94000)
#define AHBMAX_SIZE 0x4000
-#define IIM_BASE 0x83f98000
+#define IIM_BASE (AIPSTZ2_BASE + 0x03f98000)
#define IIM_SIZE 0x4000
-#define CSU_BASE 0x83f9c000
+#define CSU_BASE (AIPSTZ2_BASE + 0x03f9c000)
#define CSU_SIZE 0x4000
-#define OWIRE_BASE 0x83fa4000 /* 1-wire */
+#define OWIRE_BASE (AIPSTZ2_BASE + 0x03fa4000)
#define OWIRE_SIZE 0x4000
-#define FIRI_BASE 0x83fa8000
+#define FIRI_BASE (AIPSTZ2_BASE + 0x03fa8000)
#define FIRI_SIZE 0x4000
-#define SDMA_BASE 0x83fb0000
+#define SDMA_BASE (AIPSTZ2_BASE + 0x03fb0000)
#define SDMA_SIZE 0x4000
/* see imxsdmareg.h for register definitions */
-#define SCC_BASE 0x83fb4000
+#define SCC_BASE (AIPSTZ2_BASE + 0x03fb4000)
#define SCC_SIZE 0x4000
-#define ROMCP_BASE 0x83fb8000
+#define ROMCP_BASE (AIPSTZ2_BASE + 0x03fb8000)
#define ROMCP_SIZE 0x4000
-#define RTIC_BASE 0x83fbc000
+#define RTIC_BASE (AIPSTZ2_BASE + 0x03fbc000)
#define RTIC_SIZE 0x4000
-#define CSPI_BASE 0x83fc0000
+#define CSPI_BASE (AIPSTZ2_BASE + 0x03fc0000)
#define CSPI_SIZE 0x4000
-#define I2C1_BASE 0x83fc8000
-#define I2C2_BASE 0x83fc4000
+#define I2C1_BASE (AIPSTZ2_BASE + 0x03fc8000)
+#define I2C2_BASE (AIPSTZ2_BASE + 0x03fc4000)
/* register definitions in imxi2creg.h */
-#define AUDMUX_BASE 0x83fd0000
+#define AUDMUX_BASE (AIPSTZ2_BASE + 0x03fd0000)
#define AUDMUX_SIZE 0x4000
#define AUDMUX_PTCR(n) ((n - 1) * 0x8)
#define PTCR_TFSDIR (1 << 31)
@@ -347,43 +403,22 @@
#define PDCR_INMMASK(x) (((x) & 0xff) << 0)
#define AUDMUX_CNMCR 0x38
-#define EMI_BASE 0x83fd8000
+#define EMI_BASE (AIPSTZ2_BASE + 0x03fd8000)
#define EMI_SIZE 0x4000
-#define SIM_BASE 0x83fe4000
+#define SIM_BASE (AIPSTZ2_BASE + 0x03fe4000)
#define SIM_SIZE 0x4000
-#define FEC_BASE 0x83fec000
+#define FEC_BASE (AIPSTZ2_BASE + 0x03fec000)
#define FEC_SIZE 0x4000
-#define TVE_BASE 0x83ff0000
+#define TVE_BASE (AIPSTZ2_BASE + 0x03ff0000)
#define TVE_SIZE 0x4000
-#define VPU_BASE 0x83ff4000
+#define VPU_BASE (AIPSTZ2_BASE + 0x03ff4000)
#define VPU_SIZE 0x4000
-#define SAHARA_BASE 0x83ff8000
+#define SAHARA_BASE (AIPSTZ2_BASE + 0x03ff8000)
#define SAHARA_SIZE 0x4000
-#define CSD0DDR_BASE 0x90000000
-#define CSD1DDR_BASE 0xa0000000
-#define CSDDDR_SIZE 0x10000000 /* 256MiB */
-#define CS0_BASE 0xb0000000
-#define CS0_SIZE 0x08000000 /* 128MiB */
-#define CS1_BASE 0xb8000000
-#define CS1_SIZE 0x08000000 /* 128MiB */
-#define CS2_BASE 0xc0000000
-#define CS2_SIZE 0x08000000 /* 128MiB */
-#define CS3_BASE 0xc8000000
-#define CS3_SIZE 0x04000000 /* 64MiB */
-#define CS4_BASE 0xcc000000
-#define CS4_SIZE 0x02000000 /* 32MiB */
-#define CS5_BASE 0xcefe0000
-#define CS5_SIZE 0x00010000 /* 32MiB */
-#define NAND_FLASH_BASE 0xcfff0000 /* internal buffer */
-#define NAND_FLASH_SIZE 0x00010000
-
-#define GPU2D_BASE 0xd0000000
-#define GPU2D_SIZE 0x10000000
-
-#define TZIC_BASE 0xe0000000
-/* register definitions in imx51_tzicreg.h */
+#define DPLL_BASE(n) ((AIPSTZ2_BASE + 0x03F80000 + (0x4000 * ((n)-1))))
+#define DPLL_SIZE 0x100
#endif /* _ARM_IMX_IMX51REG_H_ */
Index: src/sys/arch/arm/imx/imx51_ccmvar.h
diff -u src/sys/arch/arm/imx/imx51_ccmvar.h:1.2 src/sys/arch/arm/imx/imx51_ccmvar.h:1.3
--- src/sys/arch/arm/imx/imx51_ccmvar.h:1.2 Sat Mar 22 09:46:33 2014
+++ src/sys/arch/arm/imx/imx51_ccmvar.h Fri Jul 25 07:49:56 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: imx51_ccmvar.h,v 1.2 2014/03/22 09:46:33 hkenken Exp $ */
+/* $NetBSD: imx51_ccmvar.h,v 1.3 2014/07/25 07:49:56 hkenken Exp $ */
/*
* Copyright (c) 2012 Genetec Corporation. All rights reserved.
* Written by Hashimoto Kenichi for Genetec Corporation.
@@ -70,10 +70,21 @@ enum imx51_clock {
IMX51CLK_CSPI_CLK_ROOT,
IMX51CLK_WRCK_CLK_ROOT,
IMX51CLK_LPSR_CLK_ROOT,
- IMX51CLK_PGC_CLK_ROOT
+ IMX51CLK_PGC_CLK_ROOT,
+#if IMX50
+ IMX50CLK_PFD0_CLK_ROOT,
+ IMX50CLK_PFD1_CLK_ROOT,
+ IMX50CLK_PFD2_CLK_ROOT,
+ IMX50CLK_PFD3_CLK_ROOT,
+ IMX50CLK_PFD4_CLK_ROOT,
+ IMX50CLK_PFD5_CLK_ROOT,
+ IMX50CLK_PFD6_CLK_ROOT,
+ IMX50CLK_PFD7_CLK_ROOT,
+#endif
};
u_int imx51_get_clock(enum imx51_clock);
void imx51_clk_gating(int, int);
+void imx51_clk_rate(int, int, int);
#endif /* _ARM_IMX_IMX51_CCMVAR_H_ */
Index: src/sys/arch/arm/imx/imx51_gpio.c
diff -u src/sys/arch/arm/imx/imx51_gpio.c:1.2 src/sys/arch/arm/imx/imx51_gpio.c:1.3
--- src/sys/arch/arm/imx/imx51_gpio.c:1.2 Fri Jul 1 20:27:50 2011
+++ src/sys/arch/arm/imx/imx51_gpio.c Fri Jul 25 07:49:56 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: imx51_gpio.c,v 1.2 2011/07/01 20:27:50 dyoung Exp $ */
+/* $NetBSD: imx51_gpio.c,v 1.3 2014/07/25 07:49:56 hkenken Exp $ */
/* derived from imx31_gpio.c */
/*-
@@ -30,7 +30,9 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: imx51_gpio.c,v 1.2 2011/07/01 20:27:50 dyoung Exp $");
+__KERNEL_RCSID(0, "$NetBSD: imx51_gpio.c,v 1.3 2014/07/25 07:49:56 hkenken Exp $");
+
+#include "opt_imx.h"
#include "locators.h"
#include "gpio.h"
@@ -71,6 +73,10 @@ imxgpio_match(device_t parent, cfdata_t
case GPIO2_BASE:
case GPIO3_BASE:
case GPIO4_BASE:
+#ifdef IMX50
+ case GPIO5_BASE:
+ case GPIO6_BASE:
+#endif
return 1;
}
Index: src/sys/arch/arm/imx/imx51_iomuxreg.h
diff -u src/sys/arch/arm/imx/imx51_iomuxreg.h:1.2 src/sys/arch/arm/imx/imx51_iomuxreg.h:1.3
--- src/sys/arch/arm/imx/imx51_iomuxreg.h:1.2 Sun Apr 15 10:16:37 2012
+++ src/sys/arch/arm/imx/imx51_iomuxreg.h Fri Jul 25 07:49:56 2014
@@ -662,21 +662,5 @@
IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_##name, \
IOMUXC_SW_PAD_CTL_PAD_##name)
-#define MUX_PIN_MUX(name) \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_##name, IOMUX_PAD_NONE)
-
-#define MUX_PIN_PAD(name) \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_##name)
-
-#define MUX_PIN_GRP(name) \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_GRP_##name)
-
-#define MUX_PIN_PATH(name) \
- IOMUX_PIN(IOMUXC_##name##_SELECT_INPUT, IOMUX_MUX_NONE)
-
-/* INPUT Control */
-
-#define MUX_SELECT(name) (name##_SELECT_INPUT)
-
#endif /* _IMX51_IOMUXREG_H */
Index: src/sys/arch/arm/imx/imx51_uart.c
diff -u src/sys/arch/arm/imx/imx51_uart.c:1.2 src/sys/arch/arm/imx/imx51_uart.c:1.3
--- src/sys/arch/arm/imx/imx51_uart.c:1.2 Sat Nov 27 13:37:27 2010
+++ src/sys/arch/arm/imx/imx51_uart.c Fri Jul 25 07:49:56 2014
@@ -25,7 +25,12 @@
*
*/
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: imx51_uart.c,v 1.3 2014/07/25 07:49:56 hkenken Exp $");
+
+#include "opt_imx.h"
#include "opt_imxuart.h"
+
#include <sys/param.h>
#include <sys/bus.h>
#include <sys/device.h>
@@ -34,7 +39,6 @@
#include <arm/imx/imxuartreg.h>
#include <arm/imx/imxuartvar.h>
-
int
imxuart_match(device_t parent, struct cfdata *cf, void *aux)
{
Index: src/sys/arch/arm/imx/imx51_dpllreg.h
diff -u src/sys/arch/arm/imx/imx51_dpllreg.h:1.1 src/sys/arch/arm/imx/imx51_dpllreg.h:1.2
--- src/sys/arch/arm/imx/imx51_dpllreg.h:1.1 Tue Apr 17 09:33:31 2012
+++ src/sys/arch/arm/imx/imx51_dpllreg.h Fri Jul 25 07:49:56 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: imx51_dpllreg.h,v 1.1 2012/04/17 09:33:31 bsh Exp $ */
+/* $NetBSD: imx51_dpllreg.h,v 1.2 2014/07/25 07:49:56 hkenken Exp $ */
/*
* Copyright (c) 2012 Genetec Corporation. All rights reserved.
* Written by Hashimoto Kenichi for Genetec Corporation.
@@ -33,22 +33,17 @@
#define IMX51_N_DPLLS 3 /* 1..3 */
-#define DPLL_BASE(n) (0x83F80000 + (0x4000 * ((n)-1)))
-#define DPLL_SIZE 0x100
-
#define DPLL_DP_CTL 0x0000
#define DP_CTL_HFSM __BIT(7)
-#define DP_CTL_REF_CLK_SEL_MASK __BITS(8,9)
-#define DP_CTL_REF_CLK_SEL_COSC (__BIT(9)|0)
-#define DP_CTL_REF_CLK_SEL_FPM (__BIT(9)|__BIT(8))
+#define DP_CTL_REF_CLK_SEL __BITS(8,9)
+#define DP_CTL_REF_CLK_SEL_COSC __SHIFTIN(0x2, DP_CTL_REF_CLK_SEL)
+#define DP_CTL_REF_CLK_SEL_FPM __SHIFTIN(0x3, DP_CTL_REF_CLK_SEL)
#define DP_CTL_REF_CLK_DIV __BIT(10)
#define DP_CTL_DPDCK0_2_EN __BIT(12)
#define DPLL_DP_CONFIG 0x0004
#define DPLL_DP_OP 0x0008
-#define DP_OP_PDF_SHIFT 0
-#define DP_OP_PDF_MASK (0xf << DP_OP_PDF_SHIFT)
-#define DP_OP_MFI_SHIFT 4
-#define DP_OP_MFI_MASK (0xf << DP_OP_MFI_SHIFT)
+#define DP_OP_PDF __BITS(3, 0)
+#define DP_OP_MFI __BITS(7, 4)
#define DPLL_DP_MFD 0x000C
#define DPLL_DP_MFN 0x0010
#define DPLL_DP_MFNMINUS 0x0014
Index: src/sys/arch/arm/imx/imx51_usb.c
diff -u src/sys/arch/arm/imx/imx51_usb.c:1.1 src/sys/arch/arm/imx/imx51_usb.c:1.2
--- src/sys/arch/arm/imx/imx51_usb.c:1.1 Tue Nov 30 13:05:27 2010
+++ src/sys/arch/arm/imx/imx51_usb.c Fri Jul 25 07:49:56 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: imx51_usb.c,v 1.1 2010/11/30 13:05:27 bsh Exp $ */
+/* $NetBSD: imx51_usb.c,v 1.2 2014/07/25 07:49:56 hkenken Exp $ */
/*
* Copyright (c) 2010 Genetec Corporation. All rights reserved.
* Written by Hiroyuki Bessho for Genetec Corporation.
@@ -25,7 +25,9 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: imx51_usb.c,v 1.1 2010/11/30 13:05:27 bsh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: imx51_usb.c,v 1.2 2014/07/25 07:49:56 hkenken Exp $");
+
+#include "opt_imx.h"
#include <sys/param.h>
#include <sys/systm.h>
@@ -49,6 +51,7 @@ __KERNEL_RCSID(0, "$NetBSD: imx51_usb.c,
#include "locators.h"
static int imxusbc_search(device_t, cfdata_t, const int *, void *);
+static int imxusbc_print(void *, const char *);
int
@@ -82,8 +85,17 @@ imxusbc_search(device_t parent, cfdata_t
aa.aa_irq = cf->cf_loc[IMXUSBCCF_IRQ];
if (config_match(parent, cf, &aa) > 0)
- config_attach(parent, cf, &aa, NULL);
+ config_attach(parent, cf, &aa, imxusbc_print);
return 0;
}
+/* ARGSUSED */
+static int
+imxusbc_print(void *aux, const char *name __unused)
+{
+ struct imxusbc_attach_args *aa = aux;
+
+ aprint_normal(" unit %d irq %d", aa->aa_unit, aa->aa_irq);
+ return (UNCONF);
+}
Index: src/sys/arch/arm/imx/imxsdmareg.h
diff -u src/sys/arch/arm/imx/imxsdmareg.h:1.1 src/sys/arch/arm/imx/imxsdmareg.h:1.2
--- src/sys/arch/arm/imx/imxsdmareg.h:1.1 Sat Nov 13 07:11:03 2010
+++ src/sys/arch/arm/imx/imxsdmareg.h Fri Jul 25 07:49:56 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: imxsdmareg.h,v 1.1 2010/11/13 07:11:03 bsh Exp $ */
+/* $NetBSD: imxsdmareg.h,v 1.2 2014/07/25 07:49:56 hkenken Exp $ */
/*
* Copyright (c) 2009 Genetec Corporation. All rights reserved.
@@ -29,7 +29,9 @@
#ifndef _IMXSDMAREG_H
#define _IMXSDMAREG_H
-#define SDMA_SIZE 0x100
+#include "opt_imx.h"
+
+#define SDMA_SIZE 0x2c0
/* SDMA Controller */
#define SDMA_N_CHANNELS 32
@@ -97,7 +99,13 @@
#define SDMA_CHN0ADDR 0x005c /* Channel 0 Boot address */
#define SDMA_XTRIG_CONF1 0x0070 /* Cross-Triger Evennts Config */
#define SDMA_XTRIG_CONF2 0x0074
+#if defined(IMX31)
#define SDMA_CHNENBL(n) (0x80+(n)*4) /* Channel Enable RAM */
+#elif defined(IMX51)
+#define SDMA_OTB 0x0078
+#define SDMA_PRF_CNT(n) (0x07c+(n)*4)
+#define SDMA_CHNENBL(n) (0x200+(n)*4) /* Channel Enable RAM */
+#endif
#define SDMA_CHNPRI(n) (0x100+(n)*4) /* Channel Priority */
Index: src/sys/arch/arm/imx/imxusbreg.h
diff -u src/sys/arch/arm/imx/imxusbreg.h:1.1 src/sys/arch/arm/imx/imxusbreg.h:1.2
--- src/sys/arch/arm/imx/imxusbreg.h:1.1 Tue Nov 30 13:05:27 2010
+++ src/sys/arch/arm/imx/imxusbreg.h Fri Jul 25 07:49:56 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: imxusbreg.h,v 1.1 2010/11/30 13:05:27 bsh Exp $ */
+/* $NetBSD: imxusbreg.h,v 1.2 2014/07/25 07:49:56 hkenken Exp $ */
/*
* Copyright (c) 2009, 2010 Genetec Corporation. All rights reserved.
* Written by Hashimoto Kenichi for Genetec Corporation.
@@ -29,18 +29,15 @@
#define _ARM_IMX_IMXUSBREG_H
#define IMXUSB_ID 0x0000
-#define IMXUSB_ID_ID_MASK __BITS(5,0)
-#define IMXUSB_ID_REVISION_SHIFT 16
-#define IMXUSB_ID_REVISION_MASK __BITS(IMXUSB_ID_REVISION_SHIFT,23)
+#define IMXUSB_ID_ID __BITS(5,0)
+#define IMXUSB_ID_REVISION __BITS(23,16)
#define IMXUSB_HWGENERAL 0x0004
#define IMXUSB_HWHOST 0x0008
-#define HWHOST_HC __BIT(0)
-#define HWHOST_NPORT_SHIFT 1
-#define HWHOST_NPORT_MASK __BITS(HWHOST_NPORT_SHIFT,3)
+#define HWHOST_HC __BIT(0)
+#define HWHOST_NPORT __BITS(3,1)
#define IMXUSB_HWDEVICE 0x000c
-#define HWDEVICE_DC __BIT(0)
-#define HWDEVICE_DEVEP_SHIFT 1
-#define HWDEVICE_DEVEP_MASK __BITS(HWDEVICE_DEVEP_SHIFT,5)
+#define HWDEVICE_DC __BIT(0)
+#define HWDEVICE_DEVEP __BITS(5,1)
#define IMXUSB_HWTXBUF 0x0010
#define IMXUSB_HWRXBUF 0x0014
@@ -51,14 +48,10 @@
#define ULPI_RUN __BIT(30)
#define ULPI_RW __BIT(29)
#define ULPI_SS __BIT(27)
-#define ULPI_PORT_SHIFT 24
-#define ULPI_PORT_MASK (0x7 << ULPI_PORT_SHIFT)
-#define ULPI_ADDR_SHIFT 16
-#define ULPI_ADDR_MASK (0xff << ULPI_ADDR_SHIFT)
-#define ULPI_DATRD_SHIFT 8
-#define ULPI_DATRD_MASK (0xff << ULPI_DATRD_SHIFT)
-#define ULPI_DATWR_SHIFT 0
-#define ULPI_DATWR_MASK (0xff << ULPI_DATWR_SHIFT)
+#define ULPI_PORT __BITS(26,24)
+#define ULPI_ADDR __BITS(23,16)
+#define ULPI_DATRD __BITS(15,8)
+#define ULPI_DATWR __BITS(7,0)
#define IMXUSB_OTGSC 0x01A4
#define OTGSC_DPIE __BIT(30)
@@ -88,24 +81,25 @@
#define OTGSC_VC __BIT( 1)
#define OTGSC_VD __BIT( 0)
#define IMXUSB_OTGMODE 0x01A8
-#define USBMODE_DEVICE (0x2 << 0)
-#define USBMODE_HOST (0x3 << 0)
+#define USBMODE_CM __BITS(1,0)
+#define USBMODE_CM_IDLE __SHIFTIN(0,USBMODE_CM)
+#define USBMODE_CM_DEVICE __SHIFTIN(2,USBMODE_CM)
+#define USBMODE_CM_HOST __SHIFTIN(3,USBMODE_CM)
#define IMXUSB_EHCI_SIZE 0x200
/* extension to PORTSCx register of EHCI. */
-#define PORTSC_PTS_SHIFT 30
-#define PORTSC_PTS_MASK __BITS(PORTSC_PTS_SHIFT,31)
-#define PORTSC_PTS_UTMI (0 << PORTSC_PTS_SHIFT)
-#define PORTSC_PTS_PHILIPS (1 << PORTSC_PTS_SHIFT) /* not in i.MX51*/
-#define PORTSC_PTS_ULPI (2 << PORTSC_PTS_SHIFT)
-#define PORTSC_PTS_SERIAL (3 << PORTSC_PTS_SHIFT)
+#define PORTSC_PTS __BITS(31,30)
+#define PORTSC_PTS_UTMI __SHIFTIN(0,PORTSC_PTS)
+#define PORTSC_PTS_PHILIPS __SHIFTIN(1,PORTSC_PTS) /* not in i.MX51*/
+#define PORTSC_PTS_ULPI __SHIFTIN(2,PORTSC_PTS)
+#define PORTSC_PTS_SERIAL __SHIFTIN(3,PORTSC_PTS)
#define PORTSC_STS __BIT(29) /* serial transeiver select */
#define PORTSC_PTW __BIT(28) /* parallel transceiver width */
#define PORTSC_PTW_8 0
-#define PORTSC_PTW_16 PORT_SC_PTW
+#define PORTSC_PTW_16 PORTSC_PTW
#define PORTSC_PSPD __BITS(26,27) /* port speed (RO) */
#define PORTSC_PFSC __BIT(24) /* port force full speed */
#define PORTSC_PHCD __BIT(23) /* PHY low power suspend */
Index: src/sys/arch/arm/imx/imxusbvar.h
diff -u src/sys/arch/arm/imx/imxusbvar.h:1.1 src/sys/arch/arm/imx/imxusbvar.h:1.2
--- src/sys/arch/arm/imx/imxusbvar.h:1.1 Tue Nov 30 13:05:27 2010
+++ src/sys/arch/arm/imx/imxusbvar.h Fri Jul 25 07:49:56 2014
@@ -30,7 +30,8 @@ enum imx_usb_if {
IMXUSBC_IF_UTMI,
IMXUSBC_IF_PHILIPS,
IMXUSBC_IF_ULPI,
- IMXUSBC_IF_SERIAL
+ IMXUSBC_IF_SERIAL,
+ IMXUSBC_IF_UTMI_WIDE
};
struct imxehci_softc {
Index: src/sys/arch/arm/imx/imx51_tzic.c
diff -u src/sys/arch/arm/imx/imx51_tzic.c:1.6 src/sys/arch/arm/imx/imx51_tzic.c:1.7
--- src/sys/arch/arm/imx/imx51_tzic.c:1.6 Mon Mar 10 09:35:18 2014
+++ src/sys/arch/arm/imx/imx51_tzic.c Fri Jul 25 07:49:56 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: imx51_tzic.c,v 1.6 2014/03/10 09:35:18 skrll Exp $ */
+/* $NetBSD: imx51_tzic.c,v 1.7 2014/07/25 07:49:56 hkenken Exp $ */
/*-
* Copyright (c) 2010 SHIMIZU Ryo <r...@nerv.org>
@@ -26,10 +26,11 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: imx51_tzic.c,v 1.6 2014/03/10 09:35:18 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: imx51_tzic.c,v 1.7 2014/07/25 07:49:56 hkenken Exp $");
#define _INTR_PRIVATE /* for arm/pic/picvar.h */
+#include "opt_imx.h"
#include "locators.h"
#include <sys/param.h>
Index: src/sys/arch/arm/imx/imxclock.c
diff -u src/sys/arch/arm/imx/imxclock.c:1.6 src/sys/arch/arm/imx/imxclock.c:1.7
--- src/sys/arch/arm/imx/imxclock.c:1.6 Sun May 20 14:08:18 2012
+++ src/sys/arch/arm/imx/imxclock.c Fri Jul 25 07:49:56 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: imxclock.c,v 1.6 2012/05/20 14:08:18 matt Exp $ */
+/* $NetBSD: imxclock.c,v 1.7 2014/07/25 07:49:56 hkenken Exp $ */
/*
* Copyright (c) 2009, 2010 Genetec corp. All rights reserved.
* Written by Hashimoto Kenichi for Genetec corp.
@@ -29,6 +29,11 @@
* common part for i.MX31 and i.MX51
*/
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: imxclock.c,v 1.7 2014/07/25 07:49:56 hkenken Exp $");
+
+#include "opt_imx.h"
+
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
@@ -65,6 +70,7 @@ static struct timecounter imx_epit_timec
};
static volatile uint32_t imxclock_base;
+struct imxclock_softc *imxclock = NULL;
void
cpu_initclocks(void)
@@ -72,48 +78,43 @@ cpu_initclocks(void)
uint32_t reg;
u_int freq;
- if (!epit1_sc) {
+ if (epit1_sc != NULL)
+ imxclock = epit1_sc;
+ else if (epit2_sc != NULL)
+ imxclock = epit2_sc;
+ else
panic("%s: driver has not been initialized!", __FUNCTION__);
- }
- freq = imxclock_get_timerfreq(epit1_sc);
+ freq = imxclock_get_timerfreq(imxclock);
imx_epit_timecounter.tc_frequency = freq;
tc_init(&imx_epit_timecounter);
- aprint_verbose_dev(epit1_sc->sc_dev,
- "timer clock frequency %d\n", freq);
+ aprint_verbose_dev(imxclock->sc_dev,
+ "timer clock frequency %d\n", freq);
- epit1_sc->sc_reload_value = freq / hz - 1;
+ imxclock->sc_reload_value = freq / hz - 1;
- /* stop all timers */
- bus_space_write_4(epit1_sc->sc_iot, epit1_sc->sc_ioh, EPIT_EPITCR, 0);
- bus_space_write_4(epit2_sc->sc_iot, epit2_sc->sc_ioh, EPIT_EPITCR, 0);
+ /* stop timers */
+ bus_space_write_4(imxclock->sc_iot, imxclock->sc_ioh, EPIT_EPITCR, 0);
aprint_normal("clock: hz=%d stathz = %d\n", hz, stathz);
- bus_space_write_4(epit1_sc->sc_iot, epit1_sc->sc_ioh, EPIT_EPITLR,
- epit1_sc->sc_reload_value);
- bus_space_write_4(epit1_sc->sc_iot, epit1_sc->sc_ioh, EPIT_EPITCMPR, 0);
+ bus_space_write_4(imxclock->sc_iot, imxclock->sc_ioh, EPIT_EPITLR,
+ imxclock->sc_reload_value);
+ bus_space_write_4(imxclock->sc_iot, imxclock->sc_ioh, EPIT_EPITCMPR, 0);
- reg = EPITCR_ENMOD | EPITCR_IOVW | EPITCR_RLD | epit1_sc->sc_clksrc;
- bus_space_write_4(epit1_sc->sc_iot, epit1_sc->sc_ioh,
+ reg = EPITCR_ENMOD | EPITCR_IOVW | EPITCR_RLD | imxclock->sc_clksrc;
+ bus_space_write_4(imxclock->sc_iot, imxclock->sc_ioh,
EPIT_EPITCR, reg);
reg |= EPITCR_EN | EPITCR_OCIEN | EPITCR_WAITEN | EPITCR_DOZEN |
EPITCR_STOPEN;
- bus_space_write_4(epit1_sc->sc_iot, epit1_sc->sc_ioh,
+ bus_space_write_4(imxclock->sc_iot, imxclock->sc_ioh,
EPIT_EPITCR, reg);
- epit1_sc->sc_ih = intr_establish(epit1_sc->sc_intr, IPL_CLOCK,
+ epit1_sc->sc_ih = intr_establish(imxclock->sc_intr, IPL_CLOCK,
IST_LEVEL, imxclock_intr, NULL);
}
-#if 0
-void
-microtime(struct timeval *tvp)
-{
-}
-#endif
-
void
setstatclockrate(int schz)
{
@@ -122,7 +123,7 @@ setstatclockrate(int schz)
static int
imxclock_intr(void *arg)
{
- struct imxclock_softc *sc = epit1_sc;
+ struct imxclock_softc *sc = imxclock;
bus_space_write_4(sc->sc_iot, sc->sc_ioh, EPIT_EPITSR, 1);
atomic_add_32(&imxclock_base, sc->sc_reload_value);
@@ -140,7 +141,7 @@ imx_epit_get_timecount(struct timecounte
u_int oldirqstate;
oldirqstate = disable_interrupts(I32_bit);
- counter = bus_space_read_4(epit1_sc->sc_iot, epit1_sc->sc_ioh, EPIT_EPITCNT);
+ counter = bus_space_read_4(imxclock->sc_iot, imxclock->sc_ioh, EPIT_EPITCNT);
base = imxclock_base;
restore_interrupts(oldirqstate);
Added files:
Index: src/sys/arch/arm/imx/imx50_iomuxreg.h
diff -u /dev/null src/sys/arch/arm/imx/imx50_iomuxreg.h:1.1
--- /dev/null Fri Jul 25 07:49:57 2014
+++ src/sys/arch/arm/imx/imx50_iomuxreg.h Fri Jul 25 07:49:56 2014
@@ -0,0 +1,563 @@
+/* $NetBSD: imx50_iomuxreg.h,v 1.1 2014/07/25 07:49:56 hkenken Exp $ */
+
+/*
+ * Copyright (c) 2012 Genetec Corporation. All rights reserved.
+ * Written by Hashimoto Kenichi for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file was generated automatically from PDF file by mkiomuxreg_imx50.rb
+ */
+
+#ifndef _ARM_IMX_IMX50_IOMUXREG_H
+#define _ARM_IMX_IMX50_IOMUXREG_H
+
+/* register offset address */
+
+#define IOMUXC_GPR0 0x0000
+#define IOMUXC_GPR1 0x0004
+#define IOMUXC_GPR2 0x0008
+#define IOMUXC_OBSERVE_MUX_0 0x000C
+#define IOMUXC_OBSERVE_MUX_1 0x0010
+#define IOMUXC_OBSERVE_MUX_2 0x0014
+#define IOMUXC_OBSERVE_MUX_3 0x0018
+#define IOMUXC_OBSERVE_MUX_4 0x001C
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL0 0x0020
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0 0x0024
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL1 0x0028
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1 0x002C
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL2 0x0030
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2 0x0034
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL3 0x0038
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3 0x003C
+#define IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL 0x0040
+#define IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA 0x0044
+#define IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL 0x0048
+#define IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA 0x004C
+#define IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL 0x0050
+#define IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA 0x0054
+#define IOMUXC_SW_MUX_CTL_PAD_PWM1 0x0058
+#define IOMUXC_SW_MUX_CTL_PAD_PWM2 0x005C
+#define IOMUXC_SW_MUX_CTL_PAD_OWIRE 0x0060
+#define IOMUXC_SW_MUX_CTL_PAD_EPITO 0x0064
+#define IOMUXC_SW_MUX_CTL_PAD_WDOG 0x0068
+#define IOMUXC_SW_MUX_CTL_PAD_SSI_TXFS 0x006C
+#define IOMUXC_SW_MUX_CTL_PAD_SSI_TXC 0x0070
+#define IOMUXC_SW_MUX_CTL_PAD_SSI_TXD 0x0074
+#define IOMUXC_SW_MUX_CTL_PAD_SSI_RXD 0x0078
+#define IOMUXC_SW_MUX_CTL_PAD_SSI_RXF 0x007C
+#define IOMUXC_SW_MUX_CTL_PAD_SSI_RXC 0x0080
+#define IOMUXC_SW_MUX_CTL_PAD_UART1_TXD 0x0084
+#define IOMUXC_SW_MUX_CTL_PAD_UART1_RXD 0x0088
+#define IOMUXC_SW_MUX_CTL_PAD_UART1_CTS 0x008C
+#define IOMUXC_SW_MUX_CTL_PAD_UART1_RTS 0x0090
+#define IOMUXC_SW_MUX_CTL_PAD_UART2_TXD 0x0094
+#define IOMUXC_SW_MUX_CTL_PAD_UART2_RXD 0x0098
+#define IOMUXC_SW_MUX_CTL_PAD_UART2_CTS 0x009C
+#define IOMUXC_SW_MUX_CTL_PAD_UART2_RTS 0x00A0
+#define IOMUXC_SW_MUX_CTL_PAD_UART3_TXD 0x00A4
+#define IOMUXC_SW_MUX_CTL_PAD_UART3_RXD 0x00A8
+#define IOMUXC_SW_MUX_CTL_PAD_UART4_TXD 0x00AC
+#define IOMUXC_SW_MUX_CTL_PAD_UART4_RXD 0x00B0
+#define IOMUXC_SW_MUX_CTL_PAD_CSPI_SCLK 0x00B4
+#define IOMUXC_SW_MUX_CTL_PAD_CSPI_MOSI 0x00B8
+#define IOMUXC_SW_MUX_CTL_PAD_CSPI_MISO 0x00BC
+#define IOMUXC_SW_MUX_CTL_PAD_CSPI_SS0 0x00C0
+#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK 0x00C4
+#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI 0x00C8
+#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO 0x00CC
+#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0 0x00D0
+#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK 0x00D4
+#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI 0x00D8
+#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO 0x00DC
+#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0 0x00E0
+#define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK 0x00E4
+#define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD 0x00E8
+#define IOMUXC_SW_MUX_CTL_PAD_SD1_D0 0x00EC
+#define IOMUXC_SW_MUX_CTL_PAD_SD1_D1 0x00F0
+#define IOMUXC_SW_MUX_CTL_PAD_SD1_D2 0x00F4
+#define IOMUXC_SW_MUX_CTL_PAD_SD1_D3 0x00F8
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK 0x00FC
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD 0x0100
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_D0 0x0104
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_D1 0x0108
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_D2 0x010C
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_D3 0x0110
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_D4 0x0114
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_D5 0x0118
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_D6 0x011C
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_D7 0x0120
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_WP 0x0124
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_CD 0x0128
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_D0 0x012C
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_D1 0x0130
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_D2 0x0134
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_D3 0x0138
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_D4 0x013C
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_D5 0x0140
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_D6 0x0144
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_D7 0x0148
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_WR 0x014C
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_RD 0x0150
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_RS 0x0154
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_CS 0x0158
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_BUSY 0x015C
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_RESET 0x0160
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD 0x0164
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK 0x0168
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_D0 0x016C
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_D1 0x0170
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_D2 0x0174
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_D3 0x0178
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_D4 0x017C
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_D5 0x0180
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_D6 0x0184
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_D7 0x0188
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_WP 0x018C
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_D8 0x0190
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_D9 0x0194
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_D10 0x0198
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_D11 0x019C
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_D12 0x01A0
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_D13 0x01A4
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_D14 0x01A8
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_D15 0x01AC
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_D0 0x01B0
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_D1 0x01B4
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_D2 0x01B8
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_D3 0x01BC
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_D4 0x01C0
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_D5 0x01C4
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_D6 0x01C8
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_D7 0x01CC
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_D8 0x01D0
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_D9 0x01D4
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_D10 0x01D8
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_D11 0x01DC
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_D12 0x01E0
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_D13 0x01E4
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_D14 0x01E8
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_D15 0x01EC
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDCLK 0x01F0
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDSP 0x01F4
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDOE 0x01F8
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDRL 0x01FC
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCLK 0x0200
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOEZ 0x0204
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOED 0x0208
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOE 0x020C
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDLE 0x0210
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCLKN 0x0214
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDSHR 0x0218
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWRCOM 0x021C
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWRSTAT 0x0220
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWRCTRL0 0x0224
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWRCTRL1 0x0228
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWRCTRL2 0x022C
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWRCTRL3 0x0230
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_VCOM0 0x0234
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_VCOM1 0x0238
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR0 0x023C
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR1 0x0240
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE0 0x0244
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE1 0x0248
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE2 0x024C
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE3 0x0250
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE4 0x0254
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE5 0x0258
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA0 0x025C
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA1 0x0260
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA2 0x0264
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA3 0x0268
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA4 0x026C
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA5 0x0270
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA6 0x0274
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA7 0x0278
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA8 0x027C
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA9 0x0280
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA10 0x0284
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA11 0x0288
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA12 0x028C
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA13 0x0290
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA14 0x0294
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA15 0x0298
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS2 0x029C
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS1 0x02A0
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS0 0x02A4
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB0 0x02A8
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB1 0x02AC
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT 0x02B0
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK 0x02B4
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_RDY 0x02B8
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_OE 0x02BC
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_RW 0x02C0
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_LBA 0x02C4
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_CRE 0x02C8
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0 0x02CC
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0 0x02D0
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1 0x02D4
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1 0x02D8
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2 0x02DC
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2 0x02E0
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3 0x02E4
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3 0x02E8
+#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL 0x02EC
+#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA 0x02F0
+#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL 0x02F4
+#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA 0x02F8
+#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL 0x02FC
+#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA 0x0300
+#define IOMUXC_SW_PAD_CTL_PAD_PWM1 0x0304
+#define IOMUXC_SW_PAD_CTL_PAD_PWM2 0x0308
+#define IOMUXC_SW_PAD_CTL_PAD_OWIRE 0x030C
+#define IOMUXC_SW_PAD_CTL_PAD_EPITO 0x0310
+#define IOMUXC_SW_PAD_CTL_PAD_WDOG 0x0314
+#define IOMUXC_SW_PAD_CTL_PAD_SSI_TXFS 0x0318
+#define IOMUXC_SW_PAD_CTL_PAD_SSI_TXC 0x031C
+#define IOMUXC_SW_PAD_CTL_PAD_SSI_TXD 0x0320
+#define IOMUXC_SW_PAD_CTL_PAD_SSI_RXD 0x0324
+#define IOMUXC_SW_PAD_CTL_PAD_SSI_RXFS 0x0328
+#define IOMUXC_SW_PAD_CTL_PAD_SSI_RXC 0x032C
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_TXD 0x0330
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_RXD 0x0334
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_CTS 0x0338
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_RTS 0x033C
+#define IOMUXC_SW_PAD_CTL_PAD_UART2_TXD 0x0340
+#define IOMUXC_SW_PAD_CTL_PAD_UART2_RXD 0x0344
+#define IOMUXC_SW_PAD_CTL_PAD_UART2_CTS 0x0348
+#define IOMUXC_SW_PAD_CTL_PAD_UART2_RTS 0x034C
+#define IOMUXC_SW_PAD_CTL_PAD_UART3_TXD 0x0350
+#define IOMUXC_SW_PAD_CTL_PAD_UART3_RXD 0x0354
+#define IOMUXC_SW_PAD_CTL_PAD_UART4_TXD 0x0358
+#define IOMUXC_SW_PAD_CTL_PAD_UART4_RXD 0x035C
+#define IOMUXC_SW_PAD_CTL_PAD_CSPI_SCLK 0x0360
+#define IOMUXC_SW_PAD_CTL_PAD_CSPI_MOSI 0x0364
+#define IOMUXC_SW_PAD_CTL_PAD_CSPI_MISO 0x0368
+#define IOMUXC_SW_PAD_CTL_PAD_CSPI_SS0 0x036C
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK 0x0370
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI 0x0374
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO 0x0378
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0 0x037C
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK 0x0380
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI 0x0384
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO 0x0388
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0 0x038C
+#define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK 0x0390
+#define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD 0x0394
+#define IOMUXC_SW_PAD_CTL_PAD_SD1_D0 0x0398
+#define IOMUXC_SW_PAD_CTL_PAD_SD1_D1 0x039C
+#define IOMUXC_SW_PAD_CTL_PAD_SD1_D2 0x03A0
+#define IOMUXC_SW_PAD_CTL_PAD_SD1_D3 0x03A4
+#define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK 0x03A8
+#define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD 0x03AC
+#define IOMUXC_SW_PAD_CTL_PAD_SD2_D0 0x03B0
+#define IOMUXC_SW_PAD_CTL_PAD_SD2_D1 0x03B4
+#define IOMUXC_SW_PAD_CTL_PAD_SD2_D2 0x03B8
+#define IOMUXC_SW_PAD_CTL_PAD_SD2_D3 0x03BC
+#define IOMUXC_SW_PAD_CTL_PAD_SD2_D4 0x03C0
+#define IOMUXC_SW_PAD_CTL_PAD_SD2_D5 0x03C4
+#define IOMUXC_SW_PAD_CTL_PAD_SD2_D6 0x03C8
+#define IOMUXC_SW_PAD_CTL_PAD_SD2_D7 0x03CC
+#define IOMUXC_SW_PAD_CTL_PAD_SD2_WP 0x03D0
+#define IOMUXC_SW_PAD_CTL_PAD_SD2_CD 0x03D4
+#define IOMUXC_SW_PAD_CTL_PAD_PMIC_ON_REQ 0x03D8
+#define IOMUXC_SW_PAD_CTL_PAD_PMIC_STBY_REQ 0x03DC
+#define IOMUXC_SW_PAD_CTL_PAD_POR_B 0x03E0
+#define IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE1 0x03E4
+#define IOMUXC_SW_PAD_CTL_PAD_RESET_IN_B 0x03E8
+#define IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE0 0x03EC
+#define IOMUXC_SW_PAD_CTL_PAD_TEST_MODE 0x03F0
+#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS 0x03F4
+#define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD 0x03F8
+#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB 0x03FC
+#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI 0x0400
+#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK 0x0404
+#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO 0x0408
+#define IOMUXC_SW_PAD_CTL_PAD_DISP_D0 0x040C
+#define IOMUXC_SW_PAD_CTL_PAD_DISP_D1 0x0410
+#define IOMUXC_SW_PAD_CTL_PAD_DISP_D2 0x0414
+#define IOMUXC_SW_PAD_CTL_PAD_DISP_D3 0x0418
+#define IOMUXC_SW_PAD_CTL_PAD_DISP_D4 0x041C
+#define IOMUXC_SW_PAD_CTL_PAD_DISP_D5 0x0420
+#define IOMUXC_SW_PAD_CTL_PAD_DISP_D6 0x0424
+#define IOMUXC_SW_PAD_CTL_PAD_DISP_D7 0x0428
+#define IOMUXC_SW_PAD_CTL_PAD_DISP_WR 0x042C
+#define IOMUXC_SW_PAD_CTL_PAD_DISP_RD 0x0430
+#define IOMUXC_SW_PAD_CTL_PAD_DISP_RS 0x0434
+#define IOMUXC_SW_PAD_CTL_PAD_DISP_CS 0x0438
+#define IOMUXC_SW_PAD_CTL_PAD_DISP_BUSY 0x043C
+#define IOMUXC_SW_PAD_CTL_PAD_DISP_RESET 0x0440
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD 0x0444
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK 0x0448
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_D0 0x044C
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_D1 0x0450
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_D2 0x0454
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_D3 0x0458
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_D4 0x045C
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_D5 0x0460
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_D6 0x0464
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_D7 0x0468
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_WP 0x046C
+#define IOMUXC_SW_PAD_CTL_PAD_DISP_D8 0x0470
+#define IOMUXC_SW_PAD_CTL_PAD_DISP_D9 0x0474
+#define IOMUXC_SW_PAD_CTL_PAD_DISP_D10 0x0478
+#define IOMUXC_SW_PAD_CTL_PAD_DISP_D11 0x047C
+#define IOMUXC_SW_PAD_CTL_PAD_DISP_D12 0x0480
+#define IOMUXC_SW_PAD_CTL_PAD_DISP_D13 0x0484
+#define IOMUXC_SW_PAD_CTL_PAD_DISP_D14 0x0488
+#define IOMUXC_SW_PAD_CTL_PAD_DISP_D15 0x048C
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_OPEN 0x0490
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_OPENFB 0x0494
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 0x0498
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 0x049C
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE 0x04A0
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 0x04A4
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_D16 0x04A8
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_D17 0x04AC
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_D18 0x04B0
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_D19 0x04B4
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_D20 0x04B8
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_D21 0x04BC
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_D22 0x04C0
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_D23 0x04C4
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 0x04C8
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 0x04CC
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_D0 0x04D0
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_D1 0x04D4
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_D2 0x04D8
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_D3 0x04DC
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_D4 0x04E0
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_D5 0x04E4
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_D6 0x04E8
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_D7 0x04EC
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 0x04F0
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 0x04F4
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 0x04F8
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 0x04FC
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 0x0500
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_D8 0x0504
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_D9 0x0508
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_D10 0x050C
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_D11 0x0510
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_D12 0x0514
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_D13 0x0518
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_D14 0x051C
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_D15 0x0520
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 0x0524
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 0x0528
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_D24 0x052C
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_D25 0x0530
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_D26 0x0534
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_D27 0x0538
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_D28 0x053C
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_D29 0x0540
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_D30 0x0544
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_D31 0x0548
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_D0 0x054C
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_D1 0x0550
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_D2 0x0554
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_D3 0x0558
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_D4 0x055C
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_D5 0x0560
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_D6 0x0564
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_D7 0x0568
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_D8 0x056C
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_D9 0x0570
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_D10 0x0574
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_D11 0x0578
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_D12 0x057C
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_D13 0x0580
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_D14 0x0584
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_D15 0x0588
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK 0x058C
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP 0x0590
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE 0x0594
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL 0x0598
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK 0x059C
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOEZ 0x05A0
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOED 0x05A4
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE 0x05A8
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE 0x05AC
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLKN 0x05B0
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR 0x05B4
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWRCOM 0x05B8
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWRSTAT 0x05BC
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWRCTRL0 0x05C0
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWRCTRL1 0x05C4
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWRCTRL2 0x05C8
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWRCTRL3 0x05CC
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_VCOM0 0x05D0
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_VCOM1 0x05D4
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0 0x05D8
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1 0x05DC
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0 0x05E0
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1 0x05E4
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2 0x05E8
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3 0x05EC
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE4 0x05F0
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE5 0x05F4
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_DA0 0x05F8
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_DA1 0x05FC
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_DA2 0x0600
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_DA3 0x0604
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_DA4 0x0608
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_DA5 0x060C
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_DA6 0x0610
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_DA7 0x0614
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_DA8 0x0618
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_DA9 0x061C
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_DA10 0x0620
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_DA11 0x0624
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_DA12 0x0628
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_DA13 0x062C
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_DA14 0x0630
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_DA15 0x0634
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS2 0x0638
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS1 0x063C
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS0 0x0640
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB0 0x0644
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB1 0x0648
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT 0x064C
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK 0x0650
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_RDY 0x0654
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_OE 0x0658
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_RW 0x065C
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_LBA 0x0660
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_CRE 0x0664
+#define IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x0668
+#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 0x066C
+#define IOMUXC_SW_PAD_CTL_GRP_DDRPKE 0x0670
+#define IOMUXC_SW_PAD_CTL_GRP_EIM 0x0674
+#define IOMUXC_SW_PAD_CTL_GRP_EPDC 0x0678
+#define IOMUXC_SW_PAD_CTL_GRP_UART 0x067C
+#define IOMUXC_SW_PAD_CTL_GRP_DDRPK 0x0680
+#define IOMUXC_SW_PAD_CTL_GRP_DDRHYS 0x0684
+#define IOMUXC_SW_PAD_CTL_GRP_KEYPAD 0x0688
+#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE 0x068C
+#define IOMUXC_SW_PAD_CTL_GRP_SSI 0x0690
+#define IOMUXC_SW_PAD_CTL_GRP_SD1 0x0694
+#define IOMUXC_SW_PAD_CTL_GRP_B0DS 0x0698
+#define IOMUXC_SW_PAD_CTL_GRP_SD2 0x069C
+#define IOMUXC_SW_PAD_CTL_GRP_B1DS 0x06A0
+#define IOMUXC_SW_PAD_CTL_GRP_CTLDS 0x06A4
+#define IOMUXC_SW_PAD_CTL_GRP_B2DS 0x06A8
+#define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE 0x06AC
+#define IOMUXC_SW_PAD_CTL_GRP_LCD 0x06B0
+#define IOMUXC_SW_PAD_CTL_GRP_B3DS 0x06B4
+#define IOMUXC_SW_PAD_CTL_GRP_MISC 0x06B8
+#define IOMUXC_SW_PAD_CTL_GRP_SPI 0x06BC
+#define IOMUXC_SW_PAD_CTL_GRP_NANDF 0x06C0
+#define IOMUXC_AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT 0x06C4
+#define IOMUXC_AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT 0x06C8
+#define IOMUXC_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT 0x06CC
+#define IOMUXC_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT 0x06D0
+#define IOMUXC_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT 0x06D4
+#define IOMUXC_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT 0x06D8
+#define IOMUXC_CCM_PLL1_BYPASS_CLK_SELECT_INPUT 0x06DC
+#define IOMUXC_CCM_PLL2_BYPASS_CLK_SELECT_INPUT 0x06E0
+#define IOMUXC_CCM_PLL3_BYPASS_CLK_SELECT_INPUT 0x06E4
+#define IOMUXC_CSPI_IPP_IND_DATAREADY_B_SELECT_INPUT 0x06E8
+#define IOMUXC_CSPI_IPP_IND_SS1_B_SELECT_INPUT 0x06EC
+#define IOMUXC_CSPI_IPP_IND_SS2_B_SELECT_INPUT 0x06F0
+#define IOMUXC_CSPI_IPP_IND_SS3_B_SELECT_INPUT 0x06F4
+#define IOMUXC_ELCDIF_LCDIF_BUSY_SELECT_INPUT 0x06F8
+#define IOMUXC_ELCDIF_LCDIF_RXDATA_0_SELECT_INPUT 0x06FC
+#define IOMUXC_ELCDIF_LCDIF_RXDATA_1_SELECT_INPUT 0x0700
+#define IOMUXC_ELCDIF_LCDIF_RXDATA_2_SELECT_INPUT 0x0704
+#define IOMUXC_ELCDIF_LCDIF_RXDATA_3_SELECT_INPUT 0x0708
+#define IOMUXC_ELCDIF_LCDIF_RXDATA_4_SELECT_INPUT 0x070C
+#define IOMUXC_ELCDIF_LCDIF_RXDATA_5_SELECT_INPUT 0x0710
+#define IOMUXC_ELCDIF_LCDIF_RXDATA_6_SELECT_INPUT 0x0714
+#define IOMUXC_ELCDIF_LCDIF_RXDATA_7_SELECT_INPUT 0x0718
+#define IOMUXC_ELCDIF_LCDIF_RXDATA_8_SELECT_INPUT 0x071C
+#define IOMUXC_C_ELCDIF_LCDIF_RXDATA_9_SELECT_INPUT 0x0720
+#define IOMUXC_ELCDIF_LCDIF_RXDATA_10_SELECT_INPUT 0x0724
+#define IOMUXC_ELCDIF_LCDIF_RXDATA_11_SELECT_INPUT 0x0728
+#define IOMUXC_ELCDIF_LCDIF_RXDATA_12_SELECT_INPUT 0x072C
+#define IOMUXC_ELCDIF_LCDIF_RXDATA_13_SELECT_INPUT 0x0730
+#define IOMUXC_ELCDIF_LCDIF_RXDATA_14_SELECT_INPUT 0x0734
+#define IOMUXC_ELCDIF_LCDIF_RXDATA_15_SELECT_INPUT 0x0738
+#define IOMUXC_ELCDIF_VSYNC_I_SELECT_INPUT 0x073C
+#define IOMUXC_ESDHC2_IPP_CARD_DET_SELECT_INPUT 0x0740
+#define IOMUXC_ESDHC2_IPP_WP_ON_SELECT_INPUT 0x0744
+#define IOMUXC_ESDHC4_IPP_CARD_CLK_IN_SELECT_INPUT 0x0748
+#define IOMUXC_ESDHC4_IPP_CMD_IN_SELECT_INPUT 0x074C
+#define IOMUXC_ESDHC4_IPP_DAT0_IN_SELECT_INPUT 0x0750
+#define IOMUXC_XC_ESDHC4_IPP_DAT1_IN_SELECT_INPUT 0x0754
+#define IOMUXC_ESDHC4_IPP_DAT2_IN_SELECT_INPUT 0x0758
+#define IOMUXC_ESDHC4_IPP_DAT3_IN_SELECT_INPUT 0x075C
+#define IOMUXC_ESDHC4_IPP_DAT4_IN_SELECT_INPUT 0x0760
+#define IOMUXC_ESDHC4_IPP_DAT5_IN_SELECT_INPUT 0x0764
+#define IOMUXC_ESDHC4_IPP_DAT6_IN_SELECT_INPUT 0x0768
+#define IOMUXC_ESDHC4_IPP_DAT7_IN_SELECT_INPUT 0x076C
+#define IOMUXC_FEC_FEC_COL_SELECT_INPUT 0x0770
+#define IOMUXC_FEC_FEC_MDI_SELECT_INPUT 0x0774
+#define IOMUXC_FEC_FEC_RDATA_0_SELECT_INPUT 0x0778
+#define IOMUXC_FEC_FEC_RDATA_1_SELECT_INPUT 0x077C
+#define IOMUXC_FEC_FEC_RX_CLK_SELECT_INPUT 0x0780
+#define IOMUXC_FEC_FEC_RX_DV_SELECT_INPUT 0x0784
+#define IOMUXC_FEC_FEC_RX_ER_SELECT_INPUT 0x0788
+#define IOMUXC_FEC_FEC_TX_CLK_SELECT_INPUT 0x078C
+#define IOMUXC_KPP_IPP_IND_COL_4_SELECT_INPUT 0x0790
+#define IOMUXC_KPP_IPP_IND_COL_5_SELECT_INPUT 0x0794
+#define IOMUXC_KPP_IPP_IND_COL_6_SELECT_INPUT 0x0798
+#define IOMUXC_KPP_IPP_IND_COL_7_SELECT_INPUT 0x079C
+#define IOMUXC_KPP_IPP_IND_ROW_4_SELECT_INPUT 0x07A0
+#define IOMUXC_KPP_IPP_IND_ROW_5_SELECT_INPUT 0x07A4
+#define IOMUXC_KPP_IPP_IND_ROW_6_SELECT_INPUT 0x07A8
+#define IOMUXC_KPP_IPP_IND_ROW_7_SELECT_INPUT 0x07AC
+#define IOMUXC_RAWNAND_U_GPMI_INPUT_GPMI_DQS_IN_SELECT_INPUT 0x07B0
+#define IOMUXC_RAWNAND_U_GPMI_INPUT_GPMI_RDY0_SELECT_INPUT 0x07B4
+#define IOMUXC_SDMA_EVENTS_14_SELECT_INPUT 0x07B8
+#define IOMUXC_SDMA_EVENTS_15_SELECT_INPUT 0x07BC
+#define IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT 0x07C0
+#define IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT 0x07C4
+#define IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT 0x07C8
+#define IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT 0x07CC
+#define IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT 0x07D0
+#define IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT 0x07D4
+#define IOMUXC_UART4_IPP_UART_RTS_B_SELECT_INPUT 0x07D8
+#define IOMUXC_UART4_IPP_UART_RXD_MUX_SELECT_INPUT 0x07DC
+#define IOMUXC_UART5_IPP_UART_RTS_B_SELECT_INPUT 0x07E0
+#define IOMUXC_UART5_IPP_UART_RXD_MUX_SELECT_INPUT 0x07E4
+#define IOMUXC_USBOH1_IPP_IND_OTG_OC_SELECT_INPUT 0x07E8
+#define IOMUXC_WEIMV2_IPP_IND_READ_DATA_0_SELECT_INPUT 0x07EC
+#define IOMUXC_WEIMV2_IPP_IND_READ_DATA_1_SELECT_INPUT 0x07F0
+#define IOMUXC_WEIMV2_IPP_IND_READ_DATA_2_SELECT_INPUT 0x07F4
+#define IOMUXC_WEIMV2_IPP_IND_READ_DATA_3_SELECT_INPUT 0x07F8
+#define IOMUXC_WEIMV2_IPP_IND_READ_DATA_4_SELECT_INPUT 0x07FC
+#define IOMUXC_WEIMV2_IPP_IND_READ_DATA_5_SELECT_INPUT 0x0800
+#define IOMUXC_WEIMV2_IPP_IND_READ_DATA_6_SELECT_INPUT 0x0804
+#define IOMUXC_WEIMV2_IPP_IND_READ_DATA_7_SELECT_INPUT 0x0808
+#define IOMUXC_WEIMV2_IPP_IND_READ_DATA_8_SELECT_INPUT 0x080C
+#define IOMUXC_WEIMV2_IPP_IND_READ_DATA_9_SELECT_INPUT 0x0810
+#define IOMUXC_WEIMV2_IPP_IND_READ_DATA_10_SELECT_INPUT 0x0814
+#define IOMUXC_WEIMV2_IPP_IND_READ_DATA_11_SELECT_INPUT 0x0818
+#define IOMUXC_WEIMV2_IPP_IND_READ_DATA_12_SELECT_INPUT 0x081C
+#define IOMUXC_WEIMV2_IPP_IND_READ_DATA_13_SELECT_INPUT 0x0820
+#define IOMUXC_WEIMV2_IPP_IND_READ_DATA_14_SELECT_INPUT 0x0824
+#define IOMUXC_WEIMV2_IPP_IND_READ_DATA_15_SELECT_INPUT 0x0828
+
+#endif /* _ARM_IMX_IMX50_IOMUXREG_H */
+
