Module Name: src
Committed By: msaitoh
Date: Fri Aug 29 12:14:30 UTC 2014
Modified Files:
src/sys/dev/pci: if_wm.c if_wmreg.h
Log Message:
No binary change:
- Move some NVM related macros fromk if_wm.c to if_wmreg.h.
- Rename some macros for consistency.
To generate a diff of this commit:
cvs rdiff -u -r1.292 -r1.293 src/sys/dev/pci/if_wm.c
cvs rdiff -u -r1.60 -r1.61 src/sys/dev/pci/if_wmreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/pci/if_wm.c
diff -u src/sys/dev/pci/if_wm.c:1.292 src/sys/dev/pci/if_wm.c:1.293
--- src/sys/dev/pci/if_wm.c:1.292 Thu Aug 28 16:22:59 2014
+++ src/sys/dev/pci/if_wm.c Fri Aug 29 12:14:29 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: if_wm.c,v 1.292 2014/08/28 16:22:59 msaitoh Exp $ */
+/* $NetBSD: if_wm.c,v 1.293 2014/08/29 12:14:29 msaitoh Exp $ */
/*
* Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
@@ -82,7 +82,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.292 2014/08/28 16:22:59 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.293 2014/08/29 12:14:29 msaitoh Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -1856,7 +1856,7 @@ wm_attach(device_t parent, device_t self
KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER);
cfg1 = (uint16_t) prop_number_integer_value(pn);
} else {
- if (wm_nvm_read(sc, EEPROM_OFF_CFG1, 1, &cfg1)) {
+ if (wm_nvm_read(sc, NVM_OFF_CFG1, 1, &cfg1)) {
aprint_error_dev(sc->sc_dev, "unable to read CFG1\n");
goto fail_5;
}
@@ -1867,7 +1867,7 @@ wm_attach(device_t parent, device_t self
KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER);
cfg2 = (uint16_t) prop_number_integer_value(pn);
} else {
- if (wm_nvm_read(sc, EEPROM_OFF_CFG2, 1, &cfg2)) {
+ if (wm_nvm_read(sc, NVM_OFF_CFG2, 1, &cfg2)) {
aprint_error_dev(sc->sc_dev, "unable to read CFG2\n");
goto fail_5;
}
@@ -1880,10 +1880,10 @@ wm_attach(device_t parent, device_t self
case WM_T_82543:
/* dummy? */
eeprom_data = 0;
- apme_mask = EEPROM_CFG3_APME;
+ apme_mask = NVM_CFG3_APME;
break;
case WM_T_82544:
- apme_mask = EEPROM_CFG2_82544_APM_EN;
+ apme_mask = NVM_CFG2_82544_APM_EN;
eeprom_data = cfg2;
break;
case WM_T_82546:
@@ -1895,9 +1895,9 @@ wm_attach(device_t parent, device_t self
case WM_T_82583:
case WM_T_80003:
default:
- apme_mask = EEPROM_CFG3_APME;
- wm_nvm_read(sc, (sc->sc_funcid == 1) ? EEPROM_OFF_CFG3_PORTB
- : EEPROM_OFF_CFG3_PORTA, 1, &eeprom_data);
+ apme_mask = NVM_CFG3_APME;
+ wm_nvm_read(sc, (sc->sc_funcid == 1) ? NVM_OFF_CFG3_PORTB
+ : NVM_OFF_CFG3_PORTA, 1, &eeprom_data);
break;
case WM_T_82575:
case WM_T_82576:
@@ -1936,7 +1936,7 @@ wm_attach(device_t parent, device_t self
KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER);
swdpin = (uint16_t) prop_number_integer_value(pn);
} else {
- if (wm_nvm_read(sc, EEPROM_OFF_SWDPIN, 1, &swdpin)) {
+ if (wm_nvm_read(sc, NVM_OFF_SWDPIN, 1, &swdpin)) {
aprint_error_dev(sc->sc_dev,
"unable to read SWDPIN\n");
goto fail_5;
@@ -1944,36 +1944,36 @@ wm_attach(device_t parent, device_t self
}
}
- if (cfg1 & EEPROM_CFG1_ILOS)
+ if (cfg1 & NVM_CFG1_ILOS)
sc->sc_ctrl |= CTRL_ILOS;
if (sc->sc_type >= WM_T_82544) {
sc->sc_ctrl |=
- ((swdpin >> EEPROM_SWDPIN_SWDPIO_SHIFT) & 0xf) <<
+ ((swdpin >> NVM_SWDPIN_SWDPIO_SHIFT) & 0xf) <<
CTRL_SWDPIO_SHIFT;
sc->sc_ctrl |=
- ((swdpin >> EEPROM_SWDPIN_SWDPIN_SHIFT) & 0xf) <<
+ ((swdpin >> NVM_SWDPIN_SWDPIN_SHIFT) & 0xf) <<
CTRL_SWDPINS_SHIFT;
} else {
sc->sc_ctrl |=
- ((cfg1 >> EEPROM_CFG1_SWDPIO_SHIFT) & 0xf) <<
+ ((cfg1 >> NVM_CFG1_SWDPIO_SHIFT) & 0xf) <<
CTRL_SWDPIO_SHIFT;
}
#if 0
if (sc->sc_type >= WM_T_82544) {
- if (cfg1 & EEPROM_CFG1_IPS0)
+ if (cfg1 & NVM_CFG1_IPS0)
sc->sc_ctrl_ext |= CTRL_EXT_IPS;
- if (cfg1 & EEPROM_CFG1_IPS1)
+ if (cfg1 & NVM_CFG1_IPS1)
sc->sc_ctrl_ext |= CTRL_EXT_IPS1;
sc->sc_ctrl_ext |=
- ((swdpin >> (EEPROM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) <<
+ ((swdpin >> (NVM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) <<
CTRL_EXT_SWDPIO_SHIFT;
sc->sc_ctrl_ext |=
- ((swdpin >> (EEPROM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) <<
+ ((swdpin >> (NVM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) <<
CTRL_EXT_SWDPINS_SHIFT;
} else {
sc->sc_ctrl_ext |=
- ((cfg2 >> EEPROM_CFG2_SWDPIO_SHIFT) & 0xf) <<
+ ((cfg2 >> NVM_CFG2_SWDPIO_SHIFT) & 0xf) <<
CTRL_EXT_SWDPIO_SHIFT;
}
#endif
@@ -1999,9 +1999,9 @@ wm_attach(device_t parent, device_t self
uint16_t val;
/* Save the NVM K1 bit setting */
- wm_nvm_read(sc, EEPROM_OFF_K1_CONFIG, 1, &val);
+ wm_nvm_read(sc, NVM_OFF_K1_CONFIG, 1, &val);
- if ((val & EEPROM_K1_CONFIG_ENABLE) != 0)
+ if ((val & NVM_K1_CONFIG_ENABLE) != 0)
sc->sc_nvm_k1_enabled = 1;
else
sc->sc_nvm_k1_enabled = 0;
@@ -2134,8 +2134,8 @@ wm_attach(device_t parent, device_t self
switch (sc->sc_type) {
case WM_T_82573:
/* XXX limited to 9234 if ASPM is disabled */
- wm_nvm_read(sc, EEPROM_INIT_3GIO_3, 1, &io3);
- if ((io3 & EEPROM_3GIO_3_ASPM_MASK) != 0)
+ wm_nvm_read(sc, NVM_OFF_INIT_3GIO_3, 1, &io3);
+ if ((io3 & NVM_3GIO_3_ASPM_MASK) != 0)
sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
break;
case WM_T_82571:
@@ -2674,10 +2674,10 @@ static int
wm_check_alt_mac_addr(struct wm_softc *sc)
{
uint16_t myea[ETHER_ADDR_LEN / 2];
- uint16_t offset = EEPROM_OFF_MACADDR;
+ uint16_t offset = NVM_OFF_MACADDR;
/* Try to read alternative MAC address pointer */
- if (wm_nvm_read(sc, EEPROM_ALT_MAC_ADDR_PTR, 1, &offset) != 0)
+ if (wm_nvm_read(sc, NVM_OFF_ALT_MAC_ADDR_PTR, 1, &offset) != 0)
return -1;
/* Check pointer */
@@ -2703,7 +2703,7 @@ static int
wm_read_mac_addr(struct wm_softc *sc, uint8_t *enaddr)
{
uint16_t myea[ETHER_ADDR_LEN / 2];
- uint16_t offset = EEPROM_OFF_MACADDR;
+ uint16_t offset = NVM_OFF_MACADDR;
int do_invert = 0;
switch (sc->sc_type) {
@@ -2713,16 +2713,16 @@ wm_read_mac_addr(struct wm_softc *sc, ui
case WM_T_I354:
switch (sc->sc_funcid) {
case 0:
- /* default value (== EEPROM_OFF_MACADDR) */
+ /* default value (== NVM_OFF_MACADDR) */
break;
case 1:
- offset = EEPROM_OFF_LAN1;
+ offset = NVM_OFF_LAN1;
break;
case 2:
- offset = EEPROM_OFF_LAN2;
+ offset = NVM_OFF_LAN2;
break;
case 3:
- offset = EEPROM_OFF_LAN3;
+ offset = NVM_OFF_LAN3;
break;
default:
goto bad;
@@ -2738,7 +2738,7 @@ wm_read_mac_addr(struct wm_softc *sc, ui
case WM_T_I211:
if (wm_check_alt_mac_addr(sc) != 0) {
/* reset the offset to LAN0 */
- offset = EEPROM_OFF_MACADDR;
+ offset = NVM_OFF_MACADDR;
if ((sc->sc_funcid & 0x01) == 1)
do_invert = 1;
goto do_read;
@@ -2746,18 +2746,18 @@ wm_read_mac_addr(struct wm_softc *sc, ui
switch (sc->sc_funcid) {
case 0:
/*
- * The offset is the value in EEPROM_ALT_MAC_ADDR_PTR
+ * The offset is the value in NVM_OFF_ALT_MAC_ADDR_PTR
* itself.
*/
break;
case 1:
- offset += EEPROM_OFF_MACADDR_LAN1;
+ offset += NVM_OFF_MACADDR_LAN1;
break;
case 2:
- offset += EEPROM_OFF_MACADDR_LAN2;
+ offset += NVM_OFF_MACADDR_LAN2;
break;
case 3:
- offset += EEPROM_OFF_MACADDR_LAN3;
+ offset += NVM_OFF_MACADDR_LAN3;
break;
default:
goto bad;
@@ -8260,13 +8260,6 @@ wm_nvm_is_onboard_eeprom(struct wm_softc
return 1;
}
-#define NVM_CHECKSUM 0xBABA
-#define EEPROM_SIZE 0x0040
-#define NVM_COMPAT 0x0003
-#define NVM_COMPAT_VALID_CHECKSUM 0x0001
-#define NVM_FUTURE_INIT_WORD1 0x0019
-#define NVM_FUTURE_INIT_WORD1_VALID_CHECKSUM 0x0040
-
/*
* wm_nvm_validate_checksum
*
@@ -8290,10 +8283,10 @@ wm_nvm_validate_checksum(struct wm_softc
#ifdef WM_DEBUG
if (sc->sc_type == WM_T_PCH_LPT) {
- csum_wordaddr = NVM_COMPAT;
+ csum_wordaddr = NVM_OFF_COMPAT;
valid_checksum = NVM_COMPAT_VALID_CHECKSUM;
} else {
- csum_wordaddr = NVM_FUTURE_INIT_WORD1;
+ csum_wordaddr = NVM_OFF_FUTURE_INIT_WORD1;
valid_checksum = NVM_FUTURE_INIT_WORD1_VALID_CHECKSUM;
}
@@ -8312,7 +8305,7 @@ wm_nvm_validate_checksum(struct wm_softc
if ((wm_debug & WM_DEBUG_NVM) != 0) {
printf("%s: NVM dump:\n", device_xname(sc->sc_dev));
- for (i = 0; i < EEPROM_SIZE; i++) {
+ for (i = 0; i < NVM_SIZE; i++) {
if (wm_nvm_read(sc, i, 1, &eeprom_data))
printf("XX ");
else
@@ -8324,7 +8317,7 @@ wm_nvm_validate_checksum(struct wm_softc
#endif /* WM_DEBUG */
- for (i = 0; i < EEPROM_SIZE; i++) {
+ for (i = 0; i < NVM_SIZE; i++) {
if (wm_nvm_read(sc, i, 1, &eeprom_data))
return 1;
checksum += eeprom_data;
@@ -8609,9 +8602,9 @@ wm_check_mng_mode_82574(struct wm_softc
{
uint16_t data;
- wm_nvm_read(sc, EEPROM_OFF_CFG2, 1, &data);
+ wm_nvm_read(sc, NVM_OFF_CFG2, 1, &data);
- if ((data & EEPROM_CFG2_MNGM_MASK) != 0)
+ if ((data & NVM_CFG2_MNGM_MASK) != 0)
return 1;
return 0;
@@ -8656,12 +8649,12 @@ wm_enable_mng_pass_thru(struct wm_softc
uint16_t data;
factps = CSR_READ(sc, WMREG_FACTPS);
- wm_nvm_read(sc, EEPROM_OFF_CFG2, 1, &data);
+ wm_nvm_read(sc, NVM_OFF_CFG2, 1, &data);
DPRINTF(WM_DEBUG_MANAGE, ("%s: FACTPS = %08x, CFG2=%04x\n",
device_xname(sc->sc_dev), factps, data));
if (((factps & FACTPS_MNGCG) == 0)
- && ((data & EEPROM_CFG2_MNGM_MASK)
- == (EEPROM_CFG2_MNGM_PT << EEPROM_CFG2_MNGM_SHIFT)))
+ && ((data & NVM_CFG2_MNGM_MASK)
+ == (NVM_CFG2_MNGM_PT << NVM_CFG2_MNGM_SHIFT)))
return 1;
} else if (((manc & MANC_SMBUS_EN) != 0)
&& ((manc & MANC_ASF_EN) == 0))
Index: src/sys/dev/pci/if_wmreg.h
diff -u src/sys/dev/pci/if_wmreg.h:1.60 src/sys/dev/pci/if_wmreg.h:1.61
--- src/sys/dev/pci/if_wmreg.h:1.60 Thu Jul 31 03:50:09 2014
+++ src/sys/dev/pci/if_wmreg.h Fri Aug 29 12:14:29 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: if_wmreg.h,v 1.60 2014/07/31 03:50:09 msaitoh Exp $ */
+/* $NetBSD: if_wmreg.h,v 1.61 2014/08/29 12:14:29 msaitoh Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@@ -898,73 +898,82 @@ struct livengood_tcpip_ctxdesc {
#define SPI_SR_BP1 0x08
#define SPI_SR_WPEN 0x80
-#define EEPROM_OFF_MACADDR 0x00 /* MAC address offset */
-#define EEPROM_OFF_CFG1 0x0a /* config word 1 */
-#define EEPROM_OFF_CFG2 0x0f /* config word 2 */
-#define EEPROM_OFF_CFG3_PORTB 0x14 /* config word 3 */
-#define EEPROM_INIT_3GIO_3 0x1a /* PCIe Initial Configuration Word 3 */
-#define EEPROM_OFF_K1_CONFIG 0x1b /* NVM K1 Config */
-#define EEPROM_OFF_SWDPIN 0x20 /* SWD Pins (Cordova) */
-#define EEPROM_OFF_CFG3_PORTA 0x24 /* config word 3 */
-#define EEPROM_ALT_MAC_ADDR_PTR 0x37 /* to the alternative MAC addresses */
-
-#define EEPROM_CFG1_LVDID (1U << 0)
-#define EEPROM_CFG1_LSSID (1U << 1)
-#define EEPROM_CFG1_PME_CLOCK (1U << 2)
-#define EEPROM_CFG1_PM (1U << 3)
-#define EEPROM_CFG1_ILOS (1U << 4)
-#define EEPROM_CFG1_SWDPIO_SHIFT 5
-#define EEPROM_CFG1_SWDPIO_MASK (0xf << EEPROM_CFG1_SWDPIO_SHIFT)
-#define EEPROM_CFG1_IPS1 (1U << 8)
-#define EEPROM_CFG1_LRST (1U << 9)
-#define EEPROM_CFG1_FD (1U << 10)
-#define EEPROM_CFG1_FRCSPD (1U << 11)
-#define EEPROM_CFG1_IPS0 (1U << 12)
-#define EEPROM_CFG1_64_32_BAR (1U << 13)
-
-#define EEPROM_CFG2_CSR_RD_SPLIT (1U << 1)
-#define EEPROM_CFG2_82544_APM_EN (1U << 2)
-#define EEPROM_CFG2_64_BIT (1U << 3)
-#define EEPROM_CFG2_MAX_READ (1U << 4)
-#define EEPROM_CFG2_DMCR_MAP (1U << 5)
-#define EEPROM_CFG2_133_CAP (1U << 6)
-#define EEPROM_CFG2_MSI_DIS (1U << 7)
-#define EEPROM_CFG2_FLASH_DIS (1U << 8)
-#define EEPROM_CFG2_FLASH_SIZE(x) (((x) & 3) >> 9)
-#define EEPROM_CFG2_APM_EN (1U << 10)
-#define EEPROM_CFG2_ANE (1U << 11)
-#define EEPROM_CFG2_PAUSE(x) (((x) & 3) >> 12)
-#define EEPROM_CFG2_ASDE (1U << 14)
-#define EEPROM_CFG2_APM_PME (1U << 15)
-#define EEPROM_CFG2_SWDPIO_SHIFT 4
-#define EEPROM_CFG2_SWDPIO_MASK (0xf << EEPROM_CFG2_SWDPIO_SHIFT)
-#define EEPROM_CFG2_MNGM_SHIFT 13 /* Manageability Operation mode */
-#define EEPROM_CFG2_MNGM_MASK (3U << EEPROM_CFG2_MNGM_SHIFT)
-#define EEPROM_CFG2_MNGM_DIS 0
-#define EEPROM_CFG2_MNGM_NCSI 1
-#define EEPROM_CFG2_MNGM_PT 2
-
-#define EEPROM_K1_CONFIG_ENABLE 0x01
-
-#define EEPROM_SWDPIN_MASK 0xdf
-#define EEPROM_SWDPIN_SWDPIN_SHIFT 0
-#define EEPROM_SWDPIN_SWDPIO_SHIFT 8
-
-#define EEPROM_3GIO_3_ASPM_MASK (0x3 << 2) /* Active State PM Support */
-
-#define EEPROM_CFG3_APME (1U << 10)
-
-#define EEPROM_OFF_MACADDR_LAN1 3 /* macaddr offset from PTR (port 1) */
-#define EEPROM_OFF_MACADDR_LAN2 6 /* macaddr offset from PTR (port 2) */
-#define EEPROM_OFF_MACADDR_LAN3 9 /* macaddr offset from PTR (port 3) */
+#define NVM_CHECKSUM 0xBABA
+#define NVM_SIZE 0x0040
+
+#define NVM_OFF_MACADDR 0x0000 /* MAC address offset */
+#define NVM_OFF_COMPAT 0x0003
+#define NVM_OFF_CFG1 0x000a /* config word 1 */
+#define NVM_OFF_CFG2 0x000f /* config word 2 */
+#define NVM_OFF_CFG3_PORTB 0x0014 /* config word 3 */
+#define NVM_OFF_FUTURE_INIT_WORD1 0x0019
+#define NVM_OFF_INIT_3GIO_3 0x001a /* PCIe Initial Configuration Word 3 */
+#define NVM_OFF_K1_CONFIG 0x001b /* NVM K1 Config */
+#define NVM_OFF_SWDPIN 0x0020 /* SWD Pins (Cordova) */
+#define NVM_OFF_CFG3_PORTA 0x0024 /* config word 3 */
+#define NVM_OFF_ALT_MAC_ADDR_PTR 0x0037 /* to the alternative MAC addresses */
+
+#define NVM_COMPAT_VALID_CHECKSUM 0x0001
+
+#define NVM_CFG1_LVDID (1U << 0)
+#define NVM_CFG1_LSSID (1U << 1)
+#define NVM_CFG1_PME_CLOCK (1U << 2)
+#define NVM_CFG1_PM (1U << 3)
+#define NVM_CFG1_ILOS (1U << 4)
+#define NVM_CFG1_SWDPIO_SHIFT 5
+#define NVM_CFG1_SWDPIO_MASK (0xf << NVM_CFG1_SWDPIO_SHIFT)
+#define NVM_CFG1_IPS1 (1U << 8)
+#define NVM_CFG1_LRST (1U << 9)
+#define NVM_CFG1_FD (1U << 10)
+#define NVM_CFG1_FRCSPD (1U << 11)
+#define NVM_CFG1_IPS0 (1U << 12)
+#define NVM_CFG1_64_32_BAR (1U << 13)
+
+#define NVM_CFG2_CSR_RD_SPLIT (1U << 1)
+#define NVM_CFG2_82544_APM_EN (1U << 2)
+#define NVM_CFG2_64_BIT (1U << 3)
+#define NVM_CFG2_MAX_READ (1U << 4)
+#define NVM_CFG2_DMCR_MAP (1U << 5)
+#define NVM_CFG2_133_CAP (1U << 6)
+#define NVM_CFG2_MSI_DIS (1U << 7)
+#define NVM_CFG2_FLASH_DIS (1U << 8)
+#define NVM_CFG2_FLASH_SIZE(x) (((x) & 3) >> 9)
+#define NVM_CFG2_APM_EN (1U << 10)
+#define NVM_CFG2_ANE (1U << 11)
+#define NVM_CFG2_PAUSE(x) (((x) & 3) >> 12)
+#define NVM_CFG2_ASDE (1U << 14)
+#define NVM_CFG2_APM_PME (1U << 15)
+#define NVM_CFG2_SWDPIO_SHIFT 4
+#define NVM_CFG2_SWDPIO_MASK (0xf << NVM_CFG2_SWDPIO_SHIFT)
+#define NVM_CFG2_MNGM_SHIFT 13 /* Manageability Operation mode */
+#define NVM_CFG2_MNGM_MASK (3U << NVM_CFG2_MNGM_SHIFT)
+#define NVM_CFG2_MNGM_DIS 0
+#define NVM_CFG2_MNGM_NCSI 1
+#define NVM_CFG2_MNGM_PT 2
+
+#define NVM_FUTURE_INIT_WORD1_VALID_CHECKSUM 0x0040
+
+#define NVM_K1_CONFIG_ENABLE 0x01
+
+#define NVM_SWDPIN_MASK 0xdf
+#define NVM_SWDPIN_SWDPIN_SHIFT 0
+#define NVM_SWDPIN_SWDPIO_SHIFT 8
+
+#define NVM_3GIO_3_ASPM_MASK (0x3 << 2) /* Active State PM Support */
+
+#define NVM_CFG3_APME (1U << 10)
+
+#define NVM_OFF_MACADDR_LAN1 3 /* macaddr offset from PTR (port 1) */
+#define NVM_OFF_MACADDR_LAN2 6 /* macaddr offset from PTR (port 2) */
+#define NVM_OFF_MACADDR_LAN3 9 /* macaddr offset from PTR (port 3) */
/*
* EEPROM Partitioning. See Table 6-1, "EEPROM Top Level Partitioning"
* in 82580's datasheet.
*/
-#define EEPROM_OFF_LAN1 0x0080 /* Offset for LAN1 (82580)*/
-#define EEPROM_OFF_LAN2 0x00c0 /* Offset for LAN2 (82580)*/
-#define EEPROM_OFF_LAN3 0x0100 /* Offset for LAN3 (82580)*/
+#define NVM_OFF_LAN1 0x0080 /* Offset for LAN1 (82580)*/
+#define NVM_OFF_LAN2 0x00c0 /* Offset for LAN2 (82580)*/
+#define NVM_OFF_LAN3 0x0100 /* Offset for LAN3 (82580)*/
/* ich8 flash control */
#define ICH_FLASH_COMMAND_TIMEOUT 5000 /* 5000 uSecs - adjusted */
