Module Name: src
Committed By: jmcneill
Date: Thu Sep 4 02:35:26 UTC 2014
Modified Files:
src/sys/arch/arm/allwinner: awin_reg.h
Log Message:
add some PLL2 and APB0_GATING bits
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/arm/allwinner/awin_reg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/allwinner/awin_reg.h
diff -u src/sys/arch/arm/allwinner/awin_reg.h:1.16 src/sys/arch/arm/allwinner/awin_reg.h:1.17
--- src/sys/arch/arm/allwinner/awin_reg.h:1.16 Wed Sep 3 21:42:46 2014
+++ src/sys/arch/arm/allwinner/awin_reg.h Thu Sep 4 02:35:26 2014
@@ -730,6 +730,12 @@
#define AWIN_PLL1_SIG_DELT_PAT_IN __BIT(3)
#define AWIN_PLL1_SIG_DELT_PAT_EN __BIT(2)
+#define AWIN_PLL2_CFG_PREVDIV __BITS(4,0)
+#define AWIN_PLL2_CFG_FACTOR_N __BITS(14,8)
+#define AWIN_PLL2_CFG_PLLBIAS __BITS(20,16)
+#define AWIN_PLL2_CFG_VCOBIAS __BITS(25,21)
+#define AWIN_PLL2_CFG_POSTDIV __BITS(29,26)
+
#define AWIN_PLL5_CFG_DDR_CLK_EN __BIT(29)
#define AWIN_PLL5_CFG_LDO_EN __BIT(7)
#define AWIN_PLL5_CFG_FACTOR_M1 __BITS(3,2)
@@ -817,6 +823,8 @@
#define AWIN_APB_GATING1_TWI1 __BIT(1)
#define AWIN_APB_GATING1_TWI0 __BIT(0)
+#define AWIN_APB0_GATING_ADDA __BIT(0)
+
#define AWIN_CLK_ENABLE __BIT(31)
#define AWIN_CLK_SRC_SEL __BITS(25,24)
#define AWIN_CLK_SRC_SEL_OSC24M 0
