Module Name: src
Committed By: msaitoh
Date: Tue Sep 9 15:11:33 UTC 2014
Modified Files:
src/sys/arch/x86/include: cacheinfo.h
Log Message:
Add new cache descriptor (0xc3) from the latest Intel SDM.
To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/x86/include/cacheinfo.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/cacheinfo.h
diff -u src/sys/arch/x86/include/cacheinfo.h:1.18 src/sys/arch/x86/include/cacheinfo.h:1.19
--- src/sys/arch/x86/include/cacheinfo.h:1.18 Thu Jul 3 17:24:33 2014
+++ src/sys/arch/x86/include/cacheinfo.h Tue Sep 9 15:11:33 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: cacheinfo.h,v 1.18 2014/07/03 17:24:33 msaitoh Exp $ */
+/* $NetBSD: cacheinfo.h,v 1.19 2014/09/09 15:11:33 msaitoh Exp $ */
#ifndef _X86_CACHEINFO_H_
#define _X86_CACHEINFO_H_
@@ -247,6 +247,7 @@ __CI_TBL(CAI_DTLB, 0xba, 4, 64,
__CI_TBL(CAI_DTLB2, 0xc0, 4, 8, 4 * 1024, "4K/4M: 8 entries"), \
__CI_TBL(CAI_L2_STLB2, 0xc1, 8,1024, 4 * 1024, "4K/2M: 1024 entries"), \
__CI_TBL(CAI_DTLB2, 0xc2, 4, 16, 4 * 1024, "4K/2M: 16 entries"), \
+__CI_TBL(CAI_L2_STLB, 0xc3, 6,1536, 4 * 1024, NULL), \
__CI_TBL(CAI_L2_STLB, 0xca, 4,512, 4 * 1024, NULL), \
__CI_TBL(CAI_ICACHE, 0x06, 4, 8 * 1024, 32, NULL), \
__CI_TBL(CAI_ICACHE, 0x08, 4, 16 * 1024, 32, NULL), \
