Module Name: src
Committed By: reinoud
Date: Thu Oct 2 11:39:45 UTC 2014
Modified Files:
src/sys/arch/arm/samsung: exynos5_reg.h
Log Message:
Add KPLL
To generate a diff of this commit:
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/arm/samsung/exynos5_reg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/samsung/exynos5_reg.h
diff -u src/sys/arch/arm/samsung/exynos5_reg.h:1.17 src/sys/arch/arm/samsung/exynos5_reg.h:1.18
--- src/sys/arch/arm/samsung/exynos5_reg.h:1.17 Wed Sep 24 20:35:43 2014
+++ src/sys/arch/arm/samsung/exynos5_reg.h Thu Oct 2 11:39:45 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: exynos5_reg.h,v 1.17 2014/09/24 20:35:43 reinoud Exp $ */
+/* $NetBSD: exynos5_reg.h,v 1.18 2014/10/02 11:39:45 reinoud Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -60,11 +60,12 @@
#define EXYNOS5_CMU_MPLL 0x00014000 /* MEM cntr. clock */
#define EXYNOS5_CMU_TOP_PART_OFFSET 0x00020000
#define EXYNOS5_CMU_CPLL 0x00020020 /* Video hardware codec clock */
-#define EXYNOS5_CMU_EPLL 0x00020030 /* Audio and ext. interf. clock */
+#define EXYNOS5_CMU_DPLL 0x00020030 /* Audio and ext. interf. clock */
#define EXYNOS5_CMU_VPLL 0x00020040 /* Dither PLL (EMI reduction) clock */
#define EXYNOS5_CMU_GPLL 0x00020050 /* Graphic 3D proc. clock */
#define EXYNOS5_CMU_MEM_PART_OFFSET 0x00030000
#define EXYNOS5_CMU_BPLL 0x00030010
+#define EXYNOS5_CMU_KPLL 0x00038010
#define EXYNOS5_ALIVE_OFFSET 0x00040000
#define EXYNOS5_PMU_OFFSET 0x00040000 /* alias */
#define EXYNOS5_SYSREG_OFFSET 0x00050000
