Module Name: src Committed By: martin Date: Sat Oct 4 15:25:15 UTC 2014
Modified Files: src/sys/arch/arm/allwinner: awin_gige.c Log Message: Initialize all bits of the GMAC clock register, add comments. To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/allwinner/awin_gige.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/arch/arm/allwinner/awin_gige.c diff -u src/sys/arch/arm/allwinner/awin_gige.c:1.7 src/sys/arch/arm/allwinner/awin_gige.c:1.8 --- src/sys/arch/arm/allwinner/awin_gige.c:1.7 Thu Sep 11 06:56:05 2014 +++ src/sys/arch/arm/allwinner/awin_gige.c Sat Oct 4 15:25:15 2014 @@ -31,7 +31,7 @@ #include <sys/cdefs.h> -__KERNEL_RCSID(1, "$NetBSD: awin_gige.c,v 1.7 2014/09/11 06:56:05 martin Exp $"); +__KERNEL_RCSID(1, "$NetBSD: awin_gige.c,v 1.8 2014/10/04 15:25:15 martin Exp $"); #include <sys/param.h> #include <sys/bus.h> @@ -126,10 +126,10 @@ awin_gige_attach(device_t parent, device /* * We use RGMII phy mode, set up clock accordingly */ + bus_space_write_4(aio->aio_core_bst, aio->aio_ccm_bsh, + AWIN_GMAC_CLK_REG, 4); /* GPIT = RMII */ awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh, - AWIN_GMAC_CLK_REG, 4, 3); - awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh, - AWIN_GMAC_CLK_REG, 2, 0); + AWIN_GMAC_CLK_REG, 2, 0); /* GTCS = internal transmit clock */ dwc_gmac_attach(&sc->sc_core, 2); }