Module Name: src
Committed By: matt
Date: Tue Oct 14 08:03:13 UTC 2014
Modified Files:
src/sys/arch/arm/arm32: arm32_tlb.c
Log Message:
Use tlb is variants for MULTIPROCESSOR
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/arm32/arm32_tlb.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm32/arm32_tlb.c
diff -u src/sys/arch/arm/arm32/arm32_tlb.c:1.2 src/sys/arch/arm/arm32/arm32_tlb.c:1.3
--- src/sys/arch/arm/arm32/arm32_tlb.c:1.2 Fri Apr 11 02:39:03 2014
+++ src/sys/arch/arm/arm32/arm32_tlb.c Tue Oct 14 08:03:13 2014
@@ -27,7 +27,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: arm32_tlb.c,v 1.2 2014/04/11 02:39:03 matt Exp $");
+__KERNEL_RCSID(1, "$NetBSD: arm32_tlb.c,v 1.3 2014/10/14 08:03:13 matt Exp $");
#include <sys/param.h>
#include <sys/types.h>
@@ -60,7 +60,11 @@ tlb_invalidate_all(void)
{
const bool vivt_icache_p = arm_pcache.icache_type == CACHE_TYPE_VIVT;
arm_dsb();
+#ifdef MULTIPROCESSOR
+ armreg_tlbiallis_write(0);
+#else
armreg_tlbiall_write(0);
+#endif
arm_isb();
if (__predict_false(vivt_icache_p)) {
if (arm_has_tlbiasid_p) {
@@ -107,7 +111,11 @@ tlb_invalidate_addr(vaddr_t va, tlb_asid
arm_dsb();
va = trunc_page(va) | asid;
for (vaddr_t eva = va + PAGE_SIZE; va < eva; va += L2_S_SIZE) {
+#ifdef MULTIPROCESSOR
+ armreg_tlbimvais_write(va);
+#else
armreg_tlbimva_write(va);
+#endif
//armreg_tlbiall_write(asid);
}
arm_isb();
