Module Name: src
Committed By: skrll
Date: Wed Oct 29 16:22:32 UTC 2014
Modified Files:
src/sys/arch/arm/arm: cpufunc_asm_arm11.S cpufunc_asm_armv7.S
cpufunc_asm_pj4b.S
Log Message:
Don't flush random ASIDs. Instead always assume KERNEL_PID, i.e. 0.
All other TLB flushes are done via
pmap_tlb_invalidate_addr -> tlb_invalidate_addr
OK matt@
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/arm/arm/cpufunc_asm_arm11.S
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/arm/arm/cpufunc_asm_armv7.S
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/arm/cpufunc_asm_pj4b.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/cpufunc_asm_arm11.S
diff -u src/sys/arch/arm/arm/cpufunc_asm_arm11.S:1.16 src/sys/arch/arm/arm/cpufunc_asm_arm11.S:1.17
--- src/sys/arch/arm/arm/cpufunc_asm_arm11.S:1.16 Wed Oct 29 16:14:45 2014
+++ src/sys/arch/arm/arm/cpufunc_asm_arm11.S Wed Oct 29 16:22:31 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_arm11.S,v 1.16 2014/10/29 16:14:45 skrll Exp $ */
+/* $NetBSD: cpufunc_asm_arm11.S,v 1.17 2014/10/29 16:22:31 skrll Exp $ */
/*
* Copyright (c) 2002, 2005 ARM Limited
@@ -97,7 +97,8 @@ END(arm11_tlb_flushI)
ENTRY(arm11_tlb_flushI_SE)
#ifdef ARM_MMU_EXTENDED
- orr r0, r0, r1 /* insert ASID into MVA */
+ bic r0, r0, #0xff
+ bic r0, r0, #0xf00 /* Always KERNEL_PID, i.e. 0 */
#endif
mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
#if PAGE_SIZE == 2 * L2_S_SIZE
@@ -119,7 +120,8 @@ END(arm11_tlb_flushD)
ENTRY(arm11_tlb_flushD_SE)
#ifdef ARM_MMU_EXTENDED
- orr r0, r0, r1 /* insert ASID into MVA */
+ bic r0, r0, #0xff
+ bic r0, r0, #0xf00 /* Always KERNEL_PID, i.e. 0 */
#endif
mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
#if PAGE_SIZE == 2 * L2_S_SIZE
@@ -140,7 +142,8 @@ END(arm11_tlb_flushID)
ENTRY(arm11_tlb_flushID_SE)
#ifdef ARM_MMU_EXTENDED
- orr r0, r0, r1 /* insert ASID into MVA */
+ bic r0, r0, #0xff
+ bic r0, r0, #0xf00 /* Always KERNEL_PID, i.e. 0 */
#endif
mcr p15, 0, r0, c8, c7, 1 /* flush I+D tlb single entry */
#if PAGE_SIZE == 2 * L2_S_SIZE
Index: src/sys/arch/arm/arm/cpufunc_asm_armv7.S
diff -u src/sys/arch/arm/arm/cpufunc_asm_armv7.S:1.18 src/sys/arch/arm/arm/cpufunc_asm_armv7.S:1.19
--- src/sys/arch/arm/arm/cpufunc_asm_armv7.S:1.18 Thu Jul 31 06:26:06 2014
+++ src/sys/arch/arm/arm/cpufunc_asm_armv7.S Wed Oct 29 16:22:31 2014
@@ -78,10 +78,7 @@ END(armv7_tlb_flushID_ASID)
STRONG_ALIAS(armv7_tlb_flushD_SE, armv7_tlb_flushID_SE)
STRONG_ALIAS(armv7_tlb_flushI_SE, armv7_tlb_flushID_SE)
ENTRY(armv7_tlb_flushID_SE)
- bfc r0, #0, #12 @ clear ASID
-#ifdef ARM_MMU_EXTENDED
- bfi r0, r1, #0, #8 @ insert ASID into MVA
-#endif
+ bfc r0, #0, #12 @ Always KERNEL_PID, i.e. 0
#ifdef MULTIPROCESSOR
mcr p15, 0, r0, c8, c3, 1 @ flush I+D tlb single entry
#if PAGE_SIZE == 2*L2_S_SIZE
Index: src/sys/arch/arm/arm/cpufunc_asm_pj4b.S
diff -u src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.4 src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.5
--- src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.4 Sun Mar 30 01:15:03 2014
+++ src/sys/arch/arm/arm/cpufunc_asm_pj4b.S Wed Oct 29 16:22:31 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_pj4b.S,v 1.4 2014/03/30 01:15:03 matt Exp $ */
+/* $NetBSD: cpufunc_asm_pj4b.S,v 1.5 2014/10/29 16:22:31 skrll Exp $ */
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
@@ -78,6 +78,7 @@ ENTRY(pj4b_tlb_flushID)
END(pj4b_tlb_flushID)
ENTRY(pj4b_tlb_flushID_SE)
+ bfc r0, #0, #12 @ always KERNEL_PID (i.e. 0)
mcr p15, 0, r0, c8, c7, 1 @flush I+D tlb single entry
#if PAGE_SIZE == 2 * L2_S_SIZE
add r0, r0, L2_S_SIZE
