Module Name: src
Committed By: skrll
Date: Wed Oct 29 19:27:37 UTC 2014
Modified Files:
src/sys/arch/arm/cortex: gic.c
Log Message:
Only target boot cpu for SPIs atm. Fix a couple of bugs in the now
disabled code.
To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/arm/cortex/gic.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gic.c
diff -u src/sys/arch/arm/cortex/gic.c:1.11 src/sys/arch/arm/cortex/gic.c:1.12
--- src/sys/arch/arm/cortex/gic.c:1.11 Wed Oct 29 14:14:14 2014
+++ src/sys/arch/arm/cortex/gic.c Wed Oct 29 19:27:36 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: gic.c,v 1.11 2014/10/29 14:14:14 skrll Exp $ */
+/* $NetBSD: gic.c,v 1.12 2014/10/29 19:27:36 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -34,7 +34,7 @@
#define _INTR_PRIVATE
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.11 2014/10/29 14:14:14 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.12 2014/10/29 19:27:36 skrll Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -350,11 +350,13 @@ armgic_establish_irq(struct pic_softc *p
* to the primary cpu.
*/
targets &= ~(0xff << byte_shift);
+#if 0
#ifdef MULTIPROCESSOR
if (is->is_mpsafe) {
- targets |= sc->sc_mptargets;
+ targets |= sc->sc_mptargets << byte_shift;
} else
#endif
+#endif
targets |= 1 << byte_shift;
gicd_write(sc, targets_reg, targets);
@@ -443,7 +445,7 @@ armgic_cpu_init_targets(struct armgic_so
struct intrsource * const is = sc->sc_pic.pic_sources[irq];
const bus_size_t targets_reg = GICD_ITARGETSRn(irq / 4);
if (is != NULL && is->is_mpsafe) {
- const u_int byte_shift = 0xff << (8 * (irq & 3));
+ const u_int byte_shift = 8 * (irq & 3);
uint32_t targets = gicd_read(sc, targets_reg);
targets |= sc->sc_mptargets << byte_shift;
gicd_write(sc, targets_reg, targets);
