Module Name: src Committed By: hkenken Date: Fri Nov 7 11:54:18 UTC 2014
Modified Files: src/sys/arch/arm/imx: imx51_ipuv3.c imx51_ipuv3reg.h Log Message: - Use __SHIFTIN macro - fix CM_DISP_GEN_DI1_COUNTER_RELEASE To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/imx/imx51_ipuv3.c cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/imx/imx51_ipuv3reg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/arch/arm/imx/imx51_ipuv3.c diff -u src/sys/arch/arm/imx/imx51_ipuv3.c:1.2 src/sys/arch/arm/imx/imx51_ipuv3.c:1.3 --- src/sys/arch/arm/imx/imx51_ipuv3.c:1.2 Tue May 6 11:22:53 2014 +++ src/sys/arch/arm/imx/imx51_ipuv3.c Fri Nov 7 11:54:18 2014 @@ -1,4 +1,4 @@ -/* $NetBSD: imx51_ipuv3.c,v 1.2 2014/05/06 11:22:53 hkenken Exp $ */ +/* $NetBSD: imx51_ipuv3.c,v 1.3 2014/11/07 11:54:18 hkenken Exp $ */ /* * Copyright (c) 2011, 2012 Genetec Corporation. All rights reserved. @@ -27,7 +27,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: imx51_ipuv3.c,v 1.2 2014/05/06 11:22:53 hkenken Exp $"); +__KERNEL_RCSID(0, "$NetBSD: imx51_ipuv3.c,v 1.3 2014/11/07 11:54:18 hkenken Exp $"); #include <sys/param.h> #include <sys/systm.h> @@ -369,8 +369,8 @@ imx51_ipuv3_di_sync_conf(struct imx51_ip IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN0(no), reg_gen0); IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN1(no), reg_gen1); reg = IPUV3_READ(sc, di0, IPU_DI_STP_REP(no)); - reg &= ~DI_STP_REP_MASK(no); - reg |= repeat << DI_STP_REP_SHIFT(no); + reg &= ~DI_STP_REP(no); + reg |= __SHIFTIN(repeat, DI_STP_REP(no)); IPUV3_WRITE(sc, di0, IPU_DI_STP_REP(no), reg); #ifdef IPUV3_DEBUG @@ -413,7 +413,7 @@ imx51_ipuv3_di_init(struct imx51_ipuv3_s IPUV3_WRITE(sc, di0, IPU_DI_BS_CLKGEN0, div); IPUV3_WRITE(sc, di0, IPU_DI_BS_CLKGEN1, - (div / 16) << DI_BS_CLKGEN1_DOWN_SHIFT); + __SHIFTIN(div / 16, DI_BS_CLKGEN1_DOWN)); #ifdef IPUV3_DEBUG printf("%s: IPU_DI_BS_CLKGEN0 = 0x%08X\n", __func__, IPUV3_READ(sc, di0, IPU_DI_BS_CLKGEN0)); @@ -421,9 +421,9 @@ imx51_ipuv3_di_init(struct imx51_ipuv3_s IPUV3_READ(sc, di0, IPU_DI_BS_CLKGEN1)); #endif /* Display Time settings */ - reg = ((div / 16 - 1) << DI_DW_GEN_ACCESS_SIZE_SHIFT) | - ((div / 16 - 1) << DI_DW_GEN_COMPONNENT_SIZE_SHIFT) | - (3 << DI_DW_GEN_PIN_SHIFT(15)); + reg = __SHIFTIN(div / 16 - 1, DI_DW_GEN_ACCESS_SIZE) | + __SHIFTIN(div / 16 - 1, DI_DW_GEN_COMPONNENT_SIZE) | + __SHIFTIN(3, DI_DW_GEN_PIN(15)); IPUV3_WRITE(sc, di0, IPU_DI_DW_GEN(0), reg); #ifdef IPUV3_DEBUG printf("%s: div = %d\n", __func__, div); @@ -432,7 +432,7 @@ imx51_ipuv3_di_init(struct imx51_ipuv3_s #endif /* Up & Down Data Wave Set */ - reg = (div / 16 * 2) << DI_DW_SET_DOWN_SHIFT; + reg = __SHIFTIN(div / 16 * 2, DI_DW_SET_DOWN); IPUV3_WRITE(sc, di0, IPU_DI_DW_SET(0, 3), reg); #ifdef IPUV3_DEBUG printf("%s: IPU_DI_DW_SET(0, 3) 0x%08X = 0x%08X\n", __func__, @@ -486,13 +486,14 @@ imx51_ipuv3_di_init(struct imx51_ipuv3_s IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN1(9), 0); reg = IPUV3_READ(sc, di0, IPU_DI_STP_REP(6)); - reg &= ~DI_STP_REP_MASK(6); + reg &= ~DI_STP_REP(6); IPUV3_WRITE(sc, di0, IPU_DI_STP_REP(6), reg); IPUV3_WRITE(sc, di0, IPU_DI_STP_REP(7), 0); IPUV3_WRITE(sc, di0, IPU_DI_STP_REP(9), 0); IPUV3_WRITE(sc, di0, IPU_DI_GENERAL, 0); - reg = ((3 - 1) << DI_SYNC_AS_GEN_VSYNC_SEL_SHIFT) | 0x2; + reg = __SHIFTIN(3 - 1, DI_SYNC_AS_GEN_VSYNC_SEL) | + __SHIFTIN(0x2, DI_SYNC_AS_GEN_SYNC_START); IPUV3_WRITE(sc, di0, IPU_DI_SYNC_AS_GEN, reg); IPUV3_WRITE(sc, di0, IPU_DI_POL, DI_POL_DRDY_POLARITY_15); @@ -576,7 +577,7 @@ imx51_ipuv3_initialize(struct imx51_ipuv reg = IPUV3_READ(sc, cm, IPU_CM_DISP_GEN); reg |= CM_DISP_GEN_MCU_MAX_BURST_STOP | - CM_DISP_GEN_MCU_T(0x8); + __SHIFTIN(0x8, CM_DISP_GEN_MCU_T); IPUV3_WRITE(sc, cm, IPU_CM_DISP_GEN, reg); } Index: src/sys/arch/arm/imx/imx51_ipuv3reg.h diff -u src/sys/arch/arm/imx/imx51_ipuv3reg.h:1.1 src/sys/arch/arm/imx/imx51_ipuv3reg.h:1.2 --- src/sys/arch/arm/imx/imx51_ipuv3reg.h:1.1 Tue Apr 17 10:19:57 2012 +++ src/sys/arch/arm/imx/imx51_ipuv3reg.h Fri Nov 7 11:54:18 2014 @@ -1,4 +1,4 @@ -/* $NetBSD: imx51_ipuv3reg.h,v 1.1 2012/04/17 10:19:57 bsh Exp $ */ +/* $NetBSD: imx51_ipuv3reg.h,v 1.2 2014/11/07 11:54:18 hkenken Exp $ */ /* * Copyright (c) 2011, 2012 Genetec Corporation. All rights reserved. * Written by Hashimoto Kenichi for Genetec Corporation. @@ -95,11 +95,11 @@ #define IPU_CM_SKIP 0x000000bc #define IPU_CM_DISP_ALT_CONF 0x000000c0 #define IPU_CM_DISP_GEN 0x000000c4 +#define CM_DISP_GEN_DI1_COUNTER_RELEASE __BIT(25) #define CM_DISP_GEN_DI0_COUNTER_RELEASE __BIT(24) -#define CM_DISP_GEN_DI1_COUNTER_RELEASE __BIT(23) -#define CM_DISP_GEN_MCU_MAX_BURST_STOP __BIT(22) -#define CM_DISP_GEN_MCU_T_SHIFT 18 -#define CM_DISP_GEN_MCU_T(n) ((n) << CM_DISP_GEN_MCU_T_SHIFT) +#define CM_DISP_GEN_MCU_CSI_VSYNC_DEST __BIT(23) +#define CM_DISP_GEN_MCU_MAX_BURST_STOP __BIT(22) +#define CM_DISP_GEN_MCU_T __BITS(18, 21) #define IPU_CM_DISP_ALT1 0x000000c8 #define IPU_CM_DISP_ALT2 0x000000cc #define IPU_CM_DISP_ALT3 0x000000d0 @@ -270,10 +270,11 @@ #define DI_GENERAL_POLARITY(n) (1 << ((n) - 1)) #define IPU_DI_BS_CLKGEN0 0x00000004 -#define DI_BS_CLKGEN0_OFFSET_SHIFT 16 +#define DI_BS_CLKGEN0_OFFSET __BITS(24, 16) +#define DI_BS_CLKGEN0_PERIOD __BITS(11, 0) #define IPU_DI_BS_CLKGEN1 0x00000008 -#define DI_BS_CLKGEN1_DOWN_SHIFT 16 -#define DI_BS_CLKGEN1_UP_SHIFT 0 +#define DI_BS_CLKGEN1_DOWN __BITS(24, 16) +#define DI_BS_CLKGEN1_UP __BITS(8, 0) #define IPU_DI_SW_GEN0(n) (0x0000000c + ((n) - 1) * 4) #define DI_SW_GEN0_RUN_VAL __BITS(30, 19) #define DI_SW_GEN0_RUN_RESOL __BITS(18, 16) @@ -298,20 +299,17 @@ #define IPU_DI_SYNC_AS_GEN 0x00000054 #define DI_SYNC_AS_GEN_SYNC_START_EN __BIT(28) #define DI_SYNC_AS_GEN_VSYNC_SEL __BITS(15, 13) -#define DI_SYNC_AS_GEN_VSYNC_SEL_SHIFT 13 -#define DI_SYNC_AS_GEN_SYNC_STAR __BITS(11, 0) +#define DI_SYNC_AS_GEN_SYNC_START __BITS(11, 0) #define IPU_DI_DW_GEN(n) (0x00000058 + (n) * 4) -#define DI_DW_GEN_ACCESS_SIZE_SHIFT 24 -#define DI_DW_GEN_COMPONNENT_SIZE_SHIFT 16 -#define DI_DW_GEN_PIN_SHIFT(n) (((n) - 11) * 2) -#define DI_DW_GEN_PIN(n) __BITS(DI_DW_GEN_PIN_SHIFT(n) + 1, \ - DI_DW_GEN_PIN_SHIFT(n)) +#define DI_DW_GEN_ACCESS_SIZE __BITS(31, 24) +#define DI_DW_GEN_COMPONNENT_SIZE __BITS(23, 16) +#define DI_DW_GEN_PIN(n) __BITS((((n) - 11) * 2) + 1, \ + ((n) - 11) * 2) #define IPU_DI_DW_SET(n, m) (0x00000088 + (n) * 4 + (m) * 0x30) -#define DI_DW_SET_DOWN_SHIFT 16 -#define DI_DW_SET_UP_SHIFT 0 +#define DI_DW_SET_DOWN __BITS(24, 16) +#define DI_DW_SET_UP __BITS(8, 0) #define IPU_DI_STP_REP(n) (0x00000148 + ((n - 1) / 2) * 4) -#define DI_STP_REP_SHIFT(n) (((n - 1) % 2) * 16) -#define DI_STP_REP_MASK(n) (__BITS(11, 0) << DI_STP_REP_SHIFT((n))) +#define DI_STP_REP(n) (__BITS(11, 0) << (((n - 1) % 2) * 16)) #define IPU_DI_SER_CONF 0x0000015c #define IPU_DI_SSC 0x00000160 #define IPU_DI_POL 0x00000164