Module Name: src Committed By: jmcneill Date: Sat Nov 8 11:28:52 UTC 2014
Modified Files: src/sys/arch/arm/allwinner: awin_reg.h Log Message: add some more A31 soft reset bits To generate a diff of this commit: cvs rdiff -u -r1.44 -r1.45 src/sys/arch/arm/allwinner/awin_reg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/arch/arm/allwinner/awin_reg.h diff -u src/sys/arch/arm/allwinner/awin_reg.h:1.44 src/sys/arch/arm/allwinner/awin_reg.h:1.45 --- src/sys/arch/arm/allwinner/awin_reg.h:1.44 Sat Nov 8 00:31:54 2014 +++ src/sys/arch/arm/allwinner/awin_reg.h Sat Nov 8 11:28:52 2014 @@ -1888,7 +1888,21 @@ struct awin_mmc_idma_descriptor { #define AWIN_A31_AHB_RESET0_SS_RST __BIT(5) #define AWIN_A31_AHB_RESET0_MIPIDSI_RST __BIT(1) +#define AWIN_A31_AHB_RESET1_DRC1_RST __BIT(26) +#define AWIN_A31_AHB_RESET1_DRC0_RST __BIT(25) +#define AWIN_A31_AHB_RESET1_DEU1_RST __BIT(24) +#define AWIN_A31_AHB_RESET1_DEU0_RST __BIT(23) +#define AWIN_A31_AHB_RESET1_GPU_RST __BIT(20) +#define AWIN_A31_AHB_RESET1_MP_RST __BIT(18) +#define AWIN_A31_AHB_RESET1_FE1_RST __BIT(15) +#define AWIN_A31_AHB_RESET1_FE0_RST __BIT(14) +#define AWIN_A31_AHB_RESET1_BE1_RST __BIT(13) +#define AWIN_A31_AHB_RESET1_BE0_RST __BIT(12) #define AWIN_A31_AHB_RESET1_HDMI_RST __BIT(11) +#define AWIN_A31_AHB_RESET1_CSI_RST __BIT(8) +#define AWIN_A31_AHB_RESET1_LCD1_RST __BIT(5) +#define AWIN_A31_AHB_RESET1_LCD0_RST __BIT(4) +#define AWIN_A31_AHB_RESET1_VE_RST __BIT(0) #define AWIN_A31_APB1_RESET_DAUDIO1_RST __BIT(13) #define AWIN_A31_APB1_RESET_DAUDIO0_RST __BIT(12)