Module Name: src
Committed By: skrll
Date: Sun Nov 9 09:18:07 UTC 2014
Modified Files:
src/sys/arch/arm/arm32: bus_dma.c
Log Message:
Post a dmb before invalidating the cache in the post-{read,write}
operations to ensure that any/all cachelines brought in via speculation
are really flushed.
To generate a diff of this commit:
cvs rdiff -u -r1.88 -r1.89 src/sys/arch/arm/arm32/bus_dma.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm32/bus_dma.c
diff -u src/sys/arch/arm/arm32/bus_dma.c:1.88 src/sys/arch/arm/arm32/bus_dma.c:1.89
--- src/sys/arch/arm/arm32/bus_dma.c:1.88 Sat Oct 18 08:33:24 2014
+++ src/sys/arch/arm/arm32/bus_dma.c Sun Nov 9 09:18:07 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: bus_dma.c,v 1.88 2014/10/18 08:33:24 snj Exp $ */
+/* $NetBSD: bus_dma.c,v 1.89 2014/11/09 09:18:07 skrll Exp $ */
/*-
* Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
@@ -35,7 +35,7 @@
#include "opt_arm_bus_space.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.88 2014/10/18 08:33:24 snj Exp $");
+__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.89 2014/11/09 09:18:07 skrll Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -832,11 +832,13 @@ _bus_dmamap_sync_segment(vaddr_t va, pad
*/
case BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE:
STAT_INCR(sync_postreadwrite);
+ __asm __volatile("dmb" ::: "memory");;
cpu_dcache_inv_range(va, len);
cpu_sdcache_inv_range(va, pa, len);
break;
case BUS_DMASYNC_POSTREAD:
STAT_INCR(sync_postread);
+ __asm __volatile("dmb" ::: "memory");;
cpu_dcache_inv_range(va, len);
cpu_sdcache_inv_range(va, pa, len);
break;
