CVS commit: src/sys/dev/mii

[NONAKA Kimihiro]

Module Name:    src
Committed By:   nonaka
Date:           Sun Nov  9 19:35:43 UTC 2014

Modified Files:
        src/sys/dev/mii: rgephy.c

Log Message:
more mention RTL8251.


To generate a diff of this commit:
cvs rdiff -u -r1.36 -r1.37 src/sys/dev/mii/rgephy.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.


Modified files:

Index: src/sys/dev/mii/rgephy.c
diff -u src/sys/dev/mii/rgephy.c:1.36 src/sys/dev/mii/rgephy.c:1.37
--- src/sys/dev/mii/rgephy.c:1.36	Sun Nov  9 17:54:45 2014
+++ src/sys/dev/mii/rgephy.c	Sun Nov  9 19:35:43 2014
@@ -1,4 +1,4 @@
-/*	$NetBSD: rgephy.c,v 1.36 2014/11/09 17:54:45 nonaka Exp $	*/
+/*	$NetBSD: rgephy.c,v 1.37 2014/11/09 19:35:43 nonaka Exp $	*/
 
 /*
  * Copyright (c) 2003
@@ -33,7 +33,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: rgephy.c,v 1.36 2014/11/09 17:54:45 nonaka Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rgephy.c,v 1.37 2014/11/09 19:35:43 nonaka Exp $");
 
 
 /*
@@ -456,7 +456,8 @@ rgephy_loop(struct mii_softc *sc)
 	uint32_t bmsr;
 	int i;
 
-	if (sc->mii_mpd_rev < 2) {
+	if (sc->mii_mpd_model != MII_MODEL_REALTEK_RTL8251 &&
+	    sc->mii_mpd_rev < 2) {
 		PHY_WRITE(sc, MII_BMCR, BMCR_PDOWN);
 		DELAY(1000);
 	}