Module Name: src
Committed By: martin
Date: Thu Dec 4 11:08:38 UTC 2014
Modified Files:
src/sys/arch/arm/allwinner [netbsd-7]: awin_board.c awin_mmc.c
awin_reg.h
Log Message:
Pull up following revision(s) (requested by jmcneill in ticket #294):
sys/arch/arm/allwinner/awin_mmc.c: revision 1.16
sys/arch/arm/allwinner/awin_board.c: revision 1.29
sys/arch/arm/allwinner/awin_reg.h: revision 1.55,1.57
Add mixer processor regs.
-
Fix some mixer processor definitions, add A31 PLL6 cfg lock bit and
some extra SD CLK bits for A31, when enabling pll, wait for pll to
become stable before returning
-
Clock fixes:
- Don't rely on U-boot to enable AHB gating
- Instead of always running at 100MHz (!), calculate proper clk dividers.
- Replace PLL6 parsing code with a call to awin_pll6_get_rate()
To generate a diff of this commit:
cvs rdiff -u -r1.14.6.3 -r1.14.6.4 src/sys/arch/arm/allwinner/awin_board.c
cvs rdiff -u -r1.3.10.2 -r1.3.10.3 src/sys/arch/arm/allwinner/awin_mmc.c
cvs rdiff -u -r1.14.2.8 -r1.14.2.9 src/sys/arch/arm/allwinner/awin_reg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/allwinner/awin_board.c
diff -u src/sys/arch/arm/allwinner/awin_board.c:1.14.6.3 src/sys/arch/arm/allwinner/awin_board.c:1.14.6.4
--- src/sys/arch/arm/allwinner/awin_board.c:1.14.6.3 Fri Nov 14 13:37:39 2014
+++ src/sys/arch/arm/allwinner/awin_board.c Thu Dec 4 11:08:38 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: awin_board.c,v 1.14.6.3 2014/11/14 13:37:39 martin Exp $ */
+/* $NetBSD: awin_board.c,v 1.14.6.4 2014/12/04 11:08:38 martin Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -36,7 +36,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: awin_board.c,v 1.14.6.3 2014/11/14 13:37:39 martin Exp $");
+__KERNEL_RCSID(1, "$NetBSD: awin_board.c,v 1.14.6.4 2014/12/04 11:08:38 martin Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -345,6 +345,13 @@ awin_pll6_enable(void)
if (ncfg != ocfg) {
bus_space_write_4(bst, bsh,
AWIN_CCM_OFFSET + AWIN_PLL6_CFG_REG, ncfg);
+
+ if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+ do {
+ ncfg = bus_space_read_4(bst, bsh,
+ AWIN_CCM_OFFSET + AWIN_PLL6_CFG_REG);
+ } while ((ncfg & AWIN_A31_PLL6_CFG_LOCK) == 0);
+ }
}
#if 0
printf(" [pll6=%#x->%#x:n=%ju k=%ju m=%ju] ",
@@ -390,6 +397,13 @@ awin_pll2_enable(void)
if (ncfg != ocfg) {
bus_space_write_4(bst, bsh,
AWIN_CCM_OFFSET + AWIN_PLL2_CFG_REG, ncfg);
+
+ if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+ do {
+ ncfg = bus_space_read_4(bst, bsh,
+ AWIN_CCM_OFFSET + AWIN_PLL2_CFG_REG);
+ } while ((ncfg & AWIN_A31_PLL2_CFG_LOCK) == 0);
+ }
}
}
@@ -459,6 +473,13 @@ awin_pll7_enable(void)
if (ncfg != ocfg) {
bus_space_write_4(bst, bsh,
AWIN_CCM_OFFSET + AWIN_PLL7_CFG_REG, ncfg);
+
+ if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+ do {
+ ncfg = bus_space_read_4(bst, bsh,
+ AWIN_CCM_OFFSET + AWIN_PLL7_CFG_REG);
+ } while ((ncfg & AWIN_A31_PLL7_CFG_LOCK) == 0);
+ }
}
}
Index: src/sys/arch/arm/allwinner/awin_mmc.c
diff -u src/sys/arch/arm/allwinner/awin_mmc.c:1.3.10.2 src/sys/arch/arm/allwinner/awin_mmc.c:1.3.10.3
--- src/sys/arch/arm/allwinner/awin_mmc.c:1.3.10.2 Sun Nov 9 14:42:33 2014
+++ src/sys/arch/arm/allwinner/awin_mmc.c Thu Dec 4 11:08:38 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: awin_mmc.c,v 1.3.10.2 2014/11/09 14:42:33 martin Exp $ */
+/* $NetBSD: awin_mmc.c,v 1.3.10.3 2014/12/04 11:08:38 martin Exp $ */
/*-
* Copyright (c) 2014 Jared D. McNeill <[email protected]>
@@ -29,7 +29,7 @@
#include "locators.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: awin_mmc.c,v 1.3.10.2 2014/11/09 14:42:33 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: awin_mmc.c,v 1.3.10.3 2014/12/04 11:08:38 martin Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -97,13 +97,10 @@ struct awin_mmc_softc {
kcondvar_t sc_intr_cv;
kcondvar_t sc_idst_cv;
- int sc_mmc_number;
int sc_mmc_width;
int sc_mmc_present;
device_t sc_sdmmc_dev;
- unsigned int sc_pll_freq;
- unsigned int sc_mod_clk;
uint32_t sc_fifo_reg;
@@ -151,53 +148,6 @@ awin_mmc_match(device_t parent, cfdata_t
return 1;
}
-static void
-awin_mmc_probe_clocks(struct awin_mmc_softc *sc, struct awinio_attach_args *aio)
-{
- uint32_t val, freq;
- int n, k, p, div;
-
- val = bus_space_read_4(aio->aio_core_bst, aio->aio_ccm_bsh,
- AWIN_PLL6_CFG_REG);
-
- if (awin_chip_id() == AWIN_CHIP_ID_A31) {
- n = ((val >> 8) & 0x1f) + 1;
- k = ((val >> 4) & 3) + 1;
- freq = 24000000 * n * k / 2;
-#ifdef AWIN_MMC_DEBUG
- device_printf(sc->sc_dev, "n = %d k = %d freq = %u\n",
- n, k, freq);
-#endif
- } else {
- n = (val >> 8) & 0x1f;
- k = ((val >> 4) & 3) + 1;
- p = 1 << ((val >> 16) & 3);
- freq = 24000000 * n * k / p;
-#ifdef AWIN_MMC_DEBUG
- device_printf(sc->sc_dev, "n = %d k = %d p = %d freq = %u\n",
- n, k, p, freq);
-#endif
- }
-
- sc->sc_pll_freq = freq;
- div = ((sc->sc_pll_freq + 99999999) / 100000000) - 1;
- sc->sc_mod_clk = sc->sc_pll_freq / (div + 1);
-
- bus_space_write_4(aio->aio_core_bst, aio->aio_ccm_bsh,
- AWIN_SD0_CLK_REG + (sc->sc_mmc_number * 4),
- AWIN_PLL_CFG_ENABLE | AWIN_PLL_CFG_PLL6 | div);
-
- if (awin_chip_id() == AWIN_CHIP_ID_A31) {
- awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
- AWIN_A31_AHB_RESET0_REG,
- AWIN_A31_AHB_RESET0_SD0_RST << sc->sc_mmc_number, 0);
- }
-
-#ifdef AWIN_MMC_DEBUG
- aprint_normal_dev(sc->sc_dev, "PLL6 @ %u Hz\n", freq);
-#endif
-}
-
static int
awin_mmc_idma_setup(struct awin_mmc_softc *sc)
{
@@ -253,7 +203,6 @@ awin_mmc_attach(device_t parent, device_
sc->sc_dev = self;
sc->sc_bst = aio->aio_core_bst;
sc->sc_dmat = aio->aio_dmat;
- sc->sc_mmc_number = loc->loc_port;
mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_BIO);
cv_init(&sc->sc_intr_cv, "awinmmcirq");
cv_init(&sc->sc_idst_cv, "awinmmcdma");
@@ -268,7 +217,16 @@ awin_mmc_attach(device_t parent, device_
aprint_naive("\n");
aprint_normal(": SD3.0 (%s)\n", sc->sc_use_dma ? "DMA" : "PIO");
- awin_mmc_probe_clocks(sc, aio);
+ awin_pll6_enable();
+
+ awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
+ AWIN_AHB_GATING0_REG,
+ AWIN_AHB_GATING0_SDMMC0 << loc->loc_port, 0);
+ if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+ awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
+ AWIN_A31_AHB_RESET0_REG,
+ AWIN_A31_AHB_RESET0_SD0_RST << loc->loc_port, 0);
+ }
if (prop_dictionary_get_cstring_nocopy(cfg, "detect-gpio", &pin_name)) {
if (!awin_gpio_pin_reserve(pin_name, &sc->sc_gpio_detect)) {
@@ -539,7 +497,9 @@ static int
awin_mmc_bus_clock(sdmmc_chipset_handle_t sch, int freq)
{
struct awin_mmc_softc *sc = sch;
- uint32_t odly, sdly, clkcr;
+ uint32_t odly, sdly, clkcr, clksrc, n, m;
+ u_int pll_freq = awin_pll6_get_rate() / 1000;
+ u_int osc24m_freq = AWIN_REF_FREQ / 1000;
#ifdef AWIN_MMC_DEBUG
aprint_normal_dev(sc->sc_dev, "freq = %d\n", freq);
@@ -547,13 +507,22 @@ awin_mmc_bus_clock(sdmmc_chipset_handle_
if (freq <= 400) {
odly = 0;
- sdly = 7;
+ sdly = awin_chip_id() == AWIN_CHIP_ID_A31 ? 0 : 7;
+ clksrc = AWIN_SD_CLK_SRC_SEL_OSC24M;
+ n = 2;
+ m = ((osc24m_freq / (1 << n)) / freq) - 1;
} else if (freq <= 25000) {
odly = 0;
sdly = 5;
+ clksrc = AWIN_SD_CLK_SRC_SEL_PLL6;
+ n = 0;
+ m = (pll_freq / freq) - 1;
} else if (freq <= 50000) {
odly = 3;
sdly = 5;
+ clksrc = AWIN_SD_CLK_SRC_SEL_PLL6;
+ n = 0;
+ m = (pll_freq / freq) - 1;
} else {
/* UHS speeds not implemented yet */
return 1;
@@ -573,10 +542,17 @@ awin_mmc_bus_clock(sdmmc_chipset_handle_
return 1;
uint32_t clk = bus_space_read_4(sc->sc_bst, sc->sc_clk_bsh, 0);
+ clk &= ~AWIN_SD_CLK_SRC_SEL;
+ clk |= __SHIFTIN(clksrc, AWIN_SD_CLK_SRC_SEL);
+ clk &= ~AWIN_SD_CLK_DIV_RATIO_N;
+ clk |= __SHIFTIN(n, AWIN_SD_CLK_DIV_RATIO_N);
+ clk &= ~AWIN_SD_CLK_DIV_RATIO_M;
+ clk |= __SHIFTIN(m, AWIN_SD_CLK_DIV_RATIO_M);
clk &= ~AWIN_SD_CLK_OUTPUT_PHASE_CTR;
clk |= __SHIFTIN(odly, AWIN_SD_CLK_OUTPUT_PHASE_CTR);
clk &= ~AWIN_SD_CLK_PHASE_CTR;
clk |= __SHIFTIN(sdly, AWIN_SD_CLK_PHASE_CTR);
+ clk |= AWIN_PLL_CFG_ENABLE;
bus_space_write_4(sc->sc_bst, sc->sc_clk_bsh, 0, clk);
clkcr |= AWIN_MMC_CLKCR_CARDCLKON;
Index: src/sys/arch/arm/allwinner/awin_reg.h
diff -u src/sys/arch/arm/allwinner/awin_reg.h:1.14.2.8 src/sys/arch/arm/allwinner/awin_reg.h:1.14.2.9
--- src/sys/arch/arm/allwinner/awin_reg.h:1.14.2.8 Mon Dec 1 13:23:49 2014
+++ src/sys/arch/arm/allwinner/awin_reg.h Thu Dec 4 11:08:38 2014
@@ -1076,6 +1076,10 @@ struct awin_mmc_idma_descriptor {
#define AWIN_CLK_SRC_SEL_DE_PLL5 2
#define AWIN_CLK_SRC_SEL_CIR_LOSC 0
#define AWIN_CLK_SRC_SEL_CIR_HOSC 1
+#define AWIN_CLK_SRC_SEL_MP_PLL3 0
+#define AWIN_CLK_SRC_SEL_MP_PLL7 1
+#define AWIN_CLK_SRC_SEL_MP_PLL9 2
+#define AWIN_CLK_SRC_SEL_MP_PLL10 3
#define AWIN_CLK_DIV_RATIO_N __BITS(17,16)
#define AWIN_CLK_DIV_RATIO_M __BITS(3,0)
@@ -1141,8 +1145,13 @@ struct awin_mmc_idma_descriptor {
#define AWIN_HDMI_CLK_SRC_SEL_PLL7_2X 3
#define AWIN_HDMI_CLK_DIV_RATIO_M __BITS(3,0)
+#define AWIN_SD_CLK_SRC_SEL __BITS(25,24)
+#define AWIN_SD_CLK_SRC_SEL_OSC24M 0
+#define AWIN_SD_CLK_SRC_SEL_PLL6 1
#define AWIN_SD_CLK_PHASE_CTR __BITS(22,20)
+#define AWIN_SD_CLK_DIV_RATIO_N __BITS(17,16)
#define AWIN_SD_CLK_OUTPUT_PHASE_CTR __BITS(10,8)
+#define AWIN_SD_CLK_DIV_RATIO_M __BITS(3,0)
#define AWIN_CLK_OUT_ENABLE __BIT(31)
#define AWIN_CLK_OUT_SRC_SEL __BITS(25,24)
@@ -2019,6 +2028,220 @@ struct awin_mmc_idma_descriptor {
#define AWIN_HDMI_DDC_CLOCK_M __BITS(6,3)
#define AWIN_HDMI_DDC_CLOCK_N __BITS(2,0)
+/* Mixer processor */
+#define AWIN_MP_CTL_REG 0x0000
+#define AWIN_MP_STS_REG 0x0004
+#define AWIN_MP_IDMAGLBCTL_REG 0x0008
+#define AWIN_MP_IDMA_H4ADD_REG 0x000C
+#define AWIN_MP_IDMA_L32ADD_REG(n) (0x0010 + ((n) * 4))
+#define AWIN_MP_IDMALINEWIDTH_REG(n) (0x0020 + ((n) * 4))
+#define AWIN_MP_IDMASIZE_REG(n) (0x0030 + ((n) * 4))
+#define AWIN_MP_IDMACOOR_REG(n) (0x0040 + ((n) * 4))
+#define AWIN_MP_IDMASET_REG(n) (0x0050 + ((n) * 4))
+#define AWIN_MP_IDMAFILLCOLOR_REG(n) (0x0060 + ((n) * 4))
+#define AWIN_MP_CSC0CTL_REG 0x0074
+#define AWIN_MP_CSC1CTL_REG 0x0078
+#define AWIN_MP_SCACTL_REG 0x0080
+#define AWIN_MP_SCAOUTSIZE_REG 0x0084
+#define AWIN_MP_SCAHORFCT_REG 0x0088
+#define AWIN_MP_SCAVERFCT_REG 0x008c
+#define AWIN_MP_SCAHORPHASE_REG 0x0090
+#define AWIN_MP_SCAVERPHASE_REG 0x0094
+#define AWIN_MP_ROPCTL_REG 0x00b0
+#define AWIN_MP_ROPIDX0CTL_REG 0x00b8
+#define AWIN_MP_ROPIDX1CTL_REG 0x00bc
+#define AWIN_MP_ALPHACKCTL_REG 0x00c0
+#define AWIN_MP_CKMIN_REG 0x00c4
+#define AWIN_MP_CKMAX_REG 0x00c8
+#define AWIN_MP_ROPOUTFILLCOLOR_REG 0x00cc
+#define AWIN_MP_CSC2CTL_REG 0x00d0
+#define AWIN_MP_OUTCTL_REG 0x00e0
+#define AWIN_MP_OUTSIZE_REG 0x00e8
+#define AWIN_MP_OUTH4ADD_REG 0x00ec
+#define AWIN_MP_OUTL32ADD_REG(n) (0x00f0 + ((n) * 4))
+#define AWIN_MP_OUTLINEWIDTH_REG(n) (0x0100 + ((n) * 4))
+#define AWIN_MP_OUTALPHACTL_REG 0x0120
+#define AWIN_MP_MBCTL_REG(n) (0x0130 + ((n) * 4))
+#define AWIN_MP_CMDQUECTL_REG 0x0140
+#define AWIN_MP_CMDQUESTS_REG 0x0144
+#define AWIN_MP_CMDQUEADD_REG 0x0148
+#define AWIN_MP_ICSCYGCOEF_REG(n) (0x0180 + ((n) * 4))
+#define AWIN_MP_ICSCYGCONS_REG 0x018c
+#define AWIN_MP_ICSCCURCOEF_REG(n) (0x0190 + ((n) * 4))
+#define AWIN_MP_ICSCCURCONS_REG 0x019c
+#define AWIN_MP_ICSCVBCOEF_REG(n) (0x01a0 + ((n) * 4))
+#define AWIN_MP_ICSCVBCONS_REG 0x01ac
+#define AWIN_MP_OCSCYGCOEF_REG(n) (0x01c0 + ((n) * 4))
+#define AWIN_MP_OCSCYGCONS_REG 0x01cc
+#define AWIN_MP_OCSCCURCOEF_REG(n) (0x01d0 + ((n) * 4))
+#define AWIN_MP_OCSCCURCONS_REG 0x01dc
+#define AWIN_MP_OCSCVBCOEF_REG(n) (0x01e0 + ((n) * 4))
+#define AWIN_MP_OCSCVBCONS_REG 0x01ec
+#define AWIN_MP_SCAL_HORIZ_FILT_BLOCK 0x0200
+#define AWIN_MP_SCAL_VERT_FILT_BLOCK 0x0280
+#define AWIN_MP_PALETTE_TABLE 0x0400
+
+#define AWIN_MP_CTL_HWERRIRQ_EN __BIT(9)
+#define AWIN_MP_CTL_FINISHIRQ_EN __BIT(8)
+#define AWIN_MP_CTL_START_CTL __BIT(1)
+#define AWIN_MP_CTL_MP_EN __BIT(0)
+
+#define AWIN_MP_STS_HWERR_FLAG __BIT(13)
+#define AWIN_MP_STS_BUSY_FLAG __BIT(12)
+#define AWIN_MP_STS_HWERRIRQ_FLAG __BIT(9)
+#define AWIN_MP_STS_FINISHIRQ_FLAG __BIT(8)
+
+#define AWIN_MP_IDMAGLBCTL_MEMSCANORDER __BITS(9,8)
+#define AWIN_MP_IDMAGLBCTL_MEMSCANORDER_TD_LR 0
+#define AWIN_MP_IDMAGLBCTL_MEMSCANORDER_TD_RL 1
+#define AWIN_MP_IDMAGLBCTL_MEMSCANORDER_DT_LR 2
+#define AWIN_MP_IDMAGLBCTL_MEMSCANORDER_DT_RL 3
+
+#define AWIN_MP_IDMA_H4ADD_IDMA3_H4ADD __BITS(27,24)
+#define AWIN_MP_IDMA_H4ADD_IDMA2_H4ADD __BITS(19,16)
+#define AWIN_MP_IDMA_H4ADD_IDMA1_H4ADD __BITS(11,8)
+#define AWIN_MP_IDMA_H4ADD_IDMA0_H4ADD __BITS(3,0)
+
+#define AWIN_MP_IDMASIZE_HEIGHT __BITS(28,16)
+#define AWIN_MP_IDMASIZE_WIDTH __BITS(12,0)
+
+#define AWIN_MP_IDMACOOR_YCOOR __BITS(31,16)
+#define AWIN_MP_IDMACOOR_XCOOR __BITS(15,0)
+
+#define AWIN_MP_IDMASET_IDMA_GLBALPHA __BITS(31,24)
+#define AWIN_MP_IDMASET_MBFMT __BIT(22)
+#define AWIN_MP_IDMASET_MBSIZE __BITS(21,20)
+#define AWIN_MP_IDMASET_MBSIZE_16X16 0
+#define AWIN_MP_IDMASET_MBSIZE_32X32 1
+#define AWIN_MP_IDMASET_MBSIZE_64X64 2
+#define AWIN_MP_IDMASET_MBSIZE_128X128 3
+#define AWIN_MP_IDMASET_IDMA_FCMODEN __BIT(16)
+#define AWIN_MP_IDMASET_IDMA_PS __BITS(15,12)
+#define AWIN_MP_IDMASET_IDMA_FMT __BITS(11,8)
+#define AWIN_MP_IDMASET_IDMA_FMT_ARGB8888 0
+#define AWIN_MP_IDMASET_IDMA_FMT_ARGB4444 1
+#define AWIN_MP_IDMASET_IDMA_FMT_ARGB1555 2
+#define AWIN_MP_IDMASET_IDMA_FMT_RGB565 3
+#define AWIN_MP_IDMASET_IDMA_FMT_IYUV422 4
+#define AWIN_MP_IDMASET_IDMA_FMT_UV88 5
+#define AWIN_MP_IDMASET_IDMA_FMT_Y8 6
+#define AWIN_MP_IDMASET_IDMA_FMT_8BPP_MP 7
+#define AWIN_MP_IDMASET_IDMA_FMT_4BPP_MP 8
+#define AWIN_MP_IDMASET_IDMA_FMT_2BPP_MP 9
+#define AWIN_MP_IDMASET_IDMA_FMT_1BPP_MP 10
+#define AWIN_MP_IDMASET_IDMA_ROPMIRCTL __BITS(7,4)
+#define AWIN_MP_IDMASET_IDMA_ROPMIRCTL_NORMAL 0
+#define AWIN_MP_IDMASET_IDMA_ROPMIRCTL_X 1
+#define AWIN_MP_IDMASET_IDMA_ROPMIRCTL_Y 2
+#define AWIN_MP_IDMASET_IDMA_ROPMIRCTL_XY 3
+#define AWIN_MP_IDMASET_IDMA_ROPMIRCTL_A 4
+#define AWIN_MP_IDMASET_IDMA_ROPMIRCTL_AX 5
+#define AWIN_MP_IDMASET_IDMA_ROPMIRCTL_AY 6
+#define AWIN_MP_IDMASET_IDMA_ROPMIRCTL_AXY 7
+#define AWIN_MP_IDMASET_IDMA_ALPHACTL __BITS(3,2)
+#define AWIN_MP_IDMASET_IDMA_WORKMOD __BIT(1)
+#define AWIN_MP_IDMASET_IDMA_EN __BIT(0)
+
+#define AWIN_MP_CSCxCTL_DATAMOD __BITS(7,4)
+#define AWIN_MP_CSCxCTL_EN __BIT(0)
+
+#define AWIN_MP_SCACTL_SCA_ALGSEL __BITS(5,4)
+#define AWIN_MP_SCACTL_SCA_EN __BIT(0)
+
+#define AWIN_MP_SCAOUTSIZE_OUTHEIGHT __BITS(28,16)
+#define AWIN_MP_SCAOUTSIZE_OUTWIDTH __BITS(12,0)
+
+#define AWIN_MP_SCAHORFCT_HORINTFCT __BITS(23,16)
+#define AWIN_MP_SCAHORFCT_HORFRAFCT __BITS(15,0)
+
+#define AWIN_MP_SCAVERFCT_VERINTFCT __BITS(23,16)
+#define AWIN_MP_SCAVERFCT_VERFRAFCT __BITS(15,0)
+
+#define AWIN_MP_SCAHORPHASE_HORPHASE __BITS(19,0)
+
+#define AWIN_MP_SCAVERPHASE_VERPHASE __BITS(19,0)
+
+#define AWIN_MP_ROPCTL_ROP_ALPHABYPASSSEL __BITS(15,14)
+#define AWIN_MP_ROPCTL_ROP_REDBYPASSSEL __BITS(13,12)
+#define AWIN_MP_ROPCTL_ROP_GREENBYPASSSEL __BITS(11,10)
+#define AWIN_MP_ROPCTL_ROP_BLUEBYPASSSEL __BITS(9,8)
+#define AWIN_MP_ROPCTL_ROP_ALPHABYPASSEN __BIT(7)
+#define AWIN_MP_ROPCTL_ROP_REDBYPASSEN __BIT(6)
+#define AWIN_MP_ROPCTL_ROP_GREENBYPASSEN __BIT(5)
+#define AWIN_MP_ROPCTL_ROP_BLUEBYPSASEN __BIT(4)
+#define AWIN_MP_ROPCTL_ROP_MOD __BIT(0)
+
+#define AWIN_MP_ROPIDXxCTL_CH2IGN_EN __BIT(18)
+#define AWIN_MP_ROPIDXxCTL_CH1IGN_EN __BIT(17)
+#define AWIN_MP_ROPIDXxCTL_CH0IGN_EN __BIT(16)
+#define AWIN_MP_ROPIDXxCTL_NOD7_CTL __BIT(15)
+#define AWIN_MP_ROPIDXxCTL_NOD6_CTL __BITS(14,11)
+#define AWIN_MP_ROPIDXxCTL_NOD5_CTL __BIT(10)
+#define AWIN_MP_ROPIDXxCTL_NOD4_CTL __BITS(9,6)
+#define AWIN_MP_ROPIDXxCTL_NOD3_CTL __BIT(5)
+#define AWIN_MP_ROPIDXxCTL_NOD2_CTL __BIT(4)
+#define AWIN_MP_ROPIDXxCTL_NOD1_CTL __BIT(3)
+#define AWIN_MP_ROPIDXxCTL_NOD0_CTL __BITS(2,0)
+
+#define AWIN_MP_ALPHACKCTL_CH3GALPHA __BITS(31,24)
+#define AWIN_MP_ALPHACKCTL_ROPGALPHA __BITS(23,16)
+#define AWIN_MP_ALPHACKCTL_CH3ALPHACTL __BITS(15,14)
+#define AWIN_MP_ALPHACKCTL_ROPALPHACTL __BITS(13,12)
+#define AWIN_MP_ALPHACKCTL_CK_REDCON __BIT(10)
+#define AWIN_MP_ALPHACKCTL_CK_GREENCON __BIT(9)
+#define AWIN_MP_ALPHACKCTL_CK_BLUECON __BIT(8)
+#define AWIN_MP_ALPHACKCTL_ICH3_PREMUL __BIT(7)
+#define AWIN_MP_ALPHACKCTL_IROP_PREMUL __BIT(6)
+#define AWIN_MP_ALPHACKCTL_O_PREMUL __BIT(5)
+#define AWIN_MP_ALPHACKCTL_PRI __BIT(4)
+#define AWIN_MP_ALPHACKCTL_ALPHACK_MOD __BITS(2,1)
+#define AWIN_MP_ALPHACKCTL_ALPHACK_EN __BIT(0)
+
+#define AWIN_MP_CSC2CTL_CSC2_EN __BIT(0)
+
+#define AWIN_MP_OUTCTL_OUT_PS __BITS(11,8)
+#define AWIN_MP_OUTCTL_RND_EN __BIT(7)
+#define AWIN_MP_OUTCTL_OUT_FMT __BITS(3,0)
+#define AWIN_MP_OUTCTL_OUT_FMT_ARGB8888 0
+#define AWIN_MP_OUTCTL_OUT_FMT_ARGB4444 1
+#define AWIN_MP_OUTCTL_OUT_FMT_ARGB1555 2
+#define AWIN_MP_OUTCTL_OUT_FMT_RGB565 3
+#define AWIN_MP_OUTCTL_OUT_FMT_IYUV422 4
+#define AWIN_MP_OUTCTL_OUT_FMT_YUV422_UVC 5
+#define AWIN_MP_OUTCTL_OUT_FMT_YUV422 6
+#define AWIN_MP_OUTCTL_OUT_FMT_8BPP_M 7
+#define AWIN_MP_OUTCTL_OUT_FMT_4BPP_M 8
+#define AWIN_MP_OUTCTL_OUT_FMT_2BPP_M 9
+#define AWIN_MP_OUTCTL_OUT_FMT_1BPP_M 10
+#define AWIN_MP_OUTCTL_OUT_FMT_YUV420_UVC 11
+#define AWIN_MP_OUTCTL_OUT_FMT_YUV420 12
+#define AWIN_MP_OUTCTL_OUT_FMT_YUV411_UVC 13
+#define AWIN_MP_OUTCTL_OUT_FMT_YUV411 14
+
+#define AWIN_MP_OUTSIZE_OUT_HEIGHT __BITS(28,16)
+#define AWIN_MP_OUTSIZE_OUT_WIDTH __BITS(12,0)
+
+#define AWIN_MP_OUTH4ADD_OUTCH2_H4ADD __BITS(19,16)
+#define AWIN_MP_OUTH4ADD_OUTCH1_H4ADD __BITS(11,8)
+#define AWIN_MP_OUTH4ADD_OUTCH0_H4ADD __BITS(3,0)
+
+#define AWIN_MP_OUTALPHACTL_IMG_ALPHA __BITS(31,24)
+#define AWIN_MP_OUTALPHACTL_NONIMG_ALPHA __BITS(23,16)
+#define AWIN_MP_OUTALPHACTL_A2ALPHACTL __BITS(7,6)
+#define AWIN_MP_OUTALPHACTL_A3ALPHACTL __BITS(5,4)
+#define AWIN_MP_OUTALPHACTL_A1ALPHACTL __BITS(3,2)
+#define AWIN_MP_OUTALPHACTL_A0ALPHACTL __BITS(1,0)
+
+#define AWIN_MP_MBCTL_Y_OFFSET __BITS(31,16)
+#define AWIN_MP_MBCTL_X_OFFSET __BITS(15,0)
+
+#define AWIN_MP_CMDQUECTL_FINISHIRQ_EN __BIT(8)
+#define AWIN_MP_CMDQUECTL_START_CTL __BIT(1)
+#define AWIN_MP_CMDQUECTL_EN __BIT(0)
+
+#define AWIN_MP_CMDQUESTS_BUSY_FLAG __BIT(12)
+#define AWIN_MP_CMDQUESTS_FINISHIRQ_FLAG __BIT(8)
+
/*
* A31 registers
*/
@@ -2081,6 +2304,8 @@ struct awin_mmc_idma_descriptor {
#define AWIN_A31_PLL3_CFG_FACTOR_N __BITS(14,8)
#define AWIN_A31_PLL3_CFG_PREDIV_M __BITS(3,0)
+#define AWIN_A31_PLL6_CFG_LOCK __BIT(28)
+
#define AWIN_A31_PLL7_CFG_MODE __BIT(30)
#define AWIN_A31_PLL7_CFG_LOCK __BIT(28)
#define AWIN_A31_PLL7_CFG_FRAC_CLK_OUT __BIT(25)
