Module Name: src
Committed By: martin
Date: Fri Dec 12 19:03:17 UTC 2014
Modified Files:
src/sys/dev/pci [netbsd-7]: pci_subr.c pcireg.h
Log Message:
Pull up following revision(s) (requested by msaitoh in ticket #312):
sys/dev/pci/pci_subr.c: revision 1.130
sys/dev/pci/pci_subr.c: revision 1.131
sys/dev/pci/pci_subr.c: revision 1.132
sys/dev/pci/pcireg.h: revision 1.97
sys/dev/pci/pcireg.h: revision 1.98
sys/dev/pci/pcireg.h: revision 1.99
sys/dev/pci/pci_subr.c: revision 1.127
sys/dev/pci/pci_subr.c: revision 1.128
sys/dev/pci/pci_subr.c: revision 1.129
Always print the Slot implemented bit in the PCIe Capabilities
Register using with onoff().
- Add some PCI subclass and interfaces.
- The interface of PCI_SUBCLASS_BRIDGE_RACEWAY is not decoded yet.
- Fix typo in a message.
- Add comment.
- Modify comment.
s/genric/generic/
Add comment.
Fix typo in comment.
Fix a bug that the specification revision of the Power Management function
was incorrectly printed in the output of capability "list".
The value is also printed in the detail output and it has no bug.
- Cleanup pci_conf_print_caplist. Use table. The reason why it loops twice
is that some capabilities appear multiple times (e.g. HyperTransport cap).
- Print the specification revision of Power Management and AGP not in
the capability list part but in the detail part.
Add some HyperTransport related defines. It's required for the MSI.
To generate a diff of this commit:
cvs rdiff -u -r1.124 -r1.124.2.1 src/sys/dev/pci/pci_subr.c
cvs rdiff -u -r1.95.2.1 -r1.95.2.2 src/sys/dev/pci/pcireg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/pci/pci_subr.c
diff -u src/sys/dev/pci/pci_subr.c:1.124 src/sys/dev/pci/pci_subr.c:1.124.2.1
--- src/sys/dev/pci/pci_subr.c:1.124 Mon Jun 9 11:08:05 2014
+++ src/sys/dev/pci/pci_subr.c Fri Dec 12 19:03:17 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: pci_subr.c,v 1.124 2014/06/09 11:08:05 msaitoh Exp $ */
+/* $NetBSD: pci_subr.c,v 1.124.2.1 2014/12/12 19:03:17 martin Exp $ */
/*
* Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
@@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.124 2014/06/09 11:08:05 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.124.2.1 2014/12/12 19:03:17 martin Exp $");
#ifdef _KERNEL_OPT
#include "opt_pci.h"
@@ -88,7 +88,7 @@ static const struct pci_class pci_subcla
/*
* Class 0x01.
- * Mass strage controller
+ * Mass storage controller
*/
/* ATA programming interface */
@@ -100,7 +100,16 @@ static const struct pci_class pci_interf
/* SATA programming interface */
static const struct pci_class pci_interface_sata[] = {
+ { "vendor specific", PCI_INTERFACE_SATA_VND, NULL, },
{ "AHCI 1.0", PCI_INTERFACE_SATA_AHCI10, NULL, },
+ { "Serial Storage Bus Interface", PCI_INTERFACE_SATA_SSBI, NULL, },
+ { NULL, 0, NULL, },
+};
+
+/* Flash programming interface */
+static const struct pci_class pci_interface_nvm[] = {
+ { "vendor specific", PCI_INTERFACE_NVM_VND, NULL, },
+ { "NVMHCI 1.0", PCI_INTERFACE_NVM_NVMHCI10, NULL, },
{ NULL, 0, NULL, },
};
@@ -116,7 +125,8 @@ static const struct pci_class pci_subcla
{ "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA,
pci_interface_sata, },
{ "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, },
- { "NVM", PCI_SUBCLASS_MASS_STORAGE_NVM, NULL, },
+ { "Flash", PCI_SUBCLASS_MASS_STORAGE_NVM,
+ pci_interface_nvm, },
{ "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, },
{ NULL, 0, NULL, },
};
@@ -165,7 +175,7 @@ static const struct pci_class pci_subcla
{ "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, },
{ "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, },
{ "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,},
- { "HD audio", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, },
+ { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, },
{ "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, },
{ NULL, 0, NULL, },
};
@@ -193,13 +203,20 @@ static const struct pci_class pci_interf
{ NULL, 0, NULL, },
};
-/* Semi-transparent PCI-toPCI bridge programming interface */
+/* Semi-transparent PCI-to-PCI bridge programming interface */
static const struct pci_class pci_interface_stpci[] = {
{ "primary side facing host", PCI_INTERFACE_STPCI_PRIMARY, NULL, },
{ "secondary side facing host", PCI_INTERFACE_STPCI_SECONDARY, NULL, },
{ NULL, 0, NULL, },
};
+/* Advanced Switching programming interface */
+static const struct pci_class pci_interface_advsw[] = {
+ { "custom interface", PCI_INTERFACE_ADVSW_CUSTOM, NULL, },
+ { "ASI-SIG", PCI_INTERFACE_ADVSW_ASISIG, NULL, },
+ { NULL, 0, NULL, },
+};
+
/* Subclasses */
static const struct pci_class pci_subclass_bridge[] = {
{ "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, },
@@ -215,6 +232,8 @@ static const struct pci_class pci_subcla
{ "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI,
pci_interface_stpci, },
{ "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, },
+ { "advanced switching", PCI_SUBCLASS_BRIDGE_ADVSW,
+ pci_interface_advsw, },
{ "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, },
{ NULL, 0, NULL, },
};
@@ -226,7 +245,7 @@ static const struct pci_class pci_subcla
/* Serial controller programming interface */
static const struct pci_class pci_interface_serial[] = {
- { "genric XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, },
+ { "generic XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, },
{ "16450-compat", PCI_INTERFACE_SERIAL_16450, NULL, },
{ "16550-compat", PCI_INTERFACE_SERIAL_16550, NULL, },
{ "16650-compat", PCI_INTERFACE_SERIAL_16650, NULL, },
@@ -241,8 +260,8 @@ static const struct pci_class pci_interf
{ "", PCI_INTERFACE_PARALLEL, NULL,},
{ "bi-directional", PCI_INTERFACE_PARALLEL_BIDIRECTIONAL, NULL,},
{ "ECP 1.X-compat", PCI_INTERFACE_PARALLEL_ECP1X, NULL,},
- { "IEEE1284", PCI_INTERFACE_PARALLEL_IEEE1284, NULL,},
- { "IEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,},
+ { "IEEE1284 controller", PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL, NULL,},
+ { "IEEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,},
{ NULL, 0, NULL,},
};
@@ -278,7 +297,7 @@ static const struct pci_class pci_subcla
/* PIC programming interface */
static const struct pci_class pci_interface_pic[] = {
- { "genric 8259", PCI_INTERFACE_PIC_8259, NULL, },
+ { "generic 8259", PCI_INTERFACE_PIC_8259, NULL, },
{ "ISA PIC", PCI_INTERFACE_PIC_ISA, NULL, },
{ "EISA PIC", PCI_INTERFACE_PIC_EISA, NULL, },
{ "IO APIC", PCI_INTERFACE_PIC_IOAPIC, NULL, },
@@ -288,7 +307,7 @@ static const struct pci_class pci_interf
/* DMA programming interface */
static const struct pci_class pci_interface_dma[] = {
- { "genric 8237", PCI_INTERFACE_DMA_8237, NULL, },
+ { "generic 8237", PCI_INTERFACE_DMA_8237, NULL, },
{ "ISA", PCI_INTERFACE_DMA_ISA, NULL, },
{ "EISA", PCI_INTERFACE_DMA_EISA, NULL, },
{ NULL, 0, NULL, },
@@ -296,9 +315,10 @@ static const struct pci_class pci_interf
/* Timer programming interface */
static const struct pci_class pci_interface_tmr[] = {
- { "genric 8254", PCI_INTERFACE_TIMER_8254, NULL, },
+ { "generic 8254", PCI_INTERFACE_TIMER_8254, NULL, },
{ "ISA", PCI_INTERFACE_TIMER_ISA, NULL, },
{ "EISA", PCI_INTERFACE_TIMER_EISA, NULL, },
+ { "HPET", PCI_INTERFACE_TIMER_HPET, NULL, },
{ NULL, 0, NULL, },
};
@@ -369,6 +389,7 @@ static const struct pci_class pci_subcla
{ "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, },
{ "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, },
{ "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, },
+ { "miscellaneous", PCI_SUBCLASS_PROCESSOR_MISC, NULL, },
{ NULL, 0, NULL, },
};
@@ -429,7 +450,7 @@ static const struct pci_class pci_subcla
*/
static const struct pci_class pci_subclass_wireless[] = {
{ "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, },
- { "Consumer IR", PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, },
+ { "Consumer IR",/*XXX*/ PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, },
{ "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, },
{ "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, },
{ "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, },
@@ -487,7 +508,7 @@ static const struct pci_class pci_subcla
*/
static const struct pci_class pci_subclass_dasp[] = {
{ "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, },
- { "Time and Frequency", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, },
+ { "performance counters", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, },
{ "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, },
{ "management", PCI_SUBCLASS_DASP_MGMT, NULL, },
{ "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, },
@@ -1011,6 +1032,20 @@ pci_conf_print_regs(const pcireg_t *regs
printf("\n");
}
+static void
+pci_conf_print_agp_cap(const pcireg_t *regs, int capoff)
+{
+ pcireg_t rval;
+
+ printf("\n AGP Capabilities Register\n");
+
+ rval = regs[o2i(capoff)];
+ printf(" Revision: %d.%d\n",
+ PCI_CAP_AGP_MAJOR(rval), PCI_CAP_AGP_MINOR(rval));
+
+ /* XXX need more */
+}
+
static const char *
pci_conf_print_pcipm_cap_aux(uint16_t caps)
{
@@ -1401,8 +1436,7 @@ pci_conf_print_pcie_cap(const pcireg_t *
printf("unknown\n");
break;
}
- if (check_slot && (reg & PCIE_XCAP_SI) != 0)
- printf(" Slot implemented\n");
+ onoff("Slot implemented", reg, PCIE_XCAP_SI);
printf(" Interrupt Message Number: %x\n",
(unsigned int)((reg & PCIE_XCAP_IRQ) >> 27));
@@ -1839,6 +1873,35 @@ pci_conf_print_pciaf_cap(const pcireg_t
onoff("Transaction Pending", reg, PCI_AFSR_TP);
}
+static struct {
+ pcireg_t cap;
+ const char *name;
+ void (*printfunc)(const pcireg_t *, int);
+} pci_captab[] = {
+ { PCI_CAP_RESERVED0, "reserved", NULL },
+ { PCI_CAP_PWRMGMT, "Power Management", pci_conf_print_pcipm_cap },
+ { PCI_CAP_AGP, "AGP", pci_conf_print_agp_cap },
+ { PCI_CAP_VPD, "VPD", NULL },
+ { PCI_CAP_SLOTID, "SlotID", NULL },
+ { PCI_CAP_MSI, "MSI", pci_conf_print_msi_cap },
+ { PCI_CAP_CPCI_HOTSWAP, "CompactPCI Hot-swapping", NULL },
+ { PCI_CAP_PCIX, "PCI-X", pci_conf_print_pcix_cap },
+ { PCI_CAP_LDT, "HyperTransport", NULL },
+ { PCI_CAP_VENDSPEC, "Vendor-specific",
+ pci_conf_print_vendspec_cap },
+ { PCI_CAP_DEBUGPORT, "Debug Port", pci_conf_print_debugport_cap },
+ { PCI_CAP_CPCI_RSRCCTL, "CompactPCI Resource Control", NULL },
+ { PCI_CAP_HOTPLUG, "Hot-Plug", NULL },
+ { PCI_CAP_SUBVENDOR, "Subsystem vendor ID",
+ pci_conf_print_subsystem_cap },
+ { PCI_CAP_AGP8, "AGP 8x", NULL },
+ { PCI_CAP_SECURE, "Secure Device", NULL },
+ { PCI_CAP_PCIEXPRESS, "PCI Express", pci_conf_print_pcie_cap },
+ { PCI_CAP_MSIX, "MSI-X", pci_conf_print_msix_cap },
+ { PCI_CAP_SATA, "SATA", NULL },
+ { PCI_CAP_PCIAF, "Advanced Features", pci_conf_print_pciaf_cap }
+};
+
static void
pci_conf_print_caplist(
#ifdef _KERNEL
@@ -1847,11 +1910,16 @@ pci_conf_print_caplist(
const pcireg_t *regs, int capoff)
{
int off;
+ pcireg_t foundcap;
pcireg_t rval;
- int pcie_off = -1, pcipm_off = -1, msi_off = -1, pcix_off = -1;
- int vendspec_off = -1, msix_off = -1;
- int debugport_off = -1, subsystem_off = -1, pciaf_off = -1;
+ bool foundtable[__arraycount(pci_captab)];
+ unsigned int i;
+
+ /* Clear table */
+ for (i = 0; i < __arraycount(pci_captab); i++)
+ foundtable[i] = false;
+ /* Print capability register's offset and the type first */
for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]);
off != 0;
off = PCI_CAPLIST_NEXT(regs[o2i(off)])) {
@@ -1859,113 +1927,39 @@ pci_conf_print_caplist(
printf(" Capability register at 0x%02x\n", off);
printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval));
- switch (PCI_CAPLIST_CAP(rval)) {
- case PCI_CAP_RESERVED0:
- printf("reserved");
- break;
- case PCI_CAP_PWRMGMT:
- printf("Power Management, rev. %s",
- pci_conf_print_pcipm_cap_pmrev(
- (rval >> 0) & 0x07));
- pcipm_off = off;
- break;
- case PCI_CAP_AGP:
- printf("AGP, rev. %d.%d",
- PCI_CAP_AGP_MAJOR(rval),
- PCI_CAP_AGP_MINOR(rval));
- break;
- case PCI_CAP_VPD:
- printf("VPD");
- break;
- case PCI_CAP_SLOTID:
- printf("SlotID");
- break;
- case PCI_CAP_MSI:
- printf("MSI");
- msi_off = off;
- break;
- case PCI_CAP_CPCI_HOTSWAP:
- printf("CompactPCI Hot-swapping");
- break;
- case PCI_CAP_PCIX:
- pcix_off = off;
- printf("PCI-X");
- break;
- case PCI_CAP_LDT:
- printf("LDT");
- break;
- case PCI_CAP_VENDSPEC:
- vendspec_off = off;
- printf("Vendor-specific");
- break;
- case PCI_CAP_DEBUGPORT:
- printf("Debug Port");
- debugport_off = off;
- break;
- case PCI_CAP_CPCI_RSRCCTL:
- printf("CompactPCI Resource Control");
- break;
- case PCI_CAP_HOTPLUG:
- printf("Hot-Plug");
- break;
- case PCI_CAP_SUBVENDOR:
- printf("Subsystem ID");
- subsystem_off = off;
- break;
- case PCI_CAP_AGP8:
- printf("AGP 8x");
- break;
- case PCI_CAP_SECURE:
- printf("Secure Device");
- break;
- case PCI_CAP_PCIEXPRESS:
- printf("PCI Express");
- pcie_off = off;
- break;
- case PCI_CAP_MSIX:
- printf("MSI-X");
- msix_off = off;
- break;
- case PCI_CAP_SATA:
- printf("SATA");
- break;
- case PCI_CAP_PCIAF:
- printf("Advanced Features");
- pciaf_off = off;
- break;
- default:
- printf("unknown");
+ foundcap = PCI_CAPLIST_CAP(rval);
+ if (foundcap < __arraycount(pci_captab)) {
+ printf("%s)\n", pci_captab[foundcap].name);
+ /* Mark as found */
+ foundtable[foundcap] = true;
+ } else
+ printf("unknown)\n");
+ }
+
+ /*
+ * And then, print the detail of each capability registers
+ * in capability value's order.
+ */
+ for (i = 0; i < __arraycount(pci_captab); i++) {
+ if (foundtable[i] == false)
+ continue;
+
+ /*
+ * The type was found. Search capability list again and
+ * print all capabilities that the capabiliy type is
+ * the same. This is required because some capabilities
+ * appear multiple times (e.g. HyperTransport capability).
+ */
+ for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]);
+ off != 0;
+ off = PCI_CAPLIST_NEXT(regs[o2i(off)])) {
+ rval = regs[o2i(off)];
+ foundcap = PCI_CAPLIST_CAP(rval);
+ if ((i == foundcap)
+ && (pci_captab[foundcap].printfunc != NULL))
+ pci_captab[foundcap].printfunc(regs, off);
}
- printf(")\n");
}
- if (pcipm_off != -1)
- pci_conf_print_pcipm_cap(regs, pcipm_off);
- /* XXX AGP */
- /* XXX VPD */
- /* XXX SLOTID */
- if (msi_off != -1)
- pci_conf_print_msi_cap(regs, msi_off);
- /* XXX CPCI_HOTSWAP */
- if (pcix_off != -1)
- pci_conf_print_pcix_cap(regs, pcix_off);
- /* XXX LDT */
- if (vendspec_off != -1)
- pci_conf_print_vendspec_cap(regs, vendspec_off);
- if (debugport_off != -1)
- pci_conf_print_debugport_cap(regs, debugport_off);
- /* XXX CPCI_RSRCCTL */
- /* XXX HOTPLUG */
- if (subsystem_off != -1)
- pci_conf_print_subsystem_cap(regs, subsystem_off);
- /* XXX AGP8 */
- /* XXX SECURE */
- if (pcie_off != -1)
- pci_conf_print_pcie_cap(regs, pcie_off);
- if (msix_off != -1)
- pci_conf_print_msix_cap(regs, msix_off);
- /* XXX SATA */
- if (pciaf_off != -1)
- pci_conf_print_pciaf_cap(regs, pciaf_off);
}
/* Print the Secondary Status Register. */
Index: src/sys/dev/pci/pcireg.h
diff -u src/sys/dev/pci/pcireg.h:1.95.2.1 src/sys/dev/pci/pcireg.h:1.95.2.2
--- src/sys/dev/pci/pcireg.h:1.95.2.1 Fri Dec 12 18:56:16 2014
+++ src/sys/dev/pci/pcireg.h Fri Dec 12 19:03:17 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: pcireg.h,v 1.95.2.1 2014/12/12 18:56:16 martin Exp $ */
+/* $NetBSD: pcireg.h,v 1.95.2.2 2014/12/12 19:03:17 martin Exp $ */
/*
* Copyright (c) 1995, 1996, 1999, 2000
@@ -180,9 +180,13 @@ typedef u_int8_t pci_revision_t;
#define PCI_INTERFACE_ATA_SINGLEDMA 0x20
#define PCI_INTERFACE_ATA_CHAINEDDMA 0x30
#define PCI_SUBCLASS_MASS_STORAGE_SATA 0x06
+#define PCI_INTERFACE_SATA_VND 0x00
#define PCI_INTERFACE_SATA_AHCI10 0x01
+#define PCI_INTERFACE_SATA_SSBI 0x02
#define PCI_SUBCLASS_MASS_STORAGE_SAS 0x07
#define PCI_SUBCLASS_MASS_STORAGE_NVM 0x08
+#define PCI_INTERFACE_NVM_VND 0x00
+#define PCI_INTERFACE_NVM_NVMHCI10 0x01
#define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80
/* 0x02 network subclasses */
@@ -220,7 +224,7 @@ typedef u_int8_t pci_revision_t;
#define PCI_SUBCLASS_BRIDGE_HOST 0x00
#define PCI_SUBCLASS_BRIDGE_ISA 0x01
#define PCI_SUBCLASS_BRIDGE_EISA 0x02
-#define PCI_SUBCLASS_BRIDGE_MC 0x03 /* XXX _MCA? */
+#define PCI_SUBCLASS_BRIDGE_MC 0x03 /* XXX _MCA */
#define PCI_SUBCLASS_BRIDGE_PCI 0x04
#define PCI_INTERFACE_BRIDGE_PCI_PCI 0x00
#define PCI_INTERFACE_BRIDGE_PCI_SUBDEC 0x01
@@ -228,10 +232,14 @@ typedef u_int8_t pci_revision_t;
#define PCI_SUBCLASS_BRIDGE_NUBUS 0x06
#define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07
#define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08
+ /* bit0 == 0 ? "transparent mode" : "endpoint mode" */
#define PCI_SUBCLASS_BRIDGE_STPCI 0x09
-#define PCI_SUBCLASS_BRIDGE_INFINIBAND 0x0a
#define PCI_INTERFACE_STPCI_PRIMARY 0x40
#define PCI_INTERFACE_STPCI_SECONDARY 0x80
+#define PCI_SUBCLASS_BRIDGE_INFINIBAND 0x0a
+#define PCI_SUBCLASS_BRIDGE_ADVSW 0x0b
+#define PCI_INTERFACE_ADVSW_CUSTOM 0x00
+#define PCI_INTERFACE_ADVSW_ASISIG 0x01
#define PCI_SUBCLASS_BRIDGE_MISC 0x80
/* 0x07 communications subclasses */
@@ -247,7 +255,7 @@ typedef u_int8_t pci_revision_t;
#define PCI_INTERFACE_PARALLEL 0x00
#define PCI_INTERFACE_PARALLEL_BIDIRECTIONAL 0x01
#define PCI_INTERFACE_PARALLEL_ECP1X 0x02
-#define PCI_INTERFACE_PARALLEL_IEEE1284 0x03
+#define PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL 0x03
#define PCI_INTERFACE_PARALLEL_IEEE1284_TGT 0xfe
#define PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL 0x02
#define PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03
@@ -275,12 +283,13 @@ typedef u_int8_t pci_revision_t;
#define PCI_INTERFACE_TIMER_8254 0x00
#define PCI_INTERFACE_TIMER_ISA 0x01
#define PCI_INTERFACE_TIMER_EISA 0x02
+#define PCI_INTERFACE_TIMER_HPET 0x03
#define PCI_SUBCLASS_SYSTEM_RTC 0x03
#define PCI_INTERFACE_RTC_GENERIC 0x00
#define PCI_INTERFACE_RTC_ISA 0x01
#define PCI_SUBCLASS_SYSTEM_PCIHOTPLUG 0x04
#define PCI_SUBCLASS_SYSTEM_SDHC 0x05
-#define PCI_SUBCLASS_SYSTEM_IOMMU 0x06
+#define PCI_SUBCLASS_SYSTEM_IOMMU 0x06 /* or RCEC in old spec */
#define PCI_SUBCLASS_SYSTEM_RCEC 0x07
#define PCI_SUBCLASS_SYSTEM_MISC 0x80
@@ -306,6 +315,7 @@ typedef u_int8_t pci_revision_t;
#define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20
#define PCI_SUBCLASS_PROCESSOR_MIPS 0x30
#define PCI_SUBCLASS_PROCESSOR_COPROC 0x40
+#define PCI_SUBCLASS_PROCESSOR_MISC 0x80
/* 0x0c serial bus subclasses */
#define PCI_SUBCLASS_SERIALBUS_FIREWIRE 0x00
@@ -334,6 +344,8 @@ typedef u_int8_t pci_revision_t;
/* 0x0d wireless subclasses */
#define PCI_SUBCLASS_WIRELESS_IRDA 0x00
#define PCI_SUBCLASS_WIRELESS_CONSUMERIR 0x01
+#define PCI_INTERFACE_CONSUMERIR 0x00
+#define PCI_INTERFACE_UWB 0x10
#define PCI_SUBCLASS_WIRELESS_RF 0x10
#define PCI_SUBCLASS_WIRELESS_BLUETOOTH 0x11
#define PCI_SUBCLASS_WIRELESS_BROADBAND 0x12
@@ -362,7 +374,7 @@ typedef u_int8_t pci_revision_t;
/* 0x11 data acquisition and signal processing subclasses */
#define PCI_SUBCLASS_DASP_DPIO 0x00
-#define PCI_SUBCLASS_DASP_TIMEFREQ 0x01
+#define PCI_SUBCLASS_DASP_TIMEFREQ 0x01 /* performance counters */
#define PCI_SUBCLASS_DASP_SYNC 0x10
#define PCI_SUBCLASS_DASP_MGMT 0x20
#define PCI_SUBCLASS_DASP_MISC 0x80
@@ -518,7 +530,7 @@ typedef u_int8_t pci_revision_t;
#define PCI_CAP_MSI 0x05
#define PCI_CAP_CPCI_HOTSWAP 0x06
#define PCI_CAP_PCIX 0x07
-#define PCI_CAP_LDT 0x08
+#define PCI_CAP_LDT 0x08 /* HyperTransport */
#define PCI_CAP_VENDSPEC 0x09
#define PCI_CAP_DEBUGPORT 0x0a
#define PCI_CAP_CPCI_RSRCCTL 0x0b
@@ -763,6 +775,35 @@ typedef u_int8_t pci_revision_t;
* HyperTransport
*/
+#define PCI_HT_CMD 0x00 /* Capability List & Command Register */
+#define PCI_HT_CMD_MASK __BITS(31, 16)
+#define PCI_HT_MSI_ENABLED __BIT(16)
+#define PCI_HT_MSI_FIXED __BIT(17)
+#define PCI_HT_CAP(cr) ((((cr) >> 27) < 0x08) ? \
+ (((cr) >> 27) & 0x1c) : (((cr) >> 27) & 0x1f))
+#define PCI_HT_CAPMASK __BITS(31, 27)
+#define PCI_HT_CAP_SLAVE __SHIFTIN(0b00000, PCI_HT_CAPMASK) /* 000xx */
+#define PCI_HT_CAP_HOST __SHIFTIN(0b00100, PCI_HT_CAPMASK) /* 001xx */
+#define PCI_HT_CAP_SWITCH __SHIFTIN(0b01000, PCI_HT_CAPMASK)
+#define PCI_HT_CAP_INTERRUPT __SHIFTIN(0b10000, PCI_HT_CAPMASK)
+#define PCI_HT_CAP_REVID __SHIFTIN(0b10001, PCI_HT_CAPMASK)
+#define PCI_HT_CAP_UNITID_CLUMP __SHIFTIN(0b10010, PCI_HT_CAPMASK)
+#define PCI_HT_CAP_EXTCNFSPACE __SHIFTIN(0b10011, PCI_HT_CAPMASK)
+#define PCI_HT_CAP_ADDRMAP __SHIFTIN(0b10100, PCI_HT_CAPMASK)
+#define PCI_HT_CAP_MSIMAP __SHIFTIN(0b10101, PCI_HT_CAPMASK)
+#define PCI_HT_CAP_DIRECTROUTE __SHIFTIN(0b10110, PCI_HT_CAPMASK)
+#define PCI_HT_CAP_VCSET __SHIFTIN(0b10111, PCI_HT_CAPMASK)
+#define PCI_HT_CAP_RETRYMODE __SHIFTIN(0b11000, PCI_HT_CAPMASK)
+#define PCI_HT_CAP_X86ENCODE __SHIFTIN(0b11001, PCI_HT_CAPMASK)
+#define PCI_HT_CAP_GEN3 __SHIFTIN(0b11010, PCI_HT_CAPMASK)
+#define PCI_HT_CAP_FLE __SHIFTIN(0b11011, PCI_HT_CAPMASK)
+#define PCI_HT_CAP_PM __SHIFTIN(0b11100, PCI_HT_CAPMASK)
+#define PCI_HT_CAP_HIGHNODECNT __SHIFTIN(0b11101, PCI_HT_CAPMASK)
+
+#define PCI_HT_MSI_ADDR_LO 0x04
+#define PCI_HT_MSI_ADDR_HI 0x08
+#define PCI_HT_MSI_FIXED_ADDR 0xfee00000UL
+
/*
* Capability ID: 0x09
* Vendor Specific
