Module Name: src
Committed By: jmcneill
Date: Sun Dec 21 17:37:40 UTC 2014
Modified Files:
src/sys/arch/arm/allwinner: awin_reg.h
Log Message:
add some A80 daudio and display regs
To generate a diff of this commit:
cvs rdiff -u -r1.74 -r1.75 src/sys/arch/arm/allwinner/awin_reg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/allwinner/awin_reg.h
diff -u src/sys/arch/arm/allwinner/awin_reg.h:1.74 src/sys/arch/arm/allwinner/awin_reg.h:1.75
--- src/sys/arch/arm/allwinner/awin_reg.h:1.74 Sat Dec 20 16:22:17 2014
+++ src/sys/arch/arm/allwinner/awin_reg.h Sun Dec 21 17:37:40 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: awin_reg.h,v 1.74 2014/12/20 16:22:17 skrll Exp $ */
+/* $NetBSD: awin_reg.h,v 1.75 2014/12/21 17:37:40 jmcneill Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -2674,6 +2674,11 @@ struct awin_a31_dma_desc {
* These offsets are relative to AWIN_CORE_PBASE
*/
#define AWIN_A80_SDMMC_COMM_OFFSET 0x00013000
+#define AWIN_A80_DE_BE0_OFFSET 0x01600000
+#define AWIN_A80_DE_BE1_OFFSET 0x01640000
+#define AWIN_A80_DE_BE2_OFFSET 0x01680000
+#define AWIN_A80_LCD0_OFFSET 0x02000000
+#define AWIN_A80_HDMI_OFFSET 0x02100000
#define AWIN_A80_CCU_OFFSET 0x04400000
#define AWIN_A80_CCU_SCLK_OFFSET 0x04400400
#define AWIN_A80_PIO_OFFSET 0x04400800
@@ -2716,6 +2721,7 @@ struct awin_a31_dma_desc {
#define AWIN_A80_CIR_OFFSET 0x00002000
#define AWIN_A80_RPIO_OFFSET 0x00002c00
#define AWIN_A80_RSB_OFFSET 0x00003400
+#define AWIN_A80_DAUDIO1_OFFSET 0x00006000
#define AWIN_A80_SDMMC_COMM_SDC_RESET_SW __BIT(18)
#define AWIN_A80_SDMMC_COMM_SDC_CLOCK_SW __BIT(16)
@@ -2739,6 +2745,13 @@ struct awin_a31_dma_desc {
#define AWIN_A80_CCU_PLL_CxCPUX_FACTOR_N __BITS(15,8)
#define AWIN_A80_CCU_PLL_CxCPUX_POSTDIV_M __BITS(1,0)
+#define AWIN_A80_CCU_PLL_AUDIO_ENABLE __BIT(31)
+#define AWIN_A80_CCU_PLL_AUDIO_SDM_ENABLE __BIT(24)
+#define AWIN_A80_CCU_PLL_AUDIO_OUTPUT_DIV __BIT(18)
+#define AWIN_A80_CCU_PLL_AUDIO_INPUT_DIV __BIT(16)
+#define AWIN_A80_CCU_PLL_AUDIO_FACTOR_N __BITS(15,8)
+#define AWIN_A80_CCU_PLL_AUDIO_POSTDIV_P __BITS(5,0)
+
#define AWIN_A80_CCU_PLL_PERIPH0_ENABLE __BIT(31)
#define AWIN_A80_CCU_PLL_PERIPH0_SDM_ENABLE __BIT(24)
#define AWIN_A80_CCU_PLL_PERIPH0_OUTPUT_DIV __BIT(18)
@@ -2795,6 +2808,8 @@ struct awin_a31_dma_desc {
#define AWIN_A80_CCU_SCLK_SDMMC_OUTPUT_CLK_PHASE_CTR __BITS(10,8)
#define AWIN_A80_CCU_SCLK_SDMMC_CLK_DIV_RATIO_M __BITS(3,0)
+#define AWIN_A80_CCU_SCLK_DAUDIO_SCLK_GATING __BIT(31)
+
#define AWIN_A80_USBPHY_HCI_SCR_REG 0x0000
#define AWIN_A80_USBPHY_HCI_PCR_REG 0x0004
@@ -2822,6 +2837,8 @@ struct awin_a31_dma_desc {
#define AWIN_A80_RPRCM_APB0_GATING_REG 0x0028
#define AWIN_A80_RPRCM_CIR_CLK_REG 0x0054
+#define AWIN_A80_RPRCM_DAUDIO0_CLK_REG 0x0058
+#define AWIN_A80_RPRCM_DAUDIO1_CLK_REG 0x005c
#define AWIN_A80_RPRCM_APB0_RST_REG 0x00b0
#define AWIN_A80_RPRCM_CLUSTER0_RST_REG 0x0004
@@ -2839,7 +2856,11 @@ struct awin_a31_dma_desc {
#define AWIN_A80_RPRCM_PRIVATE_REG 0x0164
#define AWIN_A80_RPRCM_APB0_GATING_CIR __BIT(1)
+#define AWIN_A80_RPRCM_APB0_GATING_DAUDIO1 __BIT(18)
+#define AWIN_A80_RPRCM_APB0_GATING_DAUDIO0 __BIT(17)
#define AWIN_A80_RPRCM_APB0_RST_CIR __BIT(1)
+#define AWIN_A80_RPRCM_APB0_RST_DAUDIO1 __BIT(18)
+#define AWIN_A80_RPRCM_APB0_RST_DAUDIO0 __BIT(17)
#define AWIN_A80_RCPUCFG_CLUSTER0_RST_REG 0x0080
#define AWIN_A80_RCPUCFG_CLUSTER1_RST_REG 0x0084
@@ -2900,6 +2921,8 @@ struct awin_a31_dma_desc {
#define AWIN_A80_PIO_PL_CIR_PINS 0x00000040 /* PL pin 6 */
#define AWIN_A80_PIO_PM_PINS 16
+#define AWIN_A80_PIO_PM_DAUDIO1_FUNC 3
+#define AWIN_A80_PIO_PM_DAUDIO1_PINS 0x00007cf0 /* PM pins 14-10,7-4 */
#define AWIN_A80_PIO_PN_PINS 2
