Module Name: src
Committed By: nonaka
Date: Sat Dec 27 16:19:34 UTC 2014
Modified Files:
src/sys/arch/evbppc/conf: files.mpc85xx
src/sys/arch/evbppc/mpc85xx: machdep.c
src/sys/arch/powerpc/booke: e500_intr.c
src/sys/arch/powerpc/booke/dev: pq3gpio.c
src/sys/arch/powerpc/booke/pci: pq3pci.c
src/sys/arch/powerpc/include/booke: e500reg.h openpicreg.h
Log Message:
Preliminary support for P1023.
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/evbppc/conf/files.mpc85xx
cvs rdiff -u -r1.36 -r1.37 src/sys/arch/evbppc/mpc85xx/machdep.c
cvs rdiff -u -r1.27 -r1.28 src/sys/arch/powerpc/booke/e500_intr.c
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/powerpc/booke/dev/pq3gpio.c
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/powerpc/booke/pci/pq3pci.c
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/powerpc/include/booke/e500reg.h
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/powerpc/include/booke/openpicreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/evbppc/conf/files.mpc85xx
diff -u src/sys/arch/evbppc/conf/files.mpc85xx:1.9 src/sys/arch/evbppc/conf/files.mpc85xx:1.10
--- src/sys/arch/evbppc/conf/files.mpc85xx:1.9 Sun Jul 15 08:44:56 2012
+++ src/sys/arch/evbppc/conf/files.mpc85xx Sat Dec 27 16:19:33 2014
@@ -1,9 +1,9 @@
-# $NetBSD: files.mpc85xx,v 1.9 2012/07/15 08:44:56 matt Exp $
+# $NetBSD: files.mpc85xx,v 1.10 2014/12/27 16:19:33 nonaka Exp $
#
# mpc85xx-specific configuration info
defflag opt_mpc85xx.h MPC8536 MPC8544 MPC8548 MPC8555 MPC8568 MPC8572
- P1025 P2020 CADMUS PIXIS E500_WDOG_STACK
+ P1023 P1025 P2020 CADMUS PIXIS E500_WDOG_STACK
defparam opt_mpc85xx.h SYS_CLK MEMSIZE
file arch/evbppc/mpc85xx/autoconf.c
Index: src/sys/arch/evbppc/mpc85xx/machdep.c
diff -u src/sys/arch/evbppc/mpc85xx/machdep.c:1.36 src/sys/arch/evbppc/mpc85xx/machdep.c:1.37
--- src/sys/arch/evbppc/mpc85xx/machdep.c:1.36 Fri Dec 19 04:31:41 2014
+++ src/sys/arch/evbppc/mpc85xx/machdep.c Sat Dec 27 16:19:33 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: machdep.c,v 1.36 2014/12/19 04:31:41 nonaka Exp $ */
+/* $NetBSD: machdep.c,v 1.37 2014/12/27 16:19:33 nonaka Exp $ */
/*-
* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -207,14 +207,15 @@ static struct consdev e500_earlycons = {
static const struct cpunode_locators mpc8548_cpunode_locs[] = {
{ "cpu", 0, 0, 0, 0, { 0 }, 0, /* not a real device */
{ 0xffff, SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16,
- SVR_P1025v1 >> 16 } },
-#if defined(MPC8572) || defined(P2020) || defined(P1025)
+ SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } },
+#if defined(MPC8572) || defined(P2020) || defined(P1025) \
+ || defined(P1023)
{ "cpu", 0, 0, 1, 0, { 0 }, 0, /* not a real device */
{ SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16,
- SVR_P1025v1 >> 16 } },
+ SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } },
{ "cpu", 0, 0, 2, 0, { 0 }, 0, /* not a real device */
{ SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16,
- SVR_P1025v1 >> 16 } },
+ SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } },
#endif
{ "wdog" }, /* not a real device */
{ "duart", DUART1_BASE, 2*DUART_SIZE, 0,
@@ -223,7 +224,7 @@ static const struct cpunode_locators mpc
{ "tsec", ETSEC1_BASE, ETSEC_SIZE, 1,
3, { ISOURCE_ETSEC1_TX, ISOURCE_ETSEC1_RX, ISOURCE_ETSEC1_ERR },
1 + ilog2(DEVDISR_TSEC1),
- { 0xffff, SVR_P1025v1 >> 16 } },
+ { 0xffff, SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } },
#if defined(P1025)
{ "mdio", ETSEC1_BASE, ETSEC_SIZE, 1,
0, { },
@@ -366,30 +367,33 @@ static const struct cpunode_locators mpc
1 + ilog2(DEVDISR_PCI2),
{ SVR_MPC8548v1 >> 16 }, },
#endif
-#if defined(MPC8572) || defined(P1025) || defined(P2020)
+#if defined(MPC8572) || defined(P1025) || defined(P2020) \
+ || defined(P1023)
{ "pcie", PCIE1_BASE, PCI_SIZE, 1,
1, { ISOURCE_PCIEX },
1 + ilog2(DEVDISR_PCIE),
{ SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16,
- SVR_P1025v1 >> 16 } },
+ SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } },
{ "pcie", PCIE2_MPC8572_BASE, PCI_SIZE, 2,
1, { ISOURCE_PCIEX2 },
1 + ilog2(DEVDISR_PCIE2),
{ SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16,
- SVR_P1025v1 >> 16 } },
+ SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } },
#endif
-#if defined(MPC8572) || defined(P2020)
+#if defined(MPC8572) || defined(P2020) || defined(_P1023)
{ "pcie", PCIE3_MPC8572_BASE, PCI_SIZE, 3,
1, { ISOURCE_PCIEX3_MPC8572 },
1 + ilog2(DEVDISR_PCIE3),
- { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, } },
+ { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16,
+ SVR_P1023v1 >> 16 } },
#endif
-#if defined(MPC8536) || defined(P1025) || defined(P2020)
+#if defined(MPC8536) || defined(P1025) || defined(P2020) \
+ || defined(P1023)
{ "ehci", USB1_BASE, USB_SIZE, 1,
1, { ISOURCE_USB1 },
1 + ilog2(DEVDISR_USB1),
{ SVR_MPC8536v1 >> 16, SVR_P2020v2 >> 16,
- SVR_P1025v1 >> 16 } },
+ SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } },
#endif
#ifdef MPC8536
{ "ehci", USB2_BASE, USB_SIZE, 2,
@@ -417,11 +421,14 @@ static const struct cpunode_locators mpc
1 + ilog2(DEVDISR_ESDHC_12),
{ SVR_MPC8536v1 >> 16 }, },
#endif
-#if defined(P1025) || defined(P2020)
+#if defined(P1025) || defined(P2020) || defined(P1023)
{ "spi", SPI_BASE, SPI_SIZE, 0,
1, { ISOURCE_SPI },
1 + ilog2(DEVDISR_SPI_28),
- { SVR_P2020v2 >> 16, SVR_P1025v1 >> 16 }, },
+ { SVR_P2020v2 >> 16, SVR_P1025v1 >> 16,
+ SVR_P1023v1 >> 16 }, },
+#endif
+#if defined(P1025) || defined(P2020)
{ "sdhc", ESDHC_BASE, ESDHC_SIZE, 0,
1, { ISOURCE_ESDHC },
1 + ilog2(DEVDISR_ESDHC_10),
@@ -681,6 +688,7 @@ getsvr(void)
case SVR_MPC8541v1 >> 16: return SVR_MPC8555v1 >> 16;
case SVR_P2010v2 >> 16: return SVR_P2020v2 >> 16;
case SVR_P1016v1 >> 16: return SVR_P1025v1 >> 16;
+ case SVR_P1017v1 >> 16: return SVR_P1023v1 >> 16;
default: return svr;
}
}
@@ -705,6 +713,8 @@ socname(uint32_t svr)
case SVR_P2020v2 >> 8: return "P2020";
case SVR_P2010v2 >> 8: return "P2010";
case SVR_P1016v1 >> 8: return "P1016";
+ case SVR_P1017v1 >> 8: return "P1017";
+ case SVR_P1023v1 >> 8: return "P1023";
case SVR_P1025v1 >> 8: return "P1025";
default:
panic("%s: unknown SVR %#x", __func__, svr);
@@ -1490,11 +1500,13 @@ cpu_startup(void)
break;
#endif
#if defined(MPC8544) || defined(MPC8572) || defined(MPC8536) \
- || defined(P1025) || defined(P2020)
+ || defined(P1025) || defined(P2020) || defined(P1023)
case SVR_MPC8536v1 >> 16:
case SVR_MPC8544v1 >> 16:
case SVR_MPC8572v1 >> 16:
case SVR_P1016v1 >> 16:
+ case SVR_P1017v1 >> 16:
+ case SVR_P1023v1 >> 16:
case SVR_P2010v2 >> 16:
case SVR_P2020v2 >> 16:
mpc85xx_pci_setup("pcie3-interrupt-map", 0x001800, IST_LEVEL,
Index: src/sys/arch/powerpc/booke/e500_intr.c
diff -u src/sys/arch/powerpc/booke/e500_intr.c:1.27 src/sys/arch/powerpc/booke/e500_intr.c:1.28
--- src/sys/arch/powerpc/booke/e500_intr.c:1.27 Sat Dec 20 17:55:07 2014
+++ src/sys/arch/powerpc/booke/e500_intr.c Sat Dec 27 16:19:33 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: e500_intr.c,v 1.27 2014/12/20 17:55:07 nonaka Exp $ */
+/* $NetBSD: e500_intr.c,v 1.28 2014/12/27 16:19:33 nonaka Exp $ */
/*-
* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -39,7 +39,7 @@
#define __INTR_PRIVATE
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: e500_intr.c,v 1.27 2014/12/20 17:55:07 nonaka Exp $");
+__KERNEL_RCSID(0, "$NetBSD: e500_intr.c,v 1.28 2014/12/27 16:19:33 nonaka Exp $");
#include <sys/param.h>
#include <sys/proc.h>
@@ -360,6 +360,29 @@ const struct e500_intr_name p20x0_onchip
INTR_INFO_DECL(p20x0, P20x0);
#endif
+#ifdef P1023
+#define p1023_external_intr_names default_external_intr_names
+const struct e500_intr_name p1023_onchip_intr_names[] = {
+ { ISOURCE_FMAN, "fman" },
+ { ISOURCE_MDIO, "mdio" },
+ { ISOURCE_QMAN0, "qman0" },
+ { ISOURCE_BMAN0, "bman0" },
+ { ISOURCE_QMAN1, "qman1" },
+ { ISOURCE_BMAN1, "bman1" },
+ { ISOURCE_QMAN2, "qman2" },
+ { ISOURCE_BMAN2, "bman2" },
+ { ISOURCE_SECURITY2_P1023, "sec2" },
+ { ISOURCE_SEC_GENERAL, "sec-general" },
+ { ISOURCE_DMA2_CHAN1, "dma2-chan1" },
+ { ISOURCE_DMA2_CHAN2, "dma2-chan2" },
+ { ISOURCE_DMA2_CHAN3, "dma2-chan3" },
+ { ISOURCE_DMA2_CHAN4, "dma2-chan4" },
+ { 0, "" },
+};
+
+INTR_INFO_DECL(p1023, P1023);
+#endif
+
static const char ist_names[][12] = {
[IST_NONE] = "none",
[IST_EDGE] = "edge",
@@ -1048,6 +1071,12 @@ e500_intr_init(void)
*ii = mpc8572_intr_info;
break;
#endif
+#ifdef P1023
+ case SVR_P1017v1 >> 16:
+ case SVR_P1023v1 >> 16:
+ *ii = p1023_intr_info;
+ break;
+#endif
#ifdef P1025
case SVR_P1016v1 >> 16:
case SVR_P1025v1 >> 16:
Index: src/sys/arch/powerpc/booke/dev/pq3gpio.c
diff -u src/sys/arch/powerpc/booke/dev/pq3gpio.c:1.10 src/sys/arch/powerpc/booke/dev/pq3gpio.c:1.11
--- src/sys/arch/powerpc/booke/dev/pq3gpio.c:1.10 Sat Dec 20 18:03:17 2014
+++ src/sys/arch/powerpc/booke/dev/pq3gpio.c Sat Dec 27 16:19:33 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: pq3gpio.c,v 1.10 2014/12/20 18:03:17 nonaka Exp $ */
+/* $NetBSD: pq3gpio.c,v 1.11 2014/12/27 16:19:33 nonaka Exp $ */
/*-
* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -41,7 +41,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pq3gpio.c,v 1.10 2014/12/20 18:03:17 nonaka Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pq3gpio.c,v 1.11 2014/12/27 16:19:33 nonaka Exp $");
#include <sys/param.h>
#include <sys/cpu.h>
@@ -161,9 +161,9 @@ pq3gpio_pin_ctl(void *v, int num, int ct
}
#endif
-#if defined(MPC8536) || defined(P2020)
+#if defined(MPC8536) || defined(P2020) || defined(P1023)
/*
- * MPC8536 / P20x0 have controllable input/output pins
+ * MPC8536 / P20x0 / P1023 have controllable input/output pins
*/
static void
pq3gpio_pin_ctl(void *v, int num, int ctl)
@@ -465,6 +465,43 @@ pq3gpio_p20x0_attach(device_t self, bus_
}
#endif /* P2020 */
+#ifdef P1023
+static void
+pq3gpio_p1023_attach(device_t self, bus_space_tag_t bst,
+ bus_space_handle_t bsh, u_int svr)
+{
+ static const uint32_t gpio2pmuxcr2_map[][3] = {
+ { __PPCBITS( 0, 1), __PPCBITS( 0, 1), 0 }, /* GPIO_1 */
+ { __PPCBIT(2), __PPCBITS( 2, 3), 0 }, /* GPUO_2 */
+ { __PPCBITS( 4, 5), __PPCBITS( 4, 5), 0 }, /* GPUO_3 */
+ { __PPCBITS( 6, 7), __PPCBITS( 6, 7), 0 }, /* GPUO_4 */
+ { __PPCBITS( 8, 9), __PPCBITS( 8, 9), 0 }, /* GPUO_5 */
+ { __PPCBITS(10,11), __PPCBITS(10,11), 0 }, /* GPUO_6 */
+ { __PPCBITS(12,13), __PPCBITS(12,13), 0 }, /* GPUO_7 */
+ { __PPCBITS(14,15), __PPCBITS(14,15), 0 }, /* GPUO_8 */
+ { __PPCBIT(3), __PPCBITS(18,19), 0 }, /* GPUO_9 */
+ };
+
+ uint32_t pinmask = 0xffff0000; /* assume all bits are valid */
+ size_t pincnt = 16;
+ const uint32_t pmuxcr2 = cpu_read_4(GLOBAL_BASE + PMUXCR2);
+ for (size_t i = 0; i < __arraycount(gpio2pmuxcr2_map); i++) {
+ const uint32_t *map = gpio2pmuxcr2_map[i];
+ if ((pmuxcr2 & map[1]) != map[2]) {
+ pinmask &= ~map[0];
+ pincnt--;
+ }
+ }
+
+ /*
+ * Create GPIO pin groups
+ */
+ aprint_normal_dev(self, "%zu input/output/opendrain pins\n", pincnt);
+ pq3gpio_group_create(self, bst, bsh, GPDAT, pinmask,
+ GPIO_PIN_INPUT|GPIO_PIN_OUTPUT|GPIO_PIN_OPENDRAIN, pq3gpio_pin_ctl);
+}
+#endif /* P1023 */
+
static const struct pq3gpio_svr_info {
uint16_t si_svr;
void (*si_attach)(device_t, bus_space_tag_t, bus_space_handle_t, u_int);
@@ -495,6 +532,10 @@ static const struct pq3gpio_svr_info {
{ SVR_P2020v2 >> 16, pq3gpio_p20x0_attach,
GPIO_BASE, GPIO_SIZE },
#endif
+#ifdef P1023
+ { SVR_P1023v1 >> 16, pq3gpio_p1023_attach,
+ GPIO_BASE, GPIO_SIZE },
+#endif
};
void
Index: src/sys/arch/powerpc/booke/pci/pq3pci.c
diff -u src/sys/arch/powerpc/booke/pci/pq3pci.c:1.19 src/sys/arch/powerpc/booke/pci/pq3pci.c:1.20
--- src/sys/arch/powerpc/booke/pci/pq3pci.c:1.19 Sat Dec 20 18:03:17 2014
+++ src/sys/arch/powerpc/booke/pci/pq3pci.c Sat Dec 27 16:19:33 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: pq3pci.c,v 1.19 2014/12/20 18:03:17 nonaka Exp $ */
+/* $NetBSD: pq3pci.c,v 1.20 2014/12/27 16:19:33 nonaka Exp $ */
/*-
* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -44,7 +44,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pq3pci.c,v 1.19 2014/12/20 18:03:17 nonaka Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pq3pci.c,v 1.20 2014/12/27 16:19:33 nonaka Exp $");
#include <sys/param.h>
#include <sys/device.h>
@@ -92,6 +92,11 @@ __KERNEL_RCSID(0, "$NetBSD: pq3pci.c,v 1
__SHIFTIN(field##_##P20x0##_##value, PORDEVSR_##field), result), \
TRUTH_ENCODE(SVR_P1016v1, inst, PORDEVSR_##field, \
__SHIFTIN(field##_##P20x0##_##value, PORDEVSR_##field), result)
+#define PORDEVSR_P1023_TRUTH_ENCODE(inst, field, value, result) \
+ TRUTH_ENCODE(SVR_P1023v1, inst, PORDEVSR_##field, \
+ __SHIFTIN(field##_##value, PORDEVSR_##field), result), \
+ TRUTH_ENCODE(SVR_P1017v1, inst, PORDEVSR_##field, \
+ __SHIFTIN(field##_##value, PORDEVSR_##field), result)
#define PORDEVSR_TRUTH_ENCODE(svr, inst, field, value, result) \
TRUTH_ENCODE(svr, inst, PORDEVSR_##field, \
@@ -171,6 +176,21 @@ const struct e500_truthtab pq3pci_pcie_l
PORDEVSR_P1025_TRUTH_ENCODE(2, IOSEL, PCIE12_X1_SGMII23, 1),
#endif
+
+#ifdef P1023
+ PORDEVSR_P1023_TRUTH_ENCODE(1, IOSEL_P1023, PCIE12_X1, 1),
+ PORDEVSR_P1023_TRUTH_ENCODE(1, IOSEL_P1023, PCIE123_X1, 1),
+ PORDEVSR_P1023_TRUTH_ENCODE(1, IOSEL_P1023, PCIE123_X1_SGMII2, 1),
+ PORDEVSR_P1023_TRUTH_ENCODE(1, IOSEL_P1023, PCIE12_X1_SGMII12, 1),
+
+ PORDEVSR_P1023_TRUTH_ENCODE(2, IOSEL_P1023, PCIE12_X1, 1),
+ PORDEVSR_P1023_TRUTH_ENCODE(2, IOSEL_P1023, PCIE123_X1, 1),
+ PORDEVSR_P1023_TRUTH_ENCODE(2, IOSEL_P1023, PCIE123_X1_SGMII2, 1),
+ PORDEVSR_P1023_TRUTH_ENCODE(2, IOSEL_P1023, PCIE12_X1_SGMII12, 1),
+
+ PORDEVSR_P1023_TRUTH_ENCODE(3, IOSEL_P1023, PCIE123_X1, 1),
+ PORDEVSR_P1023_TRUTH_ENCODE(3, IOSEL_P1023, PCIE123_X1_SGMII2, 1),
+#endif
};
static const struct e500_truthtab pq3pci_pci_pcix[] = {
Index: src/sys/arch/powerpc/include/booke/e500reg.h
diff -u src/sys/arch/powerpc/include/booke/e500reg.h:1.14 src/sys/arch/powerpc/include/booke/e500reg.h:1.15
--- src/sys/arch/powerpc/include/booke/e500reg.h:1.14 Thu Jul 26 18:41:32 2012
+++ src/sys/arch/powerpc/include/booke/e500reg.h Sat Dec 27 16:19:33 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: e500reg.h,v 1.14 2012/07/26 18:41:32 matt Exp $ */
+/* $NetBSD: e500reg.h,v 1.15 2014/12/27 16:19:33 nonaka Exp $ */
/*-
* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -394,6 +394,11 @@
#define PORDEVSR_PCI1 __PPCBIT(8)
#define PCI1_PCIX 0
#define PCI1_PCI1 1
+#define PORDEVSR_IOSEL_P1023 __PPCBITS(9,10)
+#define IOSEL_P1023_PCIE12_X1 0
+#define IOSEL_P1023_PCIE123_X1 1
+#define IOSEL_P1023_PCIE123_X1_SGMII2 2
+#define IOSEL_P1023_PCIE12_X1_SGMII12 3
#define PORDEVSR_IOSEL __PPCBITS(9,12)
#define IOSEL_MPC8536_OFF 0x01
#define IOSEL_MPC8536_PCIE1_X4 0x02
@@ -496,11 +501,16 @@
#define PMUXCR_DMA1 __PPCBIT(30)
#define PMUXCR_DMA3 __PPCBIT(31)
+#define PMUXCR2 0x064 /* Alternate function signal multiplex control2 */
+
/* Device Disables */
#define DEVDISR 0x070 /* Device disable control */
#define DEVDISR_PCI1 __PPCBIT(0)
+#define DEVDISR_QMAN_BMAN __PPCBIT(0) /* P1023 */
#define DEVDISR_PCI2 __PPCBIT(1)
+#define DEVDISR_FMAN __PPCBIT(1) /* P1023 */
#define DEVDISR_PCIE __PPCBIT(2)
+#define DEVDISR_MACSEC __PPCBIT(3) /* P1023 */
#define DEVDISR_LBC __PPCBIT(4)
#define DEVDISR_PCIE2 __PPCBIT(5)
#define DEVDISR_PCIE3 __PPCBIT(6)
Index: src/sys/arch/powerpc/include/booke/openpicreg.h
diff -u src/sys/arch/powerpc/include/booke/openpicreg.h:1.6 src/sys/arch/powerpc/include/booke/openpicreg.h:1.7
--- src/sys/arch/powerpc/include/booke/openpicreg.h:1.6 Sun Jul 15 08:44:57 2012
+++ src/sys/arch/powerpc/include/booke/openpicreg.h Sat Dec 27 16:19:33 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: openpicreg.h,v 1.6 2012/07/15 08:44:57 matt Exp $ */
+/* $NetBSD: openpicreg.h,v 1.7 2014/12/27 16:19:33 nonaka Exp $ */
/*-
* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -275,6 +275,30 @@
+ MPC8572_TIMERSOURCES \
+ MPC8572_MISOURCES))
+#define P1023_EXTERNALSOURCES 12
+#define P1023_ONCHIPSOURCES 64
+#define P1023_ONCHIPBITMAP { 0xbc07f5f9, 0xf0000e00 }
+#define P1023_IPISOURCES 4
+#define P1023_TIMERSOURCES 4/*8?*/
+#define P1023_MISOURCES 4/*8?*/
+#define P1023_MSIGROUPSOURCES 8
+#define P1023_NCPUS 2
+#define P1023_SOURCES /* 116 */ \
+ (P1023_EXTERNALSOURCES \
+ + P1023_ONCHIPSOURCES \
+ + P1023_MSIGROUPSOURCES \
+ + P1023_NCPUS*(P1023_IPISOURCES \
+ + P1023_TIMERSOURCES \
+ + P1023_MISOURCES))
+#define P1017_NCPUS 1
+#define P1017_SOURCES \
+ (P1023_EXTERNALSOURCES \
+ + P1023_ONCHIPSOURCES \
+ + P1023_MSIGROUPSOURCES \
+ + P1017_NCPUS*(P1023_IPISOURCES \
+ + P1023_TIMERSOURCES \
+ + P1023_MISOURCES))
+
#define P1025_EXTERNALSOURCES 6
#define P1025_ONCHIPSOURCES 64
#define P1025_ONCHIPBITMAP { 0xbd1fffff, 0x01789c18 }
@@ -348,20 +372,28 @@
#define ISOURCE_PCIEX3_MPC8572 8 /* MPC8572/P20x0/P1025 */
#define ISOURCE_PCI1 8 /* MPC8548/MPC8544/MPC8536/MPC8555 */
#define ISOURCE_ETSEC1_G1_ERR 8 /* P1025 */
+#define ISOURCE_FMAN 8 /* P1023 */
#define ISOURCE_PCI2 9 /* MPC8548 */
#define ISOURCE_PCIEX2 9 /* MPC8544/MPC8572/MPC8536/P20x0 */
#define ISOURCE_ETSEC3_G1_TX 9 /* P1025 */
#define ISOURCE_PCIEX 10
#define ISOURCE_ETSEC3_G1_RX 10 /* P1025 */
+#define ISOURCE_MDIO 10 /* P1023 */
#define ISOURCE_PCIEX3 11 /* MPC8544/MPC8536 */
#define ISOURCE_ETSEC3_G1_ERR 11 /* P1025 */
-#define ISOURCE_USB1 12 /* MPC8536/P20x0/P1025 */
+#define ISOURCE_USB1 12 /* MPC8536/P20x0/P1025/P1023 */
#define ISOURCE_ETSEC1_TX 13
+#define ISOURCE_QMAN0 13 /* P1023 */
#define ISOURCE_ETSEC1_RX 14
+#define ISOURCE_BMAN0 14 /* P1023 */
#define ISOURCE_ETSEC3_TX 15
+#define ISOURCE_QMAN1 15 /* P1023 */
#define ISOURCE_ETSEC3_RX 16
+#define ISOURCE_BMAN1 16 /* P1023 */
#define ISOURCE_ETSEC3_ERR 17
+#define ISOURCE_QMAN2 17 /* P1023 */
#define ISOURCE_ETSEC1_ERR 18
+#define ISOURCE_BMAN2 18 /* P1023 */
#define ISOURCE_ETSEC2_TX 19 /* !MPC8544/!MPC8536/!P1025 */
#define ISOURCE_ETSEC2_RX 20 /* !MPC8544/!MPC8536/!P1025 */
#define ISOURCE_ETSEC4_TX 21 /* !MPC8544/!MPC8536/!P20x0/!P1025 */
@@ -389,7 +421,9 @@
#define ISOURCE_SRIO_OMU2 39 /* !MPC8548&!P20x0&!P1025 */
#define ISOURCE_SRIO_IMU2 40 /* !MPC8548&!P20x0&!P1025 */
#define ISOURCE_PME_GENERAL 41 /* MPC8572 */
+#define ISOURCE_SECURITY2_P1023 41 /* P1023 */
#define ISOURCE_SECURITY2 42 /* MPC8572|MPC8536|P20x0|P1025 */
+#define ISOURCE_SEC_GENERAL 42 /* P1023 */
#define ISOURCE_SPI 43 /* MPC8536|P20x0|P1025 */
#define ISOURCE_QEB_IECC 43 /* MPC8568 */
#define ISOURCE_USB3 44 /* MPC8536 */
@@ -410,9 +444,9 @@
#define ISOURCE_57 57
#define ISOURCE_SATA1 58 /* MPC8536 */
#define ISOURCE_TLU2 59 /* MPC8572 */
-#define ISOURCE_DMA2_CHAN1 60 /* MPC8572|P20x0 */
-#define ISOURCE_DMA2_CHAN2 61 /* MPC8572|P20x0 */
-#define ISOURCE_DMA2_CHAN3 62 /* MPC8572|P20x0 */
-#define ISOURCE_DMA2_CHAN4 63 /* MPC8572|P20x0 */
+#define ISOURCE_DMA2_CHAN1 60 /* MPC8572|P20x0|P1023 */
+#define ISOURCE_DMA2_CHAN2 61 /* MPC8572|P20x0|P1023 */
+#define ISOURCE_DMA2_CHAN3 62 /* MPC8572|P20x0|P1023 */
+#define ISOURCE_DMA2_CHAN4 63 /* MPC8572|P20x0|P1023 */
#endif /* _POWERPC_BOOKE_OPENPICREG_H_ */
