Module Name: src Committed By: jmcneill Date: Sun Dec 28 16:03:51 UTC 2014
Modified Files: src/sys/arch/evbarm/rockchip: rockchip_machdep.c rockchip_start.S Log Message: add MULTIPROCESSOR support To generate a diff of this commit: cvs rdiff -u -r1.8 -r1.9 src/sys/arch/evbarm/rockchip/rockchip_machdep.c cvs rdiff -u -r1.1 -r1.2 src/sys/arch/evbarm/rockchip/rockchip_start.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/arch/evbarm/rockchip/rockchip_machdep.c diff -u src/sys/arch/evbarm/rockchip/rockchip_machdep.c:1.8 src/sys/arch/evbarm/rockchip/rockchip_machdep.c:1.9 --- src/sys/arch/evbarm/rockchip/rockchip_machdep.c:1.8 Sun Dec 28 01:51:37 2014 +++ src/sys/arch/evbarm/rockchip/rockchip_machdep.c Sun Dec 28 16:03:51 2014 @@ -1,4 +1,4 @@ -/* $NetBSD: rockchip_machdep.c,v 1.8 2014/12/28 01:51:37 jmcneill Exp $ */ +/* $NetBSD: rockchip_machdep.c,v 1.9 2014/12/28 16:03:51 jmcneill Exp $ */ /* * Machine dependent functions for kernel setup for TI OSK5912 board. @@ -125,7 +125,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: rockchip_machdep.c,v 1.8 2014/12/28 01:51:37 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: rockchip_machdep.c,v 1.9 2014/12/28 16:03:51 jmcneill Exp $"); #include "opt_machdep.h" #include "opt_ddb.h" @@ -147,6 +147,7 @@ __KERNEL_RCSID(0, "$NetBSD: rockchip_mac #include <sys/param.h> #include <sys/systm.h> #include <sys/bus.h> +#include <sys/atomic.h> #include <sys/cpu.h> #include <sys/device.h> #include <sys/exec.h> @@ -420,6 +421,13 @@ initarm(void *arg) pmap_devmap_register(devmap); rockchip_bootstrap(); +#ifdef MULTIPROCESSOR + uint32_t scu_cfg = bus_space_read_4(&rockchip_bs_tag, + rockchip_core0_bsh, ROCKCHIP_SCU_OFFSET + SCU_CFG); + arm_cpu_max = (scu_cfg & SCU_CFG_CPUMAX) + 1; + membar_producer(); +#endif + /* Heads up ... Setup the CPU / MMU / TLB functions. */ if (set_cpufuncs()) panic("cpu not recognized!"); Index: src/sys/arch/evbarm/rockchip/rockchip_start.S diff -u src/sys/arch/evbarm/rockchip/rockchip_start.S:1.1 src/sys/arch/evbarm/rockchip/rockchip_start.S:1.2 --- src/sys/arch/evbarm/rockchip/rockchip_start.S:1.1 Fri Dec 26 16:53:33 2014 +++ src/sys/arch/evbarm/rockchip/rockchip_start.S Sun Dec 28 16:03:51 2014 @@ -41,7 +41,9 @@ #include <arm/rockchip/rockchip_reg.h> #include <evbarm/rockchip/platform.h> -RCSID("$NetBSD: rockchip_start.S,v 1.1 2014/12/26 16:53:33 jmcneill Exp $") +#include <arm/cortex/scu_reg.h> + +RCSID("$NetBSD: rockchip_start.S,v 1.2 2014/12/28 16:03:51 jmcneill Exp $") #if defined(VERBOSE_INIT_ARM) #define XPUTC(n) mov r0, n; bl xputc @@ -150,7 +152,7 @@ _C_LABEL(rockchip_start): XPUTC2(#60) // Make sure the cache is flushed out to RAM for the other CPUs bl _C_LABEL(armv7_dcache_wbinv_all) - bl a20_mpinit + bl rockchip_mpinit XPUTC2(#62) #endif /* MULTIPROCESSOR */ XPUTC2(#13) @@ -169,84 +171,110 @@ _C_LABEL(rockchip_start): #include <arm/cortex/a9_mpsubr.S> +#define PMU_PWRDN_REG 0x0008 +#define PMU_PWRDN_SCU __BIT(4) + #if defined(MULTIPROCESSOR) #ifndef KERNEL_BASES_EQUAL .pushsection .text,"ax",%progbits #endif -a20_mpinit: - mov r4, lr // because we call gtmr_bootdelay - movw r5, #:lower16:(ROCKCHIP_CORE_PBASE+ROCKCHIP_CPUCFG_OFFSET) - movt r5, #:upper16:(ROCKCHIP_CORE_PBASE+ROCKCHIP_CPUCFG_OFFSET) +rockchip_mptramp: + ldr pc, 1f +.global cortex_mpstart_vec +cortex_mpstart_vec: +1: .space 4 + +rockchip_mpinit: + mov r4, lr + /* r5: SCU, r6: PMU, r7: SRAM */ + movw r5, #:lower16:(ROCKCHIP_CORE0_BASE+ROCKCHIP_SCU_OFFSET) + movt r5, #:upper16:(ROCKCHIP_CORE0_BASE+ROCKCHIP_SCU_OFFSET) + movw r6, #:lower16:(ROCKCHIP_CORE1_BASE+ROCKCHIP_PMU_OFFSET) + movt r6, #:upper16:(ROCKCHIP_CORE1_BASE+ROCKCHIP_PMU_OFFSET) + movw r7, #:lower16:(ROCKCHIP_CORE0_BASE+ROCKCHIP_SRAM_OFFSET) + movt r7, #:upper16:(ROCKCHIP_CORE0_BASE+ROCKCHIP_SRAM_OFFSET) /* Set where the other CPU(s) are going to execute */ + XPUTC2(#118) movw r1, #:lower16:cortex_mpstart movt r1, #:upper16:cortex_mpstart - str r1, [r5, #ROCKCHIP_CPUCFG_PRIVATE_REG] - dsb - - /* Assert CPU core reset */ - mov r1, #0 - str r1, [r5, #ROCKCHIP_CPUCFG_CPU1_RST_CTRL_REG] + ldr r0, =cortex_mpstart_vec + str r1, [r0] + ldr r0, =rockchip_mptramp + mov r2, #0 +1: ldr r1, [r0, r2] + str r1, [r7, r2] + add r2, r2, #4 + cmp r2, #32 + blt 1b dsb - /* Ensure CPU1 reset also invalidates its L1 caches */ - ldr r1, [r5, #ROCKCHIP_CPUCFG_GENCTRL_REG] - bic r1, r1, #(1 << 1) - str r1, [r5, #ROCKCHIP_CPUCFG_GENCTRL_REG] + /* Invalid SCU cache tags */ + XPUTC2(#45) + movw r1, #0xffff + movt r1, #0 + str r1, [r5, #SCU_INV_ALL_REG] + + /* Get CPU count */ + ldr r1, [r5, #SCU_CFG] + and r2, r1, #SCU_CFG_CPUMAX + add r2, r2, #1 + + /* Convert to CPU1..N mask */ + mov r7, #0 + lsl r7, r2, #1 + sub r7, r7, #1 + and r7, r7, #~1 + + /* Power down secondary CPUs */ + XPUTC2(#46) + ldr r1, [r6, #PMU_PWRDN_REG] + orr r1, r1, r7 + str r1, [r6, #PMU_PWRDN_REG] dsb - /* Hold DBGPWRDUP signal low */ - ldr r1, [r5, #ROCKCHIP_CPUCFG_DBGCTRL1_REG] - bic r1, r1, #(1 << 1) - str r1, [r5, #ROCKCHIP_CPUCFG_DBGCTRL1_REG] + /* Power up SCU */ + XPUTC2(#46) + ldr r1, [r6, #PMU_PWRDN_REG] + and r1, r1, #~PMU_PWRDN_SCU + str r1, [r6, #PMU_PWRDN_REG] dsb - /* Ramp up power to CPU1 */ - movw r1, #0xff -1: str r1, [r5, #ROCKCHIP_CPUCFG_CPU1_PWRCLAMP_REG] + /* Enable SCU */ + XPUTC2(#46) + ldr r1, [r5, #SCU_CTL] + orr r1, r1, #SCU_CTL_SCU_ENA + str r1, [r5, #SCU_CTL] dsb - lsrs r1, r1, #1 - bne 1b - /* We need to wait (at least) 10ms */ - mov r0, #0x3b000 // 10.06ms - bl _C_LABEL(gtmr_bootdelay) - - /* Clear power-off gating */ - ldr r1, [r5, #ROCKCHIP_CPUCFG_CPU1_PWROFF_REG] - bic r1, r1, #(1 << 1) - str r1, [r5, #ROCKCHIP_CPUCFG_CPU1_PWROFF_REG] + /* Power up secondary CPUs */ + XPUTC2(#33) + ldr r1, [r6, #PMU_PWRDN_REG] + and r1, r1, r7 + str r1, [r6, #PMU_PWRDN_REG] dsb - /* Bring CPU1 out of reset */ - ldr r1, [r5, #ROCKCHIP_CPUCFG_CPU1_RST_CTRL_REG] - orr r1, r1, #(ROCKCHIP_CPUCFG_CPU_RST_CTRL_CORE_RESET|ROCKCHIP_CPUCFG_CPU_RST_CTRL_RESET) - str r1, [r5, #ROCKCHIP_CPUCFG_CPU1_RST_CTRL_REG] - dsb - - /* Reassert DBGPWRDUP signal */ - ldr r1, [r5, #ROCKCHIP_CPUCFG_DBGCTRL1_REG] - orr r1, r1, #(1 << 1) - str r1, [r5, #ROCKCHIP_CPUCFG_DBGCTRL1_REG] - dsb + XPUTC2(#49) + XPUTC2(#50) + XPUTC2(#51) // // Wait up a second for CPU1 to hatch. // - movw r6, #:lower16:arm_cpu_hatched - movt r6, #:upper16:arm_cpu_hatched - mov r5, #200 // 200 x 5ms - -1: dmb // memory barrier - ldr r0, [r6] // load hatched - tst r0, #2 // our bit set yet? - bxne r4 // yes, return - subs r5, r5, #1 // decrement count - bxeq r4 // 0? return - mov r0, #0x1d800 // 5.03ms - bl _C_LABEL(gtmr_bootdelay) - b 1b -ASEND(a20_mpinit) + movw r2, #:lower16:arm_cpu_hatched + movt r2, #:upper16:arm_cpu_hatched + mov r1, #0x10000000 +1: dmb + ldr r0, [r2] + cmp r0, r7 + beq .hatched + subs r1, r1, #1 + bne 1b + +.hatched: + bx r4 + +ASEND(rockchip_mpinit) #ifndef KERNEL_BASES_EQUAL .popsection #endif