Module Name: src
Committed By: palle
Date: Tue Dec 30 18:29:20 UTC 2014
Modified Files:
src/sys/arch/sparc64/sparc64: cache.c cache.h
Log Message:
sp_tlb_flush_*: Avoid run-time check for cpu type/implementation by installing
correct function in cache_setup_funcs()
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/sparc64/sparc64/cache.c
cvs rdiff -u -r1.26 -r1.27 src/sys/arch/sparc64/sparc64/cache.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/sparc64/sparc64/cache.c
diff -u src/sys/arch/sparc64/sparc64/cache.c:1.8 src/sys/arch/sparc64/sparc64/cache.c:1.9
--- src/sys/arch/sparc64/sparc64/cache.c:1.8 Mon Jun 6 02:49:39 2011
+++ src/sys/arch/sparc64/sparc64/cache.c Tue Dec 30 18:29:20 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: cache.c,v 1.8 2011/06/06 02:49:39 mrg Exp $ */
+/* $NetBSD: cache.c,v 1.9 2014/12/30 18:29:20 palle Exp $ */
/*
* Copyright (c) 2011 Matthew R. Green
@@ -35,7 +35,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.8 2011/06/06 02:49:39 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.9 2014/12/30 18:29:20 palle Exp $");
#include "opt_multiprocessor.h"
@@ -75,6 +75,24 @@ void (*blast_icache)(void) = blast_icac
void (*sp_dcache_flush_page)(paddr_t) = dcache_flush_page_us;
#endif
+void (*sp_tlb_flush_pte)(vaddr_t, int) = sp_tlb_flush_pte_us;
+void (*sp_tlb_flush_all)(void) = sp_tlb_flush_all_us;
+
+static void
+sp_tlb_flush_pte_sun4v(vaddr_t va, int ctx)
+{
+ int64_t hv_rc;
+ hv_rc = hv_mmu_demap_page(va, ctx, MAP_DTLB|MAP_ITLB);
+ if ( hv_rc != H_EOK )
+ panic("hv_mmu_demap_page(%p,%d) failed - rc = %" PRIx64 "\n", (void*)va, ctx, hv_rc);
+}
+
+static void
+sp_tlb_flush_all_sun4v(void)
+{
+ panic("sp_tlb_flush_all_sun4v() not implemented yet");
+}
+
void
cache_setup_funcs(void)
{
@@ -103,4 +121,16 @@ cache_setup_funcs(void)
}
#endif
}
+
+ /* Prepare sp_tlb_flush_* functions */
+ if (CPU_ISSUN4V) {
+ sp_tlb_flush_pte = sp_tlb_flush_pte_sun4v;
+ sp_tlb_flush_all = sp_tlb_flush_all_sun4v;
+ } else {
+ if (CPU_IS_USIII_UP() || CPU_IS_SPARC64_V_UP()) {
+ sp_tlb_flush_pte = sp_tlb_flush_pte_usiii;
+ sp_tlb_flush_all = sp_tlb_flush_all_usiii;
+ }
+ }
+
}
Index: src/sys/arch/sparc64/sparc64/cache.h
diff -u src/sys/arch/sparc64/sparc64/cache.h:1.26 src/sys/arch/sparc64/sparc64/cache.h:1.27
--- src/sys/arch/sparc64/sparc64/cache.h:1.26 Wed Nov 5 13:50:50 2014
+++ src/sys/arch/sparc64/sparc64/cache.h Tue Dec 30 18:29:20 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: cache.h,v 1.26 2014/11/05 13:50:50 nakayama Exp $ */
+/* $NetBSD: cache.h,v 1.27 2014/12/30 18:29:20 palle Exp $ */
/*
* Copyright (c) 2011 Matthew R. Green
@@ -118,39 +118,13 @@ void sp_tlb_flush_pte_usiii(vaddr_t, int
void sp_tlb_flush_all_us(void);
void sp_tlb_flush_all_usiii(void);
-static __inline__ void
-sp_tlb_flush_pte_sun4v(vaddr_t va, int ctx)
-{
- int64_t hv_rc;
- hv_rc = hv_mmu_demap_page(va, ctx, MAP_DTLB|MAP_ITLB);
- if ( hv_rc != H_EOK )
- panic("hv_mmu_demap_page(%p,%d) failed - rc = %" PRIx64 "\n", (void*)va, ctx, hv_rc);
-}
-
-static __inline__ void
-sp_tlb_flush_pte(vaddr_t va, int ctx)
-{
- if (CPU_ISSUN4V)
- sp_tlb_flush_pte_sun4v(va, ctx);
- else if (CPU_IS_USIII_UP() || CPU_IS_SPARC64_V_UP())
- sp_tlb_flush_pte_usiii(va, ctx);
- else
- sp_tlb_flush_pte_us(va, ctx);
-}
-
-static __inline__ void
-sp_tlb_flush_all(void)
-{
- if (CPU_IS_USIII_UP() || CPU_IS_SPARC64_V_UP())
- sp_tlb_flush_all_usiii();
- else
- sp_tlb_flush_all_us();
-}
extern void (*dcache_flush_page)(paddr_t);
extern void (*dcache_flush_page_cpuset)(paddr_t, sparc64_cpuset_t);
extern void (*blast_dcache)(void);
extern void (*blast_icache)(void);
+extern void (*sp_tlb_flush_pte)(vaddr_t, int);
+extern void (*sp_tlb_flush_all)(void);
void cache_setup_funcs(void);
