Module Name: src
Committed By: jmcneill
Date: Wed Dec 31 18:08:58 UTC 2014
Modified Files:
src/sys/arch/arm/rockchip: rockchip_crureg.h
Log Message:
add some more bits
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/rockchip/rockchip_crureg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/rockchip/rockchip_crureg.h
diff -u src/sys/arch/arm/rockchip/rockchip_crureg.h:1.5 src/sys/arch/arm/rockchip/rockchip_crureg.h:1.6
--- src/sys/arch/arm/rockchip/rockchip_crureg.h:1.5 Tue Dec 30 03:53:52 2014
+++ src/sys/arch/arm/rockchip/rockchip_crureg.h Wed Dec 31 18:08:58 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: rockchip_crureg.h,v 1.5 2014/12/30 03:53:52 jmcneill Exp $ */
+/* $NetBSD: rockchip_crureg.h,v 1.6 2014/12/31 18:08:58 jmcneill Exp $ */
/*-
* Copyright (c) 2014 Jared D. McNeill <jmcne...@invisible.ca>
@@ -62,7 +62,12 @@
#define CRU_PLL_CON1_CLKF_MASK __BITS(31,16)
#define CRU_PLL_CON1_CLKF __BITS(15,0)
+#define CRU_PLL_CON2_BWADJ_MASK __BITS(27,16)
+#define CRU_PLL_CON2_BWADJ __BITS(11,0)
+
+#define CRU_PLL_CON3_RESET_MASK __BIT(21)
#define CRU_PLL_CON3_POWER_DOWN_MASK __BIT(17)
+#define CRU_PLL_CON3_RESET __BIT(5)
#define CRU_PLL_CON3_POWER_DOWN __BIT(1)
#define CRU_MODE_CON_APLL_WORK_MODE_MASK __BITS(17,16)
@@ -105,6 +110,11 @@
#define CRU_CLKSEL_CON11_MMC0_PLL_SEL __BIT(6)
#define CRU_CLKSEL_CON11_MMC0_DIV_CON __BITS(5,0)
+#define CRU_CLKSEL_CON13_UART0_CLK_SEL_MASK __BITS(25,24)
+#define CRU_CLKSEL_CON13_UART0_DIV_CON_MASK __BITS(22,16)
+#define CRU_CLKSEL_CON13_UART0_CLK_SEL __BITS(9,8)
+#define CRU_CLKSEL_CON13_UART0_DIV_CON __BITS(6,0)
+
#define CRU_GLB_SRST_FST_MAGIC 0xfdb9
#endif /* !_ROCKCHIP_CRUREG_H */
