Module Name: src
Committed By: martin
Date: Sun Jan 4 11:19:00 UTC 2015
Modified Files:
src/sys/arch/arm/samsung [netbsd-7]: exynos4_loc.c exynos4_reg.h
exynos5_loc.c exynos5_reg.h exynos_gpio.c exynos_i2c.c
exynos_intr.h exynos_io.c exynos_io.h exynos_reg.h exynos_smc.S
exynos_soc.c exynos_usb.c exynos_var.h exynos_wdt.c mct.c mct_reg.h
mct_var.h smc.h sscom.c
src/sys/arch/evbarm/conf [netbsd-7]: ODROID-U std.odroid
src/sys/arch/evbarm/odroid [netbsd-7]: odroid_machdep.c odroid_start.S
Added Files:
src/sys/arch/evbarm/conf [netbsd-7]: ODROID-XU
Removed Files:
src/sys/arch/evbarm/conf [netbsd-7]: ODROID ODROID_INSTALL
Log Message:
Pull up the following revisions, requested by skrll in #373:
sys/arch/arm/samsung/exynos4_loc.c 1.10-1.11
sys/arch/arm/samsung/exynos4_reg.h 1.8-1.13
sys/arch/arm/samsung/exynos5_loc.c 1.8-1.12
sys/arch/arm/samsung/exynos5_reg.h 1.11-1.20
sys/arch/arm/samsung/exynos_gpio.c 1.7-1.12
sys/arch/arm/samsung/exynos_i2c.c 1.2-1.3
sys/arch/arm/samsung/exynos_intr.h 1.2
sys/arch/arm/samsung/exynos_io.c 1.7-1.8
sys/arch/arm/samsung/exynos_io.h 1.5-1.6
sys/arch/arm/samsung/exynos_reg.h 1.8-1.13
sys/arch/arm/samsung/exynos_smc.S 1.2-1.3
sys/arch/arm/samsung/exynos_soc.c 1.15-1.27
sys/arch/arm/samsung/exynos_usb.c 1.8-1.13
sys/arch/arm/samsung/exynos_var.h 1.13-1.18
sys/arch/arm/samsung/exynos_wdt.c 1.5
sys/arch/arm/samsung/mct.c 1.4-1.5
sys/arch/arm/samsung/mct_reg.h 1.2
sys/arch/arm/samsung/mct_var.h 1.3
sys/arch/arm/samsung/smc.h 1.2
sys/arch/arm/samsung/sscom.c 1.7
sys/arch/evbarm/odroid/odroid_machdep.c 1.25-1.39
sys/arch/evbarm/odroid/odroid_start.S 1.4-1.6
sys/arch/evbarm/conf/std.odroid 1.3-1.5
sys/arch/evbarm/conf/ODROID delete
sys/arch/evbarm/conf/ODROID-U 1.10-1.17
sys/arch/evbarm/conf/ODROID_INSTALL delete
sys/arch/evbarm/conf/ODROID-XU 1.1-1.4
Improve ODROID support.
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.9.4.1 src/sys/arch/arm/samsung/exynos4_loc.c
cvs rdiff -u -r1.7 -r1.7.4.1 src/sys/arch/arm/samsung/exynos4_reg.h \
src/sys/arch/arm/samsung/exynos5_loc.c \
src/sys/arch/arm/samsung/exynos_reg.h \
src/sys/arch/arm/samsung/exynos_usb.c
cvs rdiff -u -r1.10 -r1.10.4.1 src/sys/arch/arm/samsung/exynos5_reg.h
cvs rdiff -u -r1.6 -r1.6.6.1 src/sys/arch/arm/samsung/exynos_gpio.c
cvs rdiff -u -r1.1 -r1.1.4.1 src/sys/arch/arm/samsung/exynos_i2c.c
cvs rdiff -u -r1.1 -r1.1.8.1 src/sys/arch/arm/samsung/exynos_intr.h \
src/sys/arch/arm/samsung/exynos_smc.S src/sys/arch/arm/samsung/mct_reg.h \
src/sys/arch/arm/samsung/smc.h
cvs rdiff -u -r1.6 -r1.6.8.1 src/sys/arch/arm/samsung/exynos_io.c
cvs rdiff -u -r1.4 -r1.4.6.1 src/sys/arch/arm/samsung/exynos_io.h
cvs rdiff -u -r1.14 -r1.14.4.1 src/sys/arch/arm/samsung/exynos_soc.c
cvs rdiff -u -r1.12 -r1.12.4.1 src/sys/arch/arm/samsung/exynos_var.h
cvs rdiff -u -r1.4 -r1.4.8.1 src/sys/arch/arm/samsung/exynos_wdt.c
cvs rdiff -u -r1.3 -r1.3.4.1 src/sys/arch/arm/samsung/mct.c
cvs rdiff -u -r1.2 -r1.2.8.1 src/sys/arch/arm/samsung/mct_var.h
cvs rdiff -u -r1.6 -r1.6.2.1 src/sys/arch/arm/samsung/sscom.c
cvs rdiff -u -r1.5 -r0 src/sys/arch/evbarm/conf/ODROID
cvs rdiff -u -r1.9 -r1.9.4.1 src/sys/arch/evbarm/conf/ODROID-U
cvs rdiff -u -r0 -r1.4.4.2 src/sys/arch/evbarm/conf/ODROID-XU
cvs rdiff -u -r1.2 -r0 src/sys/arch/evbarm/conf/ODROID_INSTALL
cvs rdiff -u -r1.2 -r1.2.4.1 src/sys/arch/evbarm/conf/std.odroid
cvs rdiff -u -r1.24 -r1.24.4.1 src/sys/arch/evbarm/odroid/odroid_machdep.c
cvs rdiff -u -r1.3 -r1.3.4.1 src/sys/arch/evbarm/odroid/odroid_start.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/samsung/exynos4_loc.c
diff -u src/sys/arch/arm/samsung/exynos4_loc.c:1.9 src/sys/arch/arm/samsung/exynos4_loc.c:1.9.4.1
--- src/sys/arch/arm/samsung/exynos4_loc.c:1.9 Wed Jun 11 14:54:32 2014
+++ src/sys/arch/arm/samsung/exynos4_loc.c Sun Jan 4 11:19:00 2015
@@ -1,3 +1,5 @@
+/* $NetBSD: exynos4_loc.c,v 1.9.4.1 2015/01/04 11:19:00 martin Exp $ */
+
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -139,6 +141,10 @@
#define IRQ_EINT_1 IRQ_SPI(17)
#define IRQ_EINT_0 IRQ_SPI(16)
+/* rest of PPI's marked reserved */
+#define IRQ_MCT_L IRQ_PPI(12)
+#define IRQ_MCT_G IRQ_PPI(10)
+
#define IRQ_CPU_NIRQOUT_3 EXYNOS_COMBINERIRQ(19, 6)
#define IRQ_PARITYFAILSCU_3 EXYNOS_COMBINERIRQ(19, 5)
#define IRQ_PARITYFAIL3 EXYNOS_COMBINERIRQ(19, 4)
@@ -266,7 +272,7 @@
static const struct exyo_locators exynos4_locators[] = {
{ "exyogpio", 0, 0, NOPORT, NOINTR, 0 },
{ "exyoiic", 0, 0, NOPORT, NOINTR, 0 },
- { "mct", OFFANDSIZE(,MCT), NOPORT, IRQ_G0_IRQ, 0 },
+ { "mct", OFFANDSIZE(,MCT), NOPORT, IRQ_MCT_G, 0 },
{ "exyowdt", OFFANDSIZE(,WDT), NOPORT, IRQ_WDT, 0 },
{ "sscom", OFFANDSIZE(,UART0), 0, IRQ_UART0, 0 },
{ "sscom", OFFANDSIZE(,UART1), 1, IRQ_UART1, 0 },
Index: src/sys/arch/arm/samsung/exynos4_reg.h
diff -u src/sys/arch/arm/samsung/exynos4_reg.h:1.7 src/sys/arch/arm/samsung/exynos4_reg.h:1.7.4.1
--- src/sys/arch/arm/samsung/exynos4_reg.h:1.7 Wed Jun 11 14:49:50 2014
+++ src/sys/arch/arm/samsung/exynos4_reg.h Sun Jan 4 11:19:00 2015
@@ -1,4 +1,5 @@
-/* $NetBSD */
+/* $NetBSD: exynos4_reg.h,v 1.7.4.1 2015/01/04 11:19:00 martin Exp $ */
+
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -115,8 +116,12 @@
#define EXYNOS4_SYSREG_OFFSET 0x00010000
#define EXYNOS4_PMU_OFFSET 0x00020000 /* Power Management Unit */
-#define EXYNOS4_CMU_TOP_PART_OFFSET 0x00030000 /* XXX unknown XXX */
-#define EXYNOS4_CMU_CORE_ISP_PART_OFFSET 0x00040000 /* XXX unknown XXX */
+#define EXYNOS4_CMU_TOP_PART_OFFSET 0x00030000 /* Clock(s) management unit */
+#define EXYNOS4_CMU_EPLL 0x0003C010 /* Audio and ext. interf. clock */
+#define EXYNOS4_CMU_VPLL 0x0003C020 /* Video core (dither?) clock */
+#define EXYNOS4_CMU_CORE_ISP_PART_OFFSET 0x00040000 /* Clock(s) management unit */
+#define EXYNOS4_CMU_MPLL 0x00040008 /* MEM cntr. clock */
+#define EXYNOS4_CMU_APLL 0x00044000 /* ARM core clock */
#define EXYNOS4_MCT_OFFSET 0x00050000 /* Multi Core Timer */
#define EXYNOS4_WDT_OFFSET 0x00060000 /* Watch Dog Timer */
#define EXYNOS4_RTC_OFFSET 0x00070000 /* Real Time Clock */
@@ -207,8 +212,9 @@
#define EXYNOS4_SROMC_OFFSET 0x02570000
#define EXYNOS4_USB2HOST_OFFSET 0x02580000
-#define EXYNOS4_USBHOST0_OFFSET 0x02580000 /* USB EHCI */
-#define EXYNOS4_USBHOST1_OFFSET 0x02590000 /* USB OHCI companion to EHCI (paired) */
+#define EXYNOS4_USB2_HOST_EHCI_OFFSET 0x02580000
+#define EXYNOS4_USB2_HOST_OHCI_OFFSET 0x02590000
+#define EXYNOS4_USB2_HOST_PHYCTRL_OFFSET 0x025B0000
#define EXYNOS4_USBOTG1_OFFSET 0x025B0000 /* USB On The Go interface */
#define EXYNOS4_PDMA0_OFFSET 0x02680000 /* Peripheral DMA */
@@ -262,13 +268,33 @@
#define EXYNOS4_PWMTIMER_OFFSET 0x039D0000
/* AUDIOCORE */
-#define EXYNOS4_AUDIOCORE_OFFSET 0x04060000 /* on 1Mb L1 chunk */
+#define EXYNOS4_AUDIOCORE_OFFSET 0x04000000 /* on 1Mb L1 chunk */
#define EXYNOS4_AUDIOCORE_VBASE (EXYNOS_CORE_VBASE + EXYNOS4_AUDIOCORE_OFFSET)
-#define EXYNOS4_AUDIOCORE_PBASE 0x03860000 /* Audio SFR */
-#define EXYNOS4_AUDIOCORE_SIZE 0x00001000
+#define EXYNOS4_AUDIOCORE_PBASE 0x03800000 /* Audio SFR */
+#define EXYNOS4_AUDIOCORE_SIZE 0x00100000
+
+#define EXYNOS4_GPIO_I2S0_OFFSET (EXYNOS4_AUDIOCORE_OFFSET + 0x00060000)
-#define EXYNOS4_GPIO_I2S0_OFFSET (EXYNOS4_AUDIOCORE_OFFSET + 0x00000000)
+/* used Exynos4 USB PHY registers */
+#define USB_PHYPWR 0x00
+#define PHYPWR_FORCE_SUSPEND __BIT(1)
+#define PHYPWR_ANALOG_POWERDOWN __BIT(3)
+#define PHYPWR_OTG_DISABLE __BIT(4)
+#define PHYPWR_SLEEP_PHY0 __BIT(5)
+#define PHYPWR_NORMAL_MASK 0x19
+#define PHYPWR_NORMAL_MASK_PHY0 (__BITS(3,3) | 1)
+#define PHYPWR_NORMAL_MASK_PHY1 __BITS(6,3)
+#define PHYPWR_NORMAL_MASK_HSIC0 __BITS(9,3)
+#define PHYPWR_NORMAL_MASK_HSIC1 __BITS(12,3)
+#define USB_PHYCLK 0x04 /* holds FSEL_CLKSEL_ */
+#define USB_RSTCON 0x08
+#define RSTCON_SWRST __BIT(0)
+#define RSTCON_HLINK_RWRST __BIT(1)
+#define RSTCON_DEVPHYLINK_SWRST __BIT(2)
+#define RSTCON_DEVPHY_SWRST __BITS(0,3)
+#define RSTCON_HOSTPHY_SWRST __BITS(3,4)
+#define RSTCON_HOSTPHYLINK_SWRST __BITS(7,4)
-#endif /* _ARM_SAMSUNG_EXYNOS5_REG_H_ */
+#endif /* _ARM_SAMSUNG_EXYNOS4_REG_H_ */
Index: src/sys/arch/arm/samsung/exynos5_loc.c
diff -u src/sys/arch/arm/samsung/exynos5_loc.c:1.7 src/sys/arch/arm/samsung/exynos5_loc.c:1.7.4.1
--- src/sys/arch/arm/samsung/exynos5_loc.c:1.7 Wed Jun 11 14:54:32 2014
+++ src/sys/arch/arm/samsung/exynos5_loc.c Sun Jan 4 11:19:00 2015
@@ -1,3 +1,5 @@
+/* $NetBSD: exynos5_loc.c,v 1.7.4.1 2015/01/04 11:19:00 martin Exp $ */
+
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -91,7 +93,7 @@
#define IRQ_CPU_NFIQ_1 IRQ_SPI(67)
#define IRQ_CPU_NFIQ_0 IRQ_SPI(66)
#define IRQ_TMU IRQ_SPI(65)
-#define IRQ_I2C IRQ_SPI(64)
+#define IRQ_HDMI_I2C IRQ_SPI(64)
#define IRQ_I2C7 IRQ_SPI(63)
#define IRQ_I2C6 IRQ_SPI(62)
#define IRQ_I2C5 IRQ_SPI(61)
@@ -213,11 +215,14 @@
EXYNOS5##p##_##n##_OFFSET, 0x10000
static const struct exyo_locators exynos5_locators[] = {
+ { "exyogpio", 0, 0, NOPORT, NOINTR, 0 },
+ { "exyoiic", 0, 0, NOPORT, NOINTR, 0 },
{ "exyowdt", OFFANDSIZE(,WDT), NOPORT, IRQ_WDT, 0 },
{ "sscom", OFFANDSIZE(,UART0), 0, IRQ_UART0, 0 },
{ "sscom", OFFANDSIZE(,UART1), 1, IRQ_UART1, 0 },
{ "sscom", OFFANDSIZE(,UART2), 2, IRQ_UART2, 0 },
{ "sscom", OFFANDSIZE(,UART3), 3, IRQ_UART3, 0 },
+ { "exyousb", OFFANDSIZE(,USB2HOST), NOPORT, IRQ_USB_HOST20, 0 },
};
const struct exyo_locinfo exynos5_locinfo = {
@@ -228,6 +233,16 @@ const struct exyo_locinfo exynos5_locinf
/* flag signal the use of gpio */
static const struct exyo_locators exynos5_i2c_locators[] = {
+ /* busname, sdabit, slcbit, func */
+ { "iic0", OFFANDSIZE(,I2C0), 0, IRQ_I2C0_USI0, 1 , "GPB3", 0, 1, 2 },
+ { "iic1", OFFANDSIZE(,I2C1), 1, IRQ_I2C1_USI1, 1 , "GPB3", 2, 3, 2 },
+ { "iic2", OFFANDSIZE(,I2C2), 2, IRQ_I2C2_USI2, 1 , "GPA0", 6, 7, 3 },
+ { "iic3", OFFANDSIZE(,I2C3), 3, IRQ_I2C3_USI3, 1 , "GPA1", 2, 3, 3 },
+ { "iic4", OFFANDSIZE(,I2C4), 4, IRQ_I2C4, 1 , "GPA2", 0, 1, 3 },
+ { "iic5", OFFANDSIZE(,I2C5), 5, IRQ_I2C5, 1 , "GPA2", 2, 3, 3 },
+ { "iic6", OFFANDSIZE(,I2C6), 6, IRQ_I2C6, 1 , "GPB1", 3, 4, 4 },
+ { "iic7", OFFANDSIZE(,I2C7), 7, IRQ_I2C7, 1 , "GPB2", 2, 3, 3 },
+ { "iic8", OFFANDSIZE(,I2CHDMI), 8, IRQ_HDMI_I2C, 0 , "", 0, 0, 0 },
};
Index: src/sys/arch/arm/samsung/exynos_reg.h
diff -u src/sys/arch/arm/samsung/exynos_reg.h:1.7 src/sys/arch/arm/samsung/exynos_reg.h:1.7.4.1
--- src/sys/arch/arm/samsung/exynos_reg.h:1.7 Sun Aug 3 19:14:24 2014
+++ src/sys/arch/arm/samsung/exynos_reg.h Sun Jan 4 11:19:00 2015
@@ -1,4 +1,5 @@
-/* $NetBSD */
+/* $NetBSD: exynos_reg.h,v 1.7.4.1 2015/01/04 11:19:00 martin Exp $ */
+
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -112,6 +113,25 @@
#define EXYNOS_USB_FREQ EXYNOS_F_IN_FREQ/* 24 Mhz */
+/* PLLs */
+#define PLL_LOCK_OFFSET 0x000
+#define PLL_CON0_OFFSET 0x100
+#define PLL_CON1_OFFSET 0x104
+
+#define PLL_CON0_ENABLE __BIT(31)
+#define PLL_CON0_LOCKED __BIT(29) /* has the PLL locked on */
+#define PLL_CON0_M __BITS(16,25) /* PLL M divide value */
+#define PLL_CON0_P __BITS( 8,13) /* PLL P divide value */
+#define PLL_CON0_S __BITS( 0, 2) /* PLL S divide value */
+
+#define PLL_PMS2FREQ(F, M, P, S) (((M)*(F))/((P)*(1<<(S))))
+#define PLL_FREQ(f, v) PLL_PMS2FREQ( \
+ (f),\
+ __SHIFTOUT((v), PLL_CON0_M),\
+ __SHIFTOUT((v), PLL_CON0_P),\
+ __SHIFTOUT((v), PLL_CON0_S))
+
+
/* Watchdog register definitions */
#define EXYNOS_WDT_WTCON 0x0000
#define WTCON_PRESCALER __BITS(15,8)
@@ -159,32 +179,23 @@
#define EXYNOS_PMU_USB_HSIC_1_PHY_CTRL 0x708
#define EXYNOS_PMU_USB_HSIC_2_PHY_CTRL 0x70C
-#define PMU_PHY_ENABLE (1<< 0)
-#define PMU_PHY_DISABLE (0)
+#define PMU_PHY_ENABLE (1 << 0)
+#define PMU_PHY_DISABLE (0)
+#define EXYNOS_PMU_DEBUG_CLKOUT 0x0A00
/* used SYSREG registers */
#define EXYNOS5_SYSREG_USB20_PHY_TYPE 0x230
+#define USB20_PHY_HOST_LINK_EN (1 << 0)
-/* used USB PHY registers */
-#define USB_PHYPWR 0x00
-#define PHYPWR_FORCE_SUSPEND __BIT(1)
-#define PHYPWR_ANALOG_POWERDOWN __BIT(3)
-#define PHYPWR_OTG_DISABLE __BIT(4)
-#define PHYPWR_SLEEP_PHY0 __BIT(5)
-#define PHYPWR_NORMAL_MASK 0x19
-#define PHYPWR_NORMAL_MASK_PHY0 (__BITS(3,3) | 1)
-#define PHYPWR_NORMAL_MASK_PHY1 __BITS(6,3)
-#define PHYPWR_NORMAL_MASK_HSIC0 __BITS(9,3)
-#define PHYPWR_NORMAL_MASK_HSIC1 __BITS(12,3)
-#define USB_PHYCLK 0x04
-#define USB_RSTCON 0x08
-#define RSTCON_SWRST __BIT(0)
-#define RSTCON_HLINK_RWRST __BIT(1)
-#define RSTCON_DEVPHYLINK_SWRST __BIT(2)
-#define RSTCON_DEVPHY_SWRST __BITS(0,3)
-#define RSTCON_HOSTPHY_SWRST __BITS(3,4)
-#define RSTCON_HOSTPHYLINK_SWRST __BITS(7,4)
+/* Generic USB registers/constants */
+#define FSEL_CLKSEL_50M 7
+#define FSEL_CLKSEL_24M 5
+#define FSEL_CLKSEL_20M 4
+#define FSEL_CLKSEL_19200K 3
+#define FSEL_CLKSEL_12M 2
+#define FSEL_CLKSEL_10M 1
+#define FSEL_CLKSEL_9600K 0
#endif /* _ARM_SAMSUNG_EXYNOS_REG_H_ */
Index: src/sys/arch/arm/samsung/exynos_usb.c
diff -u src/sys/arch/arm/samsung/exynos_usb.c:1.7 src/sys/arch/arm/samsung/exynos_usb.c:1.7.4.1
--- src/sys/arch/arm/samsung/exynos_usb.c:1.7 Sat Jun 21 09:11:04 2014
+++ src/sys/arch/arm/samsung/exynos_usb.c Sun Jan 4 11:19:00 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: exynos_usb.c,v 1.7 2014/06/21 09:11:04 skrll Exp $ */
+/* $NetBSD: exynos_usb.c,v 1.7.4.1 2015/01/04 11:19:00 martin Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -35,7 +35,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: exynos_usb.c,v 1.7 2014/06/21 09:11:04 skrll Exp $");
+__KERNEL_RCSID(1, "$NetBSD: exynos_usb.c,v 1.7.4.1 2015/01/04 11:19:00 martin Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -67,11 +67,6 @@ __KERNEL_RCSID(1, "$NetBSD: exynos_usb.c
#include <arm/samsung/exynos_var.h>
#include <arm/samsung/exynos_io.h>
-#define EHCI_OFFSET (0)
-#define OHCI_OFFSET (1*EXYNOS_BLOCK_SIZE)
-#define DEVLINK_OFFSET (2*EXYNOS_BLOCK_SIZE) /* Exynos5 */
-#define USB2PHY_OFFSET (3*EXYNOS_BLOCK_SIZE)
-
struct exynos_usb_softc {
device_t sc_self;
@@ -83,8 +78,6 @@ struct exynos_usb_softc {
bus_space_handle_t sc_ohci_bsh;
bus_space_handle_t sc_usb2phy_bsh;
- bus_space_handle_t sc_pmuregs_bsh;
-
device_t sc_ohci_dev;
device_t sc_ehci_dev;
@@ -92,19 +85,14 @@ struct exynos_usb_softc {
void *sc_intrh;
} exynos_usb_sc;
+
struct exynos_usb_attach_args {
const char *name;
};
-static struct exynos_gpio_pinset uhost_pwr_pinset = {
- .pinset_group = "ETC6",
- .pinset_func = 0,
- .pinset_mask = __BIT(5) | __BIT(6),
-};
-
+/* forwards */
static int exynos_usb_intr(void *arg);
-static void exynos_usb_phy_init(struct exynos_usb_softc *sc);
static int exynos_usb_match(device_t, cfdata_t, void *);
@@ -131,9 +119,7 @@ exynos_usb_attach(device_t parent, devic
struct exynos_usb_softc * const sc = &exynos_usb_sc;
struct exyo_attach_args *exyoaa = (struct exyo_attach_args *) aux;
struct exyo_locators *loc = &exyoaa->exyo_loc;
- struct exynos_gpio_pindata XuhostOVERCUR;
- struct exynos_gpio_pindata XuhostPWREN;
- bus_size_t pmu_offset;
+ bus_size_t ehci_offset, ohci_offset, usb2phy_offset;
/* no locators expected */
KASSERT(loc->loc_port == EXYOCF_PORT_DEFAULT);
@@ -148,50 +134,52 @@ exynos_usb_attach(device_t parent, devic
sc->sc_dmat = exyoaa->exyo_dmat;
// sc->sc_dmat = exyoaa->exyo_coherent_dmat;
- bus_space_subregion(sc->sc_bst, exyoaa->exyo_core_bsh,
- loc->loc_offset + EHCI_OFFSET, EXYNOS_BLOCK_SIZE,
- &sc->sc_ehci_bsh);
- bus_space_subregion(sc->sc_bst, exyoaa->exyo_core_bsh,
- loc->loc_offset + OHCI_OFFSET, EXYNOS_BLOCK_SIZE,
- &sc->sc_ohci_bsh);
- bus_space_subregion(sc->sc_bst, exyoaa->exyo_core_bsh,
- loc->loc_offset + USB2PHY_OFFSET, EXYNOS_BLOCK_SIZE,
- &sc->sc_usb2phy_bsh);
-
#ifdef EXYNOS4
- if (IS_EXYNOS4_P())
- pmu_offset = EXYNOS4_PMU_OFFSET;
+ ehci_offset = EXYNOS4_USB2_HOST_EHCI_OFFSET;
+ ohci_offset = EXYNOS4_USB2_HOST_OHCI_OFFSET;
+ usb2phy_offset = EXYNOS4_USB2_HOST_PHYCTRL_OFFSET;
#endif
#ifdef EXYNOS5
- if (IS_EXYNOS5_P())
- pmu_offset = EXYNOS5_ALIVE_OFFSET;
+ ehci_offset = EXYNOS5_USB2_HOST_EHCI_OFFSET;
+ ohci_offset = EXYNOS5_USB2_HOST_OHCI_OFFSET;
+ usb2phy_offset = EXYNOS5_USB2_HOST_PHYCTRL_OFFSET;
#endif
- KASSERT(pmu_offset);
bus_space_subregion(sc->sc_bst, exyoaa->exyo_core_bsh,
- pmu_offset, EXYNOS_BLOCK_SIZE,
- &sc->sc_pmuregs_bsh);
+ ehci_offset, EXYNOS_BLOCK_SIZE,
+ &sc->sc_ehci_bsh);
+ bus_space_subregion(sc->sc_bst, exyoaa->exyo_core_bsh,
+ ohci_offset, EXYNOS_BLOCK_SIZE,
+ &sc->sc_ohci_bsh);
+ bus_space_subregion(sc->sc_bst, exyoaa->exyo_core_bsh,
+ usb2phy_offset, EXYNOS_BLOCK_SIZE,
+ &sc->sc_usb2phy_bsh);
aprint_naive("\n");
aprint_normal("\n");
- /* power up USB subsystem XXX PWREN not working yet */
- exynos_gpio_pinset_acquire(&uhost_pwr_pinset);
- exynos_gpio_pinset_to_pindata(&uhost_pwr_pinset, 5, &XuhostPWREN);
- exynos_gpio_pinset_to_pindata(&uhost_pwr_pinset, 6, &XuhostOVERCUR);
-
- /* enable power and set Xuhost OVERCUR to inactive by pulling it up */
- exynos_gpio_pindata_ctl(&XuhostPWREN, GPIO_PIN_PULLUP);
- exynos_gpio_pindata_ctl(&XuhostOVERCUR, GPIO_PIN_PULLUP);
- DELAY(80000);
+ /* power up USB subsystem */
+ exynos_usb_soc_powerup();
+
+ /* init USB phys */
+ exynos_usb_phy_init(sc->sc_usb2phy_bsh);
/*
* Disable interrupts
+ *
+ * To prevent OHCI lockups on Exynos5 SoCs, we first have to read the
+ * address before we set it; this is most likely a bug in the SoC
*/
#if NOHCI > 0
+ int regval;
+
+ regval = bus_space_read_1(sc->sc_bst, sc->sc_ohci_bsh,
+ OHCI_INTERRUPT_DISABLE);
+ regval = OHCI_ALL_INTRS;
bus_space_write_4(sc->sc_bst, sc->sc_ohci_bsh,
- OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
+ OHCI_INTERRUPT_DISABLE, regval);
#endif
+
#if NEHCI > 0
bus_size_t caplength = bus_space_read_1(sc->sc_bst,
sc->sc_ehci_bsh, EHCI_CAPLENGTH);
@@ -199,9 +187,6 @@ exynos_usb_attach(device_t parent, devic
caplength + EHCI_USBINTR, 0);
#endif
- /* init USB phys */
- exynos_usb_phy_init(sc);
-
/* claim shared interrupt for OHCI/EHCI */
sc->sc_intrh = intr_establish(sc->sc_irq,
IPL_USB, IST_LEVEL, exynos_usb_intr, sc);
@@ -366,120 +351,3 @@ exynos_ehci_attach(device_t parent, devi
}
#endif
-
-/*
- * USB Phy init
- */
-
-static void
-exynos_usb2_set_isolation(struct exynos_usb_softc *sc, bool on)
-{
- int val;
-
- val = on ? PMU_PHY_DISABLE : PMU_PHY_ENABLE;
- if (IS_EXYNOS4X12_P()) {
- bus_space_write_4(sc->sc_bst, sc->sc_pmuregs_bsh,
- EXYNOS_PMU_USB_PHY_CTRL, val);
- bus_space_write_4(sc->sc_bst, sc->sc_pmuregs_bsh,
- EXYNOS_PMU_USB_HSIC_1_PHY_CTRL, val);
- bus_space_write_4(sc->sc_bst, sc->sc_pmuregs_bsh,
- EXYNOS_PMU_USB_HSIC_2_PHY_CTRL, val);
- } else {
- bus_space_write_4(sc->sc_bst, sc->sc_pmuregs_bsh,
- EXYNOS_PMU_USBDEV_PHY_CTRL, val);
- bus_space_write_4(sc->sc_bst, sc->sc_pmuregs_bsh,
- EXYNOS_PMU_USBHOST_PHY_CTRL, val);
- }
-}
-
-
-#ifdef EXYNOS4
-static void
-exynos4_usb2phy_enable(struct exynos_usb_softc *sc)
-{
- uint32_t phypwr, rstcon, clkreg;
-
- /* disable phy isolation */
- exynos_usb2_set_isolation(sc, false);
-
- /* write clock value */
- clkreg = 5; /* 24 Mhz */
- bus_space_write_4(sc->sc_bst, sc->sc_usb2phy_bsh,
- USB_PHYCLK, clkreg);
-
- /* set device and host to normal */
- phypwr = bus_space_read_4(sc->sc_bst, sc->sc_usb2phy_bsh,
- USB_PHYPWR);
-
- /* enable analog, enable otg, unsleep phy0 (host) */
- phypwr &= ~PHYPWR_NORMAL_MASK_PHY0;
- bus_space_write_4(sc->sc_bst, sc->sc_usb2phy_bsh,
- USB_PHYPWR, phypwr);
-
- if (IS_EXYNOS4X12_P()) {
- /* enable hsic0 (host), enable hsic1 and phy1 (otg) */
- phypwr = bus_space_read_4(sc->sc_bst, sc->sc_usb2phy_bsh,
- USB_PHYPWR);
- phypwr &= ~(PHYPWR_NORMAL_MASK_HSIC0 |
- PHYPWR_NORMAL_MASK_HSIC1 |
- PHYPWR_NORMAL_MASK_PHY1);
- bus_space_write_4(sc->sc_bst, sc->sc_usb2phy_bsh,
- USB_PHYPWR, phypwr);
- }
-
- /* reset both phy and link of device */
- rstcon = bus_space_read_4(sc->sc_bst, sc->sc_usb2phy_bsh,
- USB_RSTCON);
- rstcon |= RSTCON_DEVPHY_SWRST;
- bus_space_write_4(sc->sc_bst, sc->sc_usb2phy_bsh,
- USB_RSTCON, rstcon);
- DELAY(10000);
- rstcon &= ~RSTCON_DEVPHY_SWRST;
- bus_space_write_4(sc->sc_bst, sc->sc_usb2phy_bsh,
- USB_RSTCON, rstcon);
-
- if (IS_EXYNOS4X12_P()) {
- /* reset both phy and link of host */
- rstcon = bus_space_read_4(sc->sc_bst, sc->sc_usb2phy_bsh,
- USB_RSTCON);
- rstcon |= RSTCON_HOSTPHY_SWRST | RSTCON_HOSTPHYLINK_SWRST;
- bus_space_write_4(sc->sc_bst, sc->sc_usb2phy_bsh,
- USB_RSTCON, rstcon);
- DELAY(10000);
- rstcon &= ~(RSTCON_HOSTPHY_SWRST | RSTCON_HOSTPHYLINK_SWRST);
- bus_space_write_4(sc->sc_bst, sc->sc_usb2phy_bsh,
- USB_RSTCON, rstcon);
- }
-
- /* wait for everything to be initialized */
- DELAY(80000);
-}
-#endif
-
-
-#ifdef EXYNOS5
-static void
-exynos5_usb2phy_enable(struct exynos_usb_softc *sc)
-{
- /* disable phy isolation */
- exynos_usb2_set_isolation(sc, false);
-
- aprint_error_dev(sc->sc_self, "%s not implemented\n", __func__);
-}
-#endif
-
-
-static void
-exynos_usb_phy_init(struct exynos_usb_softc *sc)
-{
-#ifdef EXYNOS4
- if (IS_EXYNOS4_P())
- exynos4_usb2phy_enable(sc);
-#endif
-#ifdef EXYNOS5
- if (IS_EXYNOS5_P())
- exynos5_usb2phy_enable(sc);
- /* TBD: USB3 phy init */
-#endif
-}
-
Index: src/sys/arch/arm/samsung/exynos5_reg.h
diff -u src/sys/arch/arm/samsung/exynos5_reg.h:1.10 src/sys/arch/arm/samsung/exynos5_reg.h:1.10.4.1
--- src/sys/arch/arm/samsung/exynos5_reg.h:1.10 Wed Jun 11 14:49:50 2014
+++ src/sys/arch/arm/samsung/exynos5_reg.h Sun Jan 4 11:19:00 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: exynos5_reg.h,v 1.10 2014/06/11 14:49:50 reinoud Exp $ */
+/* $NetBSD: exynos5_reg.h,v 1.10.4.1 2015/01/04 11:19:00 martin Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -55,10 +55,19 @@
#define EXYNOS5_CORE_SIZE 0x0f000000
#define EXYNOS5_SDRAM_PBASE 0x40000000
-#define EXYNOS5_CMU_COREPART_OFFSET 0x00010000
-#define EXYNOS5_CMU_TOPPART_OFFSET 0x00020000
-#define EXYNOS5_CMU_MEMPART_OFFSET 0x00030000
+#define EXYNOS5_CMU_CORE_PART_OFFSET 0x00010000
+#define EXYNOS5_CMU_APLL 0x00010000 /* ARM core clock */
+#define EXYNOS5_CMU_MPLL 0x00014000 /* MEM cntr. clock */
+#define EXYNOS5_CMU_TOP_PART_OFFSET 0x00020000
+#define EXYNOS5_CMU_CPLL 0x00020020 /* Video hardware codec clock */
+#define EXYNOS5_CMU_DPLL 0x00020030 /* Audio and ext. interf. clock */
+#define EXYNOS5_CMU_VPLL 0x00020040 /* Dither PLL (EMI reduction) clock */
+#define EXYNOS5_CMU_GPLL 0x00020050 /* Graphic 3D proc. clock */
+#define EXYNOS5_CMU_MEM_PART_OFFSET 0x00030000
+#define EXYNOS5_CMU_BPLL 0x00030010
+#define EXYNOS5_CMU_KPLL 0x00038000
#define EXYNOS5_ALIVE_OFFSET 0x00040000
+#define EXYNOS5_PMU_OFFSET 0x00040000 /* alias */
#define EXYNOS5_SYSREG_OFFSET 0x00050000
#define EXYNOS5_TMU_OFFSET 0x00060000
#define EXYNOS5_MONOTONIC_CNT_OFFSET 0x000C0000
@@ -94,7 +103,7 @@
#define EXYNOS5_AS_A_LEFT_BUS_OFFSET 0x00CE0000
#define EXYNOS5_AS_A_RIGHT0_BUS_OFFSET 0x00CF0000
#define EXYNOS5_AS_A_DISP1_BUS_OFFSET 0x00D00000
-#define EXYNOS5_C2C_GPIO_OFFSET 0x00D10000
+#define EXYNOS5_GPIO_C2C_OFFSET 0x00D10000
#define EXYNOS5_DREXII_OFFSET 0x00DD0000
#define EXYNOS5_AS_A_EFCON_OFFSET 0x00DE0000
#define EXYNOS5_AP_C2C_OFFSET 0x00E00000
@@ -128,7 +137,7 @@
#define EXYNOS5_USB2HOST_OFFSET 0x02110000
#define EXYNOS5_USB2_HOST_EHCI_OFFSET 0x02110000
#define EXYNOS5_USB2_HOST_OHCI_OFFSET 0x02120000
-#define EXYNOS5_USB2_HOST_CTRL_OFFSET 0x02130000
+#define EXYNOS5_USB2_HOST_PHYCTRL_OFFSET 0x02130000
#define EXYNOS5_USB2_DEVICE_LINK_OFFSET 0x02140000
#define EXYNOS5_MIPI_HSI_OFFSET 0x02160000
@@ -180,7 +189,7 @@
#define EXYNOS5_I2C5_OFFSET 0x02CB0000
#define EXYNOS5_I2C6_OFFSET 0x02CC0000
#define EXYNOS5_I2C7_OFFSET 0x02CD0000
-#define EXYNOS5_I2C_HDMI_OFFSET 0x02CE0000
+#define EXYNOS5_I2CHDMI_OFFSET 0x02CE0000
#define EXYNOS5_USI_OFFSET 0x02D00000
#define EXYNOS5_TSADC_OFFSET 0x02D10000
#define EXYNOS5_SPI0_OFFSET 0x02D20000
@@ -252,6 +261,7 @@
#define EXYNOS5_SYSMMU_GSCALER1_OFFSET 0x03E90000
#define EXYNOS5_SYSMMU_GSCALER2_OFFSET 0x03EA0000
#define EXYNOS5_SYSMMU_GSCALER3_OFFSET 0x03EB0000
+#define EXYNOS5_GPIO_USB_OFFSET 0x04000000
#define EXYNOS5_AS_A_GSCALER_OFFSET 0x04220000
#define EXYNOS5_DISP1_MIX_OFFSET 0x04400000
#define EXYNOS5_DISP1_ENH_OFFSET 0x04410000
@@ -347,6 +357,75 @@
/* AUDIOCORE */
#define EXYNOS5_AUDIOCORE_VBASE (EXYNOS_CORE_VBASE + EXYNOS5_CORE_SIZE)
#define EXYNOS5_AUDIOCORE_PBASE 0x03800000 /* Audio SFR */
+#define EXYNOS5_GPIO_I2S_OFFSET (EXYNOS5_CORE_SIZE + 0x00060000)
#define EXYNOS5_AUDIOCORE_SIZE 0x00070000
+
+/* used Exynos5 USB PHY registers */
+#define USB_PHY_HOST_CTRL0 0x00
+#define HOST_CTRL0_PHY_SWRST __BIT(0)
+#define HOST_CTRL0_LINK_SWRST __BIT(1)
+#define HOST_CTRL0_UTMI_SWRST __BIT(2)
+#define HOST_CTRL0_WORDINTERFACE __BIT(3)
+#define HOST_CTRL0_FORCESUSPEND __BIT(4)
+#define HOST_CTRL0_FORCESLEEP __BIT(5)
+#define HOST_CTRL0_SIDDQ __BIT(6)
+#define HOST_CTRL0_COMMONON_N __BIT(9) /* common block configuration during suspend */
+#define HOST_CTRL0_RETENABLE __BIT(10)
+#define HOST_CTRL0_TESTBURNIN __BIT(11)
+#define HOST_CTRL0_FSEL_MASK __BITS(16, 18) /* holds FSEL_CLKSEL_ */
+#define HOST_CTRL0_REFCLKSEL_MASK __BITS(19, 20)
+#define HOST_CTRL0_REFCLKSEL_XTAL 0
+#define HOST_CTRL0_REFCLKSEL_EXTL 1
+#define HOST_CTRL0_REFCLKSEL_CLKCORE 2
+#define HOST_CTRL0_PHY_SWRST_ALL __BIT(31)
+
+#define USB_PHY_HSIC_CTRL1 0x10
+#define USB_PHY_HSIC_TUNE1 0x14
+#define USB_PHY_HSIC_CTRL2 0x20
+#define USB_PHY_HSIC_TUNE2 0x24
+
+#define HSIC_CTRL_PHY_SWRST __BIT(0)
+#define HSIC_CTRL_UTMI_SWRST __BIT(2)
+#define HSIC_CTRL_WORDINTERFACE __BIT(3)
+#define HSIC_CTRL_FORCESUSPEND __BIT(4)
+#define HSIC_CTRL_FORCESLEEP __BIT(5)
+#define HSIC_CTRL_SIDDQ __BIT(6)
+#define HSIC_CTRL_REFCLKDIV_MASK __BITS(16,22)
+#define HSIC_CTRL_REFCLKDIV_12 0x24
+#define HSIC_CTRL_REFCLKDIV_15 0x1c
+#define HSIC_CTRL_REFCLKDIV_16 0x1a
+#define HSIC_CTRL_REFCLKDIV_19_2 0x15
+#define HSIC_CTRL_REFCLKDIV_20 0x14
+#define HSIC_CTRL_REFCLKSEL_MASK __BITS(23, 24)
+#define HSIC_CTRL_REFCLKSEL_DEFAULT 2
+
+#define USB_PHY_HOST_EHCICTRL 0x30
+#define HOST_EHCICTRL_ENA_INCR16 __BIT(26)
+#define HOST_EHCICTRL_ENA_INCR8 __BIT(27)
+#define HOST_EHCICTRL_ENA_INCR4 __BIT(28)
+#define HOST_EHCICTRL_ENA_INCRXALIGN __BIT(29)
+
+#define USB_PHY_HOST_OHCICTRL 0x34
+#define HOST_OHCICTRL_CLKCK_RST __BIT(0)
+#define HOST_OHCICTRL_CNTSEL __BIT(1)
+#define HOST_OHCICTRL_APPSTARTCLK __BIT(2)
+#define HOST_OHCICTRL_SUSPLGCY __BIT(3)
+
+#define USB_PHY_OTG_SYS 0x38
+#define OTG_SYS_FORCESUSPEND __BIT(0)
+#define OTG_SYS_SIDDQ_UOTG __BIT(1)
+#define OTG_SYS_OTGDISABLE __BIT(2)
+#define OTG_SYS_FORCESLEEP __BIT(3)
+#define OTG_SYS_FSEL_MASK __BITS(4, 6) /* holds FSEL_CLKSEL_ */
+#define OTG_SYS_COMMON_ON __BIT(7)
+#define OTG_SYS_IDPULLUP_UOTG __BIT(8)
+#define OTG_SYS_REFCLKSEL_MASK __BITS(9, 10)
+#define OTG_SYS_REFCLKSEL_XTAL __SHIFTIN(OTG_SYS_REFCLKSEL_MASK, 0)
+#define OTG_SYS_REFCLKSEL_EXTL __SHIFTIN(OTG_SYS_REFCLKSEL_MASK, 1)
+#define OTG_SYS_REFCLKSEL_CLKCORE __SHIFTIN(OTG_SYS_REFCLKSEL_MASK, 2)
+#define OTG_SYS_PHY0_SWRST __BIT(12)
+#define OTG_SYS_LINK_SWRST_UOTG __BIT(13)
+#define OTG_SYS_PHYLINK_SWRST __BIT(14)
+
#endif /* _ARM_SAMSUNG_EXYNOS5_REG_H_ */
Index: src/sys/arch/arm/samsung/exynos_gpio.c
diff -u src/sys/arch/arm/samsung/exynos_gpio.c:1.6 src/sys/arch/arm/samsung/exynos_gpio.c:1.6.6.1
--- src/sys/arch/arm/samsung/exynos_gpio.c:1.6 Wed May 21 12:18:24 2014
+++ src/sys/arch/arm/samsung/exynos_gpio.c Sun Jan 4 11:19:00 2015
@@ -1,3 +1,5 @@
+/* $NetBSD: exynos_gpio.c,v 1.6.6.1 2015/01/04 11:19:00 martin Exp $ */
+
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -32,7 +34,7 @@
#include "gpio.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: exynos_gpio.c,v 1.6 2014/05/21 12:18:24 reinoud Exp $");
+__KERNEL_RCSID(1, "$NetBSD: exynos_gpio.c,v 1.6.6.1 2015/01/04 11:19:00 martin Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -168,7 +170,7 @@ static struct exynos_gpio_pin_group exyn
GPIO_GRP(4, RIGHT, 0x01C0, GPY5, 8),
GPIO_GRP(4, RIGHT, 0x01E0, GPY6, 8),
GPIO_GRP(4, RIGHT, 0x0200, ETC0, 6),
- GPIO_GRP(4, RIGHT, 0x0220, ETC6, 7),
+ GPIO_GRP(4, RIGHT, 0x0220, ETC6, 8),
GPIO_GRP(4, RIGHT, 0x0260, GPM0, 8),
GPIO_GRP(4, RIGHT, 0x0280, GPM1, 7),
GPIO_GRP(4, RIGHT, 0x02A0, GPM2, 5),
@@ -197,7 +199,121 @@ static struct exynos_gpio_pin_group exyn
#ifdef EXYNOS5
+
+/*
+ * Exynos 5250 contains 253 multi-functional input/output port pins and 160
+ * memory port pins. There are 39 general port groups and 2 memory port
+ * groups. They are:
+ *
+ * GPA0, GPA1: 14 in/out ports-2xUART with flow control, UART without flow
+ * control, and/or 2xI2C , and/or2xHS-I2C
+ *
+ * GPA2: 8 in/out ports-2xSPI, and/or I2C
+ *
+ * GPB0, GPB1: 10 in/out ports-2xI2S, and/or 2xPCM, and/or AC97, SPDIF, I2C,
+ * and/or SPI
+ *
+ * GPB2, GPB3: 8 in/out ports-PWM, I2C, and/or I2C ,and/or HS-I2C
+ *
+ * GPC0, GPC1: 11 in/out ports-1xMMC (8-bit MMC) I/F
+ *
+ * GPC2: 7 in/out ports-1xMMC (4-bit MMC) I/F
+ *
+ * GPC3, GPC4: 14 in/out ports-2xMMC (4-bit MMC) and/or 1xMMC (8-bit MMC) I/F
+ *
+ * GPD0: 4 pin/out ports-1xUART with flow control I/F
+ *
+ * GPD1: 8 pin/out ports-HSI I/F
+ *
+ * GPE0, GPE1, GPF0, GPF1, GPG0, GPG1, GPG2, GPH0, GPH1: 48 in/out ports-CAM
+ * I/F, and/or Trace I/F
+ *
+ * GPV0, GPV1, GPV2, GPV3, GPV4: 34 in/out ports-C2C I/F
+ *
+ * GPX0, 1, 2, 3: 32 in/out port-external wake-up interrupts (up-to 32-bit),
+ * and/or AUD I/F, and/or MFC I/F (GPX groups are in alive region)
+ *
+ * GPY0, GPY1, GPY2: 16 in/out ports-control signals of EBI (SROM)
+ *
+ * GPY3, GPY4, GPY5, GPY6: 32 in/out memory ports-EBI
+ *
+ * GPZ: 7 in/out ports-low power I2S and/or PCM
+ *
+ * MP1_0-MP1_10: 80 DRAM1 ports NOTE: GPIO registers do not control these
+ * ports.
+ *
+ * MP2_0-MP2_10: 80 DRAM2 ports NOTE: GPIO registers do not control these
+ * ports.
+ *
+ * ETC0, ETC5, ETC6, ETC7, ETC8: 22 in/out ETC ports-JTAG, C2C_CLK (Rx),
+ * RESET, CLOCK, USBOTG and USB3, C2C_CLK (Tx)
+ */
+
static struct exynos_gpio_pin_group exynos5_pin_groups[] = {
+ GPIO_GRP(5, LEFT, 0x0000, GPA0, 8),
+ GPIO_GRP(5, LEFT, 0x0020, GPA1, 6),
+ GPIO_GRP(5, LEFT, 0x0040, GPA2, 8),
+ GPIO_GRP(5, LEFT, 0x0060, GPB0, 5),
+ GPIO_GRP(5, LEFT, 0x0080, GPB1, 5),
+ GPIO_GRP(5, LEFT, 0x00A0, GPB2, 4),
+ GPIO_GRP(5, LEFT, 0x00C0, GPB3, 4),
+ GPIO_GRP(5, LEFT, 0x00E0, GPC0, 7),
+ GPIO_GRP(5, LEFT, 0x0100, GPC1, 4),
+ GPIO_GRP(5, LEFT, 0x0120, GPC2, 7),
+ GPIO_GRP(5, LEFT, 0x0140, GPC3, 7),
+ GPIO_GRP(5, LEFT, 0x0160, GPD0, 4),
+ GPIO_GRP(5, LEFT, 0x0180, GPD1, 8),
+ GPIO_GRP(5, LEFT, 0x01A0, GPY0, 6),
+ GPIO_GRP(5, LEFT, 0x01C0, GPY1, 4),
+ GPIO_GRP(5, LEFT, 0x01E0, GPY2, 6),
+ GPIO_GRP(5, LEFT, 0x0200, GPY3, 8),
+ GPIO_GRP(5, LEFT, 0x0220, GPY4, 8),
+ GPIO_GRP(5, LEFT, 0x0240, GPY5, 8),
+ GPIO_GRP(5, LEFT, 0x0260, GPY6, 8),
+ GPIO_GRP(5, LEFT, 0x0280, ETC0, 6),
+ GPIO_GRP(5, LEFT, 0x02A0, ETC6, 7),
+ GPIO_GRP(5, LEFT, 0x02C0, ETC7, 5),
+ GPIO_GRP(5, LEFT, 0x02E0, GPC4, 7),
+ /* EXTINT skipped */
+ GPIO_GRP(5, LEFT, 0x0C00, GPX0, 8),
+ GPIO_GRP(5, LEFT, 0x0C20, GPX1, 8),
+ GPIO_GRP(5, LEFT, 0x0C40, GPX2, 8),
+ GPIO_GRP(5, LEFT, 0x0C60, GPX3, 8),
+ /* EXTINT skipped */
+
+ GPIO_GRP(5, RIGHT, 0x0000, GPE0, 8),
+ GPIO_GRP(5, RIGHT, 0x0020, GPE1, 2),
+ GPIO_GRP(5, RIGHT, 0x0040, GPF0, 4),
+ GPIO_GRP(5, RIGHT, 0x0060, GPF1, 4),
+ GPIO_GRP(5, RIGHT, 0x0080, GPG0, 8),
+ GPIO_GRP(5, RIGHT, 0x00A0, GPG1, 8),
+ GPIO_GRP(5, RIGHT, 0x00C0, GPG2, 2),
+ GPIO_GRP(5, RIGHT, 0x00E0, GPH0, 4),
+ GPIO_GRP(5, RIGHT, 0x0100, GPH1, 8),
+ /* EXTINT skipped */
+
+ GPIO_GRP(5, USB, 0x0000, GPJ0, 8), // unknown num bits
+ GPIO_GRP(5, USB, 0x0020, GPJ1, 8), // unknown num bits
+ GPIO_GRP(5, USB, 0x0040, GPJ2, 8), // unknown num bits
+ GPIO_GRP(5, USB, 0x0060, GPJ3, 8), // unknown num bits
+ GPIO_GRP(5, USB, 0x0080, GPJ4, 8), // unknown num bits
+ GPIO_GRP(5, USB, 0x00A0, GPK0, 8), // unknown num bits
+ GPIO_GRP(5, USB, 0x00C0, GPK1, 8), // unknown num bits
+ GPIO_GRP(5, USB, 0x00E0, GPK2, 8), // unknown num bits
+ GPIO_GRP(5, USB, 0x0100, GPK3, 8), // unknown num bits
+ /* unknown bits skipped */
+
+ GPIO_GRP(5, C2C, 0x0000, GPV0, 8),
+ GPIO_GRP(5, C2C, 0x0020, GPV1, 8),
+ GPIO_GRP(5, C2C, 0x0040, ETC5, 2),
+ GPIO_GRP(5, C2C, 0x0060, GPV2, 8),
+ GPIO_GRP(5, C2C, 0x0080, GPV3, 8),
+ GPIO_GRP(5, C2C, 0x00A0, ETC8, 2),
+ GPIO_GRP(5, C2C, 0x00C0, GPV4, 2),
+ /* EXTINT skipped */
+
+ GPIO_GRP(5, I2S, 0x0000, GPZ, 7),
+ /* EXTINT skipped */
};
#endif
@@ -223,8 +339,10 @@ CFATTACH_DECL_NEW(exynos_gpio, sizeof(st
static int
exynos_gpio_match(device_t parent, cfdata_t cf, void *aux)
{
+#ifdef DIAGNOSTIC
struct exyo_attach_args * const exyoaa = aux;
struct exyo_locators *loc = &exyoaa->exyo_loc;
+#endif
/* no locators expected */
KASSERT(loc->loc_offset == 0);
@@ -263,7 +381,7 @@ exynos_gpio_config_pins(device_t self)
/* if no pins available, don't proceed */
if (pin_count == 0)
return;
-
+
/* allocate pin data */
pins = kmem_zalloc(sizeof(gpio_pin_t) * pin_count, KM_SLEEP);
KASSERT(pins);
Index: src/sys/arch/arm/samsung/exynos_i2c.c
diff -u src/sys/arch/arm/samsung/exynos_i2c.c:1.1 src/sys/arch/arm/samsung/exynos_i2c.c:1.1.4.1
--- src/sys/arch/arm/samsung/exynos_i2c.c:1.1 Wed May 21 12:19:59 2014
+++ src/sys/arch/arm/samsung/exynos_i2c.c Sun Jan 4 11:19:00 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: exynos_i2c.c,v 1.1 2014/05/21 12:19:59 reinoud Exp $ */
+/* $NetBSD: exynos_i2c.c,v 1.1.4.1 2015/01/04 11:19:00 martin Exp $ */
/*
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -36,7 +36,7 @@
#include "exynos_iic.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: exynos_i2c.c,v 1.1 2014/05/21 12:19:59 reinoud Exp $");
+__KERNEL_RCSID(0, "$NetBSD: exynos_i2c.c,v 1.1.4.1 2015/01/04 11:19:00 martin Exp $");
#include <sys/param.h>
@@ -108,8 +108,10 @@ CFATTACH_DECL_NEW(exynos_iic, sizeof(str
static int
exynos_iic_match(device_t self, cfdata_t cf, void *aux)
{
+#ifdef DIAGNOSTIC
struct exyo_attach_args *exyoaa = aux;
struct exyo_locators *loc = &exyoaa->exyo_loc;
+#endif
int i;
/* no locators expected */
@@ -224,7 +226,7 @@ exynos_iic_attach_i2cbus(struct exynos_i
i2c_cntr->ic_initiate_xfer = exynos_iic_initiate_xfer;
i2c_cntr->ic_read_byte = exynos_iic_read_byte;
i2c_cntr->ic_write_byte = exynos_iic_write_byte;
-
+
exynos_gpio_pinset_acquire(pinset);
if (ei2c_sc->isc_isgpio) {
/* get sda and slc pins */
@@ -287,7 +289,7 @@ exynos_iic_bb_set_dir(void *cookie, uint
flags = GPIO_PIN_INPUT | GPIO_PIN_TRISTATE;
i2c_sc->isc_sda_is_output = ((bits & EXYNOS_IIC_BB_SDA_OUT) != 0);
- if (i2c_sc->isc_sda_is_output)
+ if (i2c_sc->isc_sda_is_output)
flags = GPIO_PIN_OUTPUT | GPIO_PIN_TRISTATE;
exynos_gpio_pindata_ctl(&i2c_sc->isc_sda, flags);
@@ -341,7 +343,7 @@ exynos_iic_send_start(void *cookie, int
return EINVAL;
}
-static int
+static int
exynos_iic_send_stop(void *cookie, int flags)
{
struct exynos_iic_dev_softc *i2c_sc = cookie;
@@ -352,7 +354,7 @@ exynos_iic_send_stop(void *cookie, int f
return EINVAL;
}
-static int
+static int
exynos_iic_initiate_xfer(void *cookie, i2c_addr_t addr, int flags)
{
struct exynos_iic_dev_softc *i2c_sc = cookie;
@@ -376,7 +378,7 @@ exynos_iic_read_byte(void *cookie, uint8
return EINVAL;
}
-static int
+static int
exynos_iic_write_byte(void *cookie, uint8_t byte, int flags)
{
struct exynos_iic_dev_softc *i2c_sc = cookie;
Index: src/sys/arch/arm/samsung/exynos_intr.h
diff -u src/sys/arch/arm/samsung/exynos_intr.h:1.1 src/sys/arch/arm/samsung/exynos_intr.h:1.1.8.1
--- src/sys/arch/arm/samsung/exynos_intr.h:1.1 Sun Apr 13 02:26:26 2014
+++ src/sys/arch/arm/samsung/exynos_intr.h Sun Jan 4 11:19:00 2015
@@ -1,3 +1,5 @@
+/* $NetBSD: exynos_intr.h,v 1.1.8.1 2015/01/04 11:19:00 martin Exp $ */
+
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
* All rights reserved.
Index: src/sys/arch/arm/samsung/exynos_smc.S
diff -u src/sys/arch/arm/samsung/exynos_smc.S:1.1 src/sys/arch/arm/samsung/exynos_smc.S:1.1.8.1
--- src/sys/arch/arm/samsung/exynos_smc.S:1.1 Sun Apr 13 02:26:26 2014
+++ src/sys/arch/arm/samsung/exynos_smc.S Sun Jan 4 11:19:00 2015
@@ -1,4 +1,5 @@
-/* $NetBSD: exynos_smc.S,v 1.1 2014/04/13 02:26:26 matt Exp $ */
+/* $NetBSD: exynos_smc.S,v 1.1.8.1 2015/01/04 11:19:00 martin Exp $ */
+
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -32,8 +33,10 @@
#include <arm/asm.h>
#include <arm/armreg.h>
-RCSID("$NetBSD: exynos_smc.S,v 1.1 2014/04/13 02:26:26 matt Exp $")
+RCSID("$NetBSD: exynos_smc.S,v 1.1.8.1 2015/01/04 11:19:00 martin Exp $")
+ .arch armv7-a
+ .arch_extension sec
/*
* void
* exynos_smc(uint32_t cmd, uint32_t arg1, uint32_t arg2, uint32_t arg3)
Index: src/sys/arch/arm/samsung/mct_reg.h
diff -u src/sys/arch/arm/samsung/mct_reg.h:1.1 src/sys/arch/arm/samsung/mct_reg.h:1.1.8.1
--- src/sys/arch/arm/samsung/mct_reg.h:1.1 Sun Apr 13 02:26:26 2014
+++ src/sys/arch/arm/samsung/mct_reg.h Sun Jan 4 11:19:00 2015
@@ -1,4 +1,5 @@
-/* $NetBSD */
+/* $NetBSD: mct_reg.h,v 1.1.8.1 2015/01/04 11:19:00 martin Exp $ */
+
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
* All rights reserved.
Index: src/sys/arch/arm/samsung/smc.h
diff -u src/sys/arch/arm/samsung/smc.h:1.1 src/sys/arch/arm/samsung/smc.h:1.1.8.1
--- src/sys/arch/arm/samsung/smc.h:1.1 Sun Apr 13 02:26:26 2014
+++ src/sys/arch/arm/samsung/smc.h Sun Jan 4 11:19:00 2015
@@ -1,4 +1,5 @@
-/* $NetBSD: smc.h,v 1.1 2014/04/13 02:26:26 matt Exp $ */
+/* $NetBSD: smc.h,v 1.1.8.1 2015/01/04 11:19:00 martin Exp $ */
+
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
* All rights reserved.
Index: src/sys/arch/arm/samsung/exynos_io.c
diff -u src/sys/arch/arm/samsung/exynos_io.c:1.6 src/sys/arch/arm/samsung/exynos_io.c:1.6.8.1
--- src/sys/arch/arm/samsung/exynos_io.c:1.6 Wed May 14 09:03:09 2014
+++ src/sys/arch/arm/samsung/exynos_io.c Sun Jan 4 11:19:00 2015
@@ -1,3 +1,5 @@
+/* $NetBSD: exynos_io.c,v 1.6.8.1 2015/01/04 11:19:00 martin Exp $ */
+
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -34,7 +36,7 @@
#include "opt_exynos.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: exynos_io.c,v 1.6 2014/05/14 09:03:09 reinoud Exp $");
+__KERNEL_RCSID(1, "$NetBSD: exynos_io.c,v 1.6.8.1 2015/01/04 11:19:00 martin Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -139,6 +141,10 @@ exyo_attach(device_t parent, device_t se
aprint_naive(": Exynos %x\n", product_id);
aprint_normal(": Exynos %x\n", product_id);
+ /* add sysctl nodes */
+ exynos_sysctl_cpufreq_init();
+
+ /* add all children */
#if defined(EXYNOS4)
if (IS_EXYNOS4_P()) {
l = exynos4_locinfo.locators;
Index: src/sys/arch/arm/samsung/exynos_io.h
diff -u src/sys/arch/arm/samsung/exynos_io.h:1.4 src/sys/arch/arm/samsung/exynos_io.h:1.4.6.1
--- src/sys/arch/arm/samsung/exynos_io.h:1.4 Wed May 21 13:02:46 2014
+++ src/sys/arch/arm/samsung/exynos_io.h Sun Jan 4 11:19:00 2015
@@ -1,3 +1,5 @@
+/* $NetBSD: exynos_io.h,v 1.4.6.1 2015/01/04 11:19:00 martin Exp $ */
+
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -45,8 +47,6 @@ extern const struct exyo_locinfo exynos4
extern const struct exyo_locinfo exynos4_i2c_locinfo;
extern const struct exyo_locinfo exynos5_locinfo;
extern const struct exyo_locinfo exynos5_i2c_locinfo;
-extern const struct exyo_usb_locinfo exynos4_usb_locinfo;
-extern const struct exyo_usb_locinfo exynos5_usb_locinfo;
/* XXXNH needed? */
#define NOPORT EXYOCF_PORT_DEFAULT
Index: src/sys/arch/arm/samsung/exynos_soc.c
diff -u src/sys/arch/arm/samsung/exynos_soc.c:1.14 src/sys/arch/arm/samsung/exynos_soc.c:1.14.4.1
--- src/sys/arch/arm/samsung/exynos_soc.c:1.14 Wed Jun 11 05:54:54 2014
+++ src/sys/arch/arm/samsung/exynos_soc.c Sun Jan 4 11:19:00 2015
@@ -1,4 +1,5 @@
-/* $NetBSD: exynos_soc.c,v 1.14 2014/06/11 05:54:54 matt Exp $ */
+/* $NetBSD: exynos_soc.c,v 1.14.4.1 2015/01/04 11:19:00 martin Exp $ */
+
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -33,7 +34,7 @@
#define _ARM32_BUS_DMA_PRIVATE
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: exynos_soc.c,v 1.14 2014/06/11 05:54:54 matt Exp $");
+__KERNEL_RCSID(1, "$NetBSD: exynos_soc.c,v 1.14.4.1 2015/01/04 11:19:00 martin Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -61,13 +62,82 @@ __KERNEL_RCSID(1, "$NetBSD: exynos_soc.c
/* XXXNH */
#include <evbarm/odroid/platform.h>
-bus_space_handle_t exynos_core_bsh;
-bus_space_handle_t exynos_audiocore_bsh;
/* these variables are retrieved in start.S and stored in .data */
uint32_t exynos_soc_id = 0;
uint32_t exynos_pop_id = 0;
+/* cpu frequencies */
+struct cpu_freq {
+ uint64_t freq;
+ int P;
+ int M;
+ int S;
+};
+
+
+#ifdef EXYNOS4
+const struct cpu_freq cpu_freq_settings_exynos4[] = {
+ { 200, 3, 100, 2},
+ { 300, 4, 200, 2},
+ { 400, 3, 100, 1},
+ { 500, 3, 125, 1},
+ { 600, 4, 200, 1},
+ { 700, 3, 175, 1},
+ { 800, 3, 100, 0},
+ { 900, 4, 150, 0},
+ {1000, 3, 125, 0},
+ {1100, 6, 275, 0},
+ {1200, 4, 200, 0},
+ {1300, 6, 325, 0},
+ {1400, 3, 175, 0},
+ {1600, 3, 200, 0},
+// {1704, 3, 213, 0},
+// {1800, 4, 300, 0},
+// {1920, 3, 240, 0},
+// {2000, 3, 250, 0},
+};
+#endif
+
+
+#ifdef EXYNOS5
+#define EXYNOS5_DEFAULT_ENTRY 7
+const struct cpu_freq cpu_freq_settings_exynos5[] = {
+ { 200, 3, 100, 2},
+ { 333, 4, 222, 2},
+ { 400, 3, 100, 1},
+ { 533, 12, 533, 1},
+ { 600, 4, 200, 1},
+ { 667, 7, 389, 1},
+ { 800, 3, 100, 0},
+ { 900, 4, 150, 0},
+ {1000, 3, 125, 0},
+ {1066, 12, 533, 0},
+ {1200, 3, 150, 0},
+ {1400, 3, 175, 0},
+ {1600, 3, 200, 0},
+};
+#endif
+
+static struct cpu_freq const *cpu_freq_settings = NULL;
+static int ncpu_freq_settings = 0;
+
+static int cpu_freq_target = 0;
+#define NFRQS 18
+static char sysctl_cpu_freqs_txt[NFRQS*5];
+
+bus_space_handle_t exynos_core_bsh;
+bus_space_handle_t exynos_audiocore_bsh;
+
+bus_space_handle_t exynos_wdt_bsh;
+bus_space_handle_t exynos_pmu_bsh;
+bus_space_handle_t exynos_cmu_bsh;
+bus_space_handle_t exynos_cmu_apll_bsh;
+bus_space_handle_t exynos_sysreg_bsh;
+
+
+static int sysctl_cpufreq_target(SYSCTLFN_ARGS);
+static int sysctl_cpufreq_current(SYSCTLFN_ARGS);
/*
* the early serial console
@@ -137,8 +207,9 @@ exynos_cpu_boot(int cpu)
}
+#ifdef EXYNOS4
/*
- * The latency values used below are `magic' and probably chosen empiricaly.
+ * The latency values used below are `magic' and probably chosen empirically.
* For the 4210 variant the data latency is lower, a 0x110. This is currently
* not enforced.
*
@@ -147,7 +218,7 @@ exynos_cpu_boot(int cpu)
*/
int
-exynos_l2cc_init(void)
+exynos4_l2cc_init(void)
{
const uint32_t tag_latency = 0x110;
const uint32_t data_latency = IS_EXYNOS4410_P() ? 0x110 : 0x120;
@@ -204,40 +275,283 @@ exynos_l2cc_init(void)
return 0;
}
+#endif
#endif /* ARM_TRUSTZONE_FIRMWARE */
void
-exynos_bootstrap(vaddr_t iobase, vaddr_t uartbase)
+exynos_sysctl_cpufreq_init(void)
{
+ const struct sysctlnode *node, *cpunode, *freqnode;
+ char *cpos;
+ int i, val;
int error;
- size_t core_size, audiocore_size;
- size_t audiocore_pbase, audiocore_vbase;
-#ifdef EXYNOS4
- if (IS_EXYNOS4_P()) {
- core_size = EXYNOS4_CORE_SIZE;
- audiocore_size = EXYNOS4_AUDIOCORE_SIZE;
- audiocore_pbase = EXYNOS4_AUDIOCORE_PBASE;
- audiocore_vbase = EXYNOS4_AUDIOCORE_VBASE;
+ memset(sysctl_cpu_freqs_txt, (int) ' ', sizeof(sysctl_cpu_freqs_txt));
+ cpos = sysctl_cpu_freqs_txt;
+ for (i = 0; i < ncpu_freq_settings; i++) {
+ val = cpu_freq_settings[i].freq;
+ snprintf(cpos, 6, "%d ", val);
+ cpos += (val < 1000) ? 4 : 5;
+ }
+ *cpos = 0;
+
+ error = sysctl_createv(NULL, 0, NULL, &node,
+ CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL,
+ NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL);
+ if (error)
+ printf("couldn't create `machdep' node\n");
+
+ error = sysctl_createv(NULL, 0, &node, &cpunode,
+ 0, CTLTYPE_NODE, "cpu", NULL,
+ NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL);
+ if (error)
+ printf("couldn't create `cpu' node\n");
+
+ error = sysctl_createv(NULL, 0, &cpunode, &freqnode,
+ 0, CTLTYPE_NODE, "frequency", NULL,
+ NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL);
+ if (error)
+ printf("couldn't create `frequency' node\n");
+
+ error = sysctl_createv(NULL, 0, &freqnode, &node,
+ CTLFLAG_READWRITE, CTLTYPE_INT, "target", NULL,
+ sysctl_cpufreq_target, 0, &cpu_freq_target, 0,
+ CTL_CREATE, CTL_EOL);
+ if (error)
+ printf("couldn't create `target' node\n");
+
+ error = sysctl_createv(NULL, 0, &freqnode, &node,
+ 0, CTLTYPE_INT, "current", NULL,
+ sysctl_cpufreq_current, 0, NULL, 0,
+ CTL_CREATE, CTL_EOL);
+ if (error)
+ printf("couldn't create `current' node\n");
+
+ error = sysctl_createv(NULL, 0, &freqnode, &node,
+ CTLFLAG_READONLY, CTLTYPE_STRING, "available", NULL,
+ NULL, 0, sysctl_cpu_freqs_txt, 0,
+ CTL_CREATE, CTL_EOL);
+ if (error)
+ printf("couldn't create `available' node\b");
+}
+
+
+uint64_t
+exynos_get_cpufreq(void)
+{
+ uint32_t regval;
+ uint32_t freq;
+
+ regval = bus_space_read_4(&exynos_bs_tag, exynos_cmu_apll_bsh,
+ PLL_CON0_OFFSET);
+ freq = PLL_FREQ(EXYNOS_F_IN_FREQ, regval);
+
+ return freq;
+}
+
+
+static void
+exynos_set_cpufreq(const struct cpu_freq *freqreq)
+{
+ struct cpu_info *ci;
+ uint32_t regval;
+ int M, P, S;
+ int cii;
+
+ M = freqreq->M;
+ P = freqreq->P;
+ S = freqreq->S;
+
+ regval = __SHIFTIN(M, PLL_CON0_M) |
+ __SHIFTIN(P, PLL_CON0_P) |
+ __SHIFTIN(S, PLL_CON0_S);
+
+ /* enable PPL and write config */
+ regval |= PLL_CON0_ENABLE;
+ bus_space_write_4(&exynos_bs_tag, exynos_cmu_apll_bsh, PLL_CON0_OFFSET,
+ regval);
+
+ /* update our cycle counter i.e. our CPU frequency for all CPUs */
+ for (CPU_INFO_FOREACH(cii, ci)) {
+ ci->ci_data.cpu_cc_freq = exynos_get_cpufreq();
}
+}
+
+
+static int
+sysctl_cpufreq_target(SYSCTLFN_ARGS)
+{
+ struct sysctlnode node;
+ uint32_t t, curfreq, minfreq, maxfreq;
+ int i, best_i, diff;
+ int error;
+
+ curfreq = exynos_get_cpufreq() / (1000*1000);
+ t = *(int *)rnode->sysctl_data;
+ if (t == 0)
+ t = curfreq;
+
+ node = *rnode;
+ node.sysctl_data = &t;
+ error = sysctl_lookup(SYSCTLFN_CALL(&node));
+ if (error || newp == NULL)
+ return error;
+
+ minfreq = cpu_freq_settings[0].freq;
+ maxfreq = cpu_freq_settings[ncpu_freq_settings-1].freq;
+
+ if ((t < minfreq) || (t > maxfreq))
+ return EINVAL;
+
+ if (t == curfreq) {
+ *(int *)rnode->sysctl_data = t;
+ return 0;
+ }
+
+ diff = maxfreq;
+ best_i = -1;
+ for (i = 0; i < ncpu_freq_settings; i++) {
+ if (abs(t - cpu_freq_settings[i].freq) <= diff) {
+ diff = labs(t - cpu_freq_settings[i].freq);
+ best_i = i;
+ }
+ }
+ if (best_i < 0)
+ return EINVAL;
+
+ exynos_set_cpufreq(&cpu_freq_settings[best_i]);
+
+ *(int *)rnode->sysctl_data = t;
+ return 0;
+}
+
+
+static int
+sysctl_cpufreq_current(SYSCTLFN_ARGS)
+{
+ struct sysctlnode node = *rnode;
+ uint32_t freq;
+
+ freq = exynos_get_cpufreq() / (1000*1000);
+ node.sysctl_data = &freq;
+
+ return sysctl_lookup(SYSCTLFN_CALL(&node));
+}
+
+
+#ifdef VERBOSE_INIT_ARM
+#define DUMP_PLL(v, var) \
+ reg = EXYNOS##v##_CMU_##var + PLL_CON0_OFFSET;\
+ regval = bus_space_read_4(&exynos_bs_tag, exynos_cmu_bsh, reg); \
+ freq = PLL_FREQ(EXYNOS_F_IN_FREQ, regval); \
+ printf("%8s at %d Mhz\n", #var, freq/(1000*1000));
+
+
+static void
+exynos_dump_clocks(void)
+{
+ uint32_t reg = 0;
+ uint32_t regval;
+ uint32_t freq;
+
+ printf("Initial PLL settings\n");
+#ifdef EXYNOS4
+ DUMP_PLL(4, APLL);
+ DUMP_PLL(4, MPLL);
+ DUMP_PLL(4, EPLL);
+ DUMP_PLL(4, VPLL);
+#endif
+#ifdef EXYNOS5
+ DUMP_PLL(5, APLL);
+ DUMP_PLL(5, MPLL);
+ DUMP_PLL(5, KPLL);
+ DUMP_PLL(5, DPLL);
+ DUMP_PLL(5, VPLL);
+ DUMP_PLL(5, CPLL);
+ DUMP_PLL(5, GPLL);
+ DUMP_PLL(5, BPLL);
+#endif
+}
+#undef DUMP_PLL
#endif
+
+/* XXX clock stuff needs major work XXX */
+
+void
+exynos_clocks_bootstrap(void)
+{
+ KASSERT(ncpu_freq_settings != 0);
+ KASSERT(ncpu_freq_settings < NFRQS);
+ int fsel;
+
+#ifdef VERBOSE_INIT_ARM
+ exynos_dump_clocks();
+#endif
+
+ /* set (max) cpufreq */
+ fsel = ncpu_freq_settings-1;
+
#ifdef EXYNOS5
- if (IS_EXYNOS5_P()) {
- core_size = EXYNOS5_CORE_SIZE;
- audiocore_size = EXYNOS5_AUDIOCORE_SIZE;
- audiocore_pbase = EXYNOS5_AUDIOCORE_PBASE;
- audiocore_vbase = EXYNOS5_AUDIOCORE_VBASE;
- }
+ /* XXX BUGFIX selecting freq on E5 goes wrong for now XXX */
+ fsel = EXYNOS5_DEFAULT_ENTRY;
#endif
+ exynos_set_cpufreq(&cpu_freq_settings[fsel]);
+
+ /* set external USB frequency to XCLKOUT */
+ exynos_init_clkout_for_usb();
+}
+
+
+void
+exynos_bootstrap(vaddr_t iobase, vaddr_t uartbase)
+{
+ int error;
+ size_t core_size, audiocore_size;
+ bus_addr_t audiocore_pbase;
+ bus_addr_t audiocore_vbase __diagused;
+ bus_addr_t exynos_wdt_offset;
+ bus_addr_t exynos_pmu_offset;
+ bus_addr_t exynos_sysreg_offset;
+ bus_addr_t exynos_cmu_apll_offset;
+
/* set up early console so we can use printf() and friends */
#ifdef EXYNOS_CONSOLE_EARLY
uart_base = (volatile uint8_t *) uartbase;
cn_tab = &exynos_earlycons;
printf("Exynos early console operational\n\n");
#endif
+
+#ifdef EXYNOS4
+ core_size = EXYNOS4_CORE_SIZE;
+ audiocore_size = EXYNOS4_AUDIOCORE_SIZE;
+ audiocore_pbase = EXYNOS4_AUDIOCORE_PBASE;
+ audiocore_vbase = EXYNOS4_AUDIOCORE_VBASE;
+ exynos_wdt_offset = EXYNOS4_WDT_OFFSET;
+ exynos_pmu_offset = EXYNOS4_PMU_OFFSET;
+ exynos_sysreg_offset = EXYNOS4_SYSREG_OFFSET;
+ exynos_cmu_apll_offset = EXYNOS4_CMU_APLL;
+
+ cpu_freq_settings = cpu_freq_settings_exynos4;
+ ncpu_freq_settings = __arraycount(cpu_freq_settings_exynos4);
+#endif
+
+#ifdef EXYNOS5
+ core_size = EXYNOS5_CORE_SIZE;
+ audiocore_size = EXYNOS5_AUDIOCORE_SIZE;
+ audiocore_pbase = EXYNOS5_AUDIOCORE_PBASE;
+ audiocore_vbase = EXYNOS5_AUDIOCORE_VBASE;
+ exynos_wdt_offset = EXYNOS5_WDT_OFFSET;
+ exynos_pmu_offset = EXYNOS5_PMU_OFFSET;
+ exynos_sysreg_offset = EXYNOS5_SYSREG_OFFSET;
+ exynos_cmu_apll_offset = EXYNOS5_CMU_APLL;
+
+ cpu_freq_settings = cpu_freq_settings_exynos5;
+ ncpu_freq_settings = __arraycount(cpu_freq_settings_exynos5);
+#endif
+
/* map in the exynos io registers */
error = bus_space_map(&exynos_bs_tag, EXYNOS_CORE_PBASE,
core_size, 0, &exynos_core_bsh);
@@ -253,6 +567,33 @@ exynos_bootstrap(vaddr_t iobase, vaddr_t
__func__, error);
KASSERT(exynos_audiocore_bsh == audiocore_vbase);
+ /* map in commonly used subregions and common used register banks */
+ error = bus_space_subregion(&exynos_bs_tag, exynos_core_bsh,
+ exynos_wdt_offset, EXYNOS_BLOCK_SIZE, &exynos_wdt_bsh);
+ if (error)
+ panic("%s: failed to subregion wdt registers: %d",
+ __func__, error);
+
+ error = bus_space_subregion(&exynos_bs_tag, exynos_core_bsh,
+ exynos_pmu_offset, EXYNOS_BLOCK_SIZE, &exynos_pmu_bsh);
+ if (error)
+ panic("%s: failed to subregion pmu registers: %d",
+ __func__, error);
+
+ exynos_cmu_bsh = exynos_core_bsh;
+ bus_space_subregion(&exynos_bs_tag, exynos_core_bsh,
+ exynos_sysreg_offset, EXYNOS_BLOCK_SIZE,
+ &exynos_sysreg_bsh);
+ if (error)
+ panic("%s: failed to subregion sysreg registers: %d",
+ __func__, error);
+
+ error = bus_space_subregion(&exynos_bs_tag, exynos_cmu_bsh,
+ exynos_cmu_apll_offset, 0xfff, &exynos_cmu_apll_bsh);
+ if (error)
+ panic("%s: failed to subregion cmu apll registers: %d",
+ __func__, error);
+
/* init bus dma tags */
exynos_dma_bootstrap(physmem * PAGE_SIZE);
@@ -268,8 +609,8 @@ exynos_device_register(device_t self, vo
/*
* XXX KLUDGE ALERT XXX
* The iot mainbus supplies is completely wrong since it scales
- * addresses by 2. The simpliest remedy is to replace with our
- * bus space used for the armcore regisers (which armperiph uses).
+ * addresses by 2. The simplest remedy is to replace with our
+ * bus space used for the armcore registers (which armperiph uses).
*/
struct mainbus_attach_args * const mb = aux;
mb->mb_iot = &exynos_bs_tag;
@@ -284,7 +625,7 @@ exynos_device_register(device_t self, vo
extern uint32_t exynos_soc_id;
switch (EXYNOS_PRODUCT_ID(exynos_soc_id)) {
-#if defined(EXYNOS5)
+#ifdef EXYNOS5
case 0xe5410:
/* offsets not changed on matt's request */
#if 0
@@ -294,7 +635,7 @@ exynos_device_register(device_t self, vo
#endif
break;
#endif
-#if defined(EXYNOS4)
+#ifdef EXYNOS4
case 0xe4410:
case 0xe4412: {
struct mpcore_attach_args * const mpcaa = aux;
@@ -341,3 +682,324 @@ exynos_device_register_post_config(devic
exyo_device_register_post_config(self, aux);
}
+
+/*
+ * USB power SoC dependent handling
+ */
+
+#ifdef EXYNOS4
+static struct exynos_gpio_pinset e4_uhost_pwr_pinset = {
+ .pinset_group = "ETC6",
+ .pinset_func = 0,
+ .pinset_mask = __BIT(6) | __BIT(7),
+};
+#endif
+
+
+#ifdef EXYNOS5
+static struct exynos_gpio_pinset e5_uhost_pwr_pinset = {
+ .pinset_group = "ETC6",
+ .pinset_func = 0,
+ .pinset_mask = __BIT(5) | __BIT(6),
+};
+static struct exynos_gpio_pinset e5_usb3_bus0_pinset = {
+ .pinset_group = "GPK3",
+ .pinset_func = 2,
+ .pinset_mask = __BIT(0) | __BIT(1) | __BIT(3),
+};
+static struct exynos_gpio_pinset e5_usb3_bus1_pinset = {
+ .pinset_group = "GPK2",
+ .pinset_func = 2,
+ .pinset_mask = __BIT(4) | __BIT(5) | __BIT(7),
+};
+#endif
+
+
+void
+exynos_usb_soc_powerup(void)
+{
+ struct exynos_gpio_pindata XuhostOVERCUR;
+ struct exynos_gpio_pindata XuhostPWREN;
+
+#ifdef EXYNOS4
+ exynos_gpio_pinset_acquire(&e4_uhost_pwr_pinset);
+ exynos_gpio_pinset_to_pindata(&e4_uhost_pwr_pinset, 6, &XuhostPWREN);
+ exynos_gpio_pinset_to_pindata(&e4_uhost_pwr_pinset, 7, &XuhostOVERCUR);
+
+ /* enable power and set Xuhost OVERCUR to inactive by pulling it up */
+ exynos_gpio_pindata_ctl(&XuhostPWREN, GPIO_PIN_PULLUP);
+ exynos_gpio_pindata_ctl(&XuhostOVERCUR, GPIO_PIN_PULLUP);
+ DELAY(80000);
+#endif
+#ifdef EXYNOS5
+ if (IS_EXYNOS5410_P()) {
+ struct exynos_gpio_pindata Xovercur2, Xovercur3;
+ struct exynos_gpio_pindata Xvbus;
+
+ /* BUS 0 */
+ exynos_gpio_pinset_acquire(&e5_usb3_bus0_pinset);
+ exynos_gpio_pinset_to_pindata(&e5_usb3_bus0_pinset, 0, &Xovercur2);
+ exynos_gpio_pinset_to_pindata(&e5_usb3_bus0_pinset, 1, &Xovercur3);
+ exynos_gpio_pinset_to_pindata(&e5_usb3_bus0_pinset, 3, &Xvbus);
+
+ /* enable power and set overcur inactive by pulling them up */
+ exynos_gpio_pindata_ctl(&Xvbus, GPIO_PIN_PULLUP);
+ exynos_gpio_pindata_ctl(&Xovercur2, GPIO_PIN_PULLUP);
+ exynos_gpio_pindata_ctl(&Xovercur3, GPIO_PIN_PULLUP);
+
+ /* BUS 1 */
+ exynos_gpio_pinset_acquire(&e5_usb3_bus1_pinset);
+ exynos_gpio_pinset_to_pindata(&e5_usb3_bus1_pinset, 4, &Xovercur2);
+ exynos_gpio_pinset_to_pindata(&e5_usb3_bus1_pinset, 5, &Xovercur3);
+ exynos_gpio_pinset_to_pindata(&e5_usb3_bus1_pinset, 7, &Xvbus);
+
+ /* enable power and set overcur inactive by pulling them up */
+ exynos_gpio_pindata_ctl(&Xvbus, GPIO_PIN_PULLUP);
+ exynos_gpio_pindata_ctl(&Xovercur2, GPIO_PIN_PULLUP);
+ exynos_gpio_pindata_ctl(&Xovercur3, GPIO_PIN_PULLUP);
+
+ /* enable power to the hub */
+ exynos_gpio_pinset_acquire(&e5_uhost_pwr_pinset);
+ exynos_gpio_pinset_to_pindata(&e5_uhost_pwr_pinset, 5, &XuhostPWREN);
+ exynos_gpio_pinset_to_pindata(&e5_uhost_pwr_pinset, 6, &XuhostOVERCUR);
+
+ /* enable power and set Xuhost OVERCUR to inactive by pulling it up */
+ exynos_gpio_pindata_ctl(&XuhostPWREN, GPIO_PIN_PULLUP);
+ exynos_gpio_pindata_ctl(&XuhostOVERCUR, GPIO_PIN_PULLUP);
+ DELAY(80000);
+ }
+ /* XXX 5422 XXX */
+#endif
+}
+
+
+/*
+ * USB Phy SoC dependent handling
+ */
+
+/* XXX 5422 not handled since its unknown how it handles this XXX*/
+static void
+exynos_usb2_set_isolation(bool on)
+{
+ uint32_t en_mask, regval;
+ bus_addr_t reg;
+
+ /* enable PHY */
+ reg = EXYNOS_PMU_USB_PHY_CTRL;
+
+ if (IS_EXYNOS5_P() || IS_EXYNOS4410_P()) {
+ /* set usbhost mode */
+ regval = on ? 0 : USB20_PHY_HOST_LINK_EN;
+ bus_space_write_4(&exynos_bs_tag, exynos_sysreg_bsh,
+ EXYNOS5_SYSREG_USB20_PHY_TYPE, regval);
+ reg = EXYNOS_PMU_USBHOST_PHY_CTRL;
+ }
+
+ /* do enable PHY */
+ en_mask = PMU_PHY_ENABLE;
+ regval = bus_space_read_4(&exynos_bs_tag, exynos_pmu_bsh, reg);
+ regval = on ? regval & ~en_mask : regval | en_mask;
+
+ bus_space_write_4(&exynos_bs_tag, exynos_pmu_bsh,
+ reg, regval);
+
+ if (IS_EXYNOS4X12_P()) {
+ bus_space_write_4(&exynos_bs_tag, exynos_pmu_bsh,
+ EXYNOS_PMU_USB_HSIC_1_PHY_CTRL, regval);
+ bus_space_write_4(&exynos_bs_tag, exynos_pmu_bsh,
+ EXYNOS_PMU_USB_HSIC_2_PHY_CTRL, regval);
+ }
+}
+
+
+#ifdef EXYNOS4
+static void
+exynos4_usb2phy_enable(bus_space_handle_t usb2phy_bsh)
+{
+ uint32_t phypwr, rstcon, clkreg;
+
+ /* write clock value */
+ clkreg = FSEL_CLKSEL_24M;
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHYCLK, clkreg);
+
+ /* set device and host to normal */
+ phypwr = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHYPWR);
+
+ /* enable analog, enable otg, unsleep phy0 (host) */
+ phypwr &= ~PHYPWR_NORMAL_MASK_PHY0;
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHYPWR, phypwr);
+
+ if (IS_EXYNOS4X12_P()) {
+ /* enable hsic0 (host), enable hsic1 and phy1 (otg) */
+ phypwr = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHYPWR);
+ phypwr &= ~(PHYPWR_NORMAL_MASK_HSIC0 |
+ PHYPWR_NORMAL_MASK_HSIC1 |
+ PHYPWR_NORMAL_MASK_PHY1);
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHYPWR, phypwr);
+ }
+
+ /* reset both phy and link of device */
+ rstcon = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_RSTCON);
+ rstcon |= RSTCON_DEVPHY_SWRST;
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_RSTCON, rstcon);
+ DELAY(10000);
+ rstcon &= ~RSTCON_DEVPHY_SWRST;
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_RSTCON, rstcon);
+
+ if (IS_EXYNOS4X12_P()) {
+ /* reset both phy and link of host */
+ rstcon = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_RSTCON);
+ rstcon |= RSTCON_HOSTPHY_SWRST | RSTCON_HOSTPHYLINK_SWRST;
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_RSTCON, rstcon);
+ DELAY(10000);
+ rstcon &= ~(RSTCON_HOSTPHY_SWRST | RSTCON_HOSTPHYLINK_SWRST);
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_RSTCON, rstcon);
+ }
+
+ /* wait for everything to be initialized */
+ DELAY(80000);
+}
+#endif
+
+
+#ifdef EXYNOS5
+static void
+exynos5410_usb2phy_enable(bus_space_handle_t usb2phy_bsh)
+{
+ uint32_t phyhost; //, phyotg;
+ uint32_t phyhsic;
+ uint32_t ehcictrl, ohcictrl;
+
+ /* host configuration: */
+ phyhost = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHY_HOST_CTRL0);
+
+ /* host phy reference clock; assumption its 24 MHz now */
+ phyhost &= ~HOST_CTRL0_FSEL_MASK;
+ phyhost |= __SHIFTIN(FSEL_CLKSEL_24M, HOST_CTRL0_FSEL_MASK);
+
+ /* enable normal mode of operation */
+ phyhost &= ~(HOST_CTRL0_FORCESUSPEND | HOST_CTRL0_FORCESLEEP);
+
+ /* host phy reset */
+ phyhost &= ~(HOST_CTRL0_PHY_SWRST | HOST_CTRL0_PHY_SWRST_ALL |
+ HOST_CTRL0_SIDDQ | HOST_CTRL0_FORCESUSPEND |
+ HOST_CTRL0_FORCESLEEP);
+
+ /* host link reset */
+ phyhost |= HOST_CTRL0_LINK_SWRST | HOST_CTRL0_UTMI_SWRST |
+ HOST_CTRL0_COMMONON_N;
+ /* do the reset */
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, USB_PHY_HOST_CTRL0,
+ phyhost);
+ DELAY(10000);
+
+ phyhost &= ~(HOST_CTRL0_LINK_SWRST | HOST_CTRL0_UTMI_SWRST);
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, USB_PHY_HOST_CTRL0,
+ phyhost);
+
+ /* HSIC control */
+ phyhsic =
+ __SHIFTIN(HSIC_CTRL_REFCLKDIV_12, HSIC_CTRL_REFCLKDIV_MASK) |
+ __SHIFTIN(HSIC_CTRL_REFCLKSEL_DEFAULT, HSIC_CTRL_REFCLKSEL_MASK) |
+ HSIC_CTRL_PHY_SWRST;
+
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL1,
+ phyhsic);
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL2,
+ phyhsic);
+ DELAY(10);
+
+ phyhsic &= ~HSIC_CTRL_PHY_SWRST;
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL1,
+ phyhsic);
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL2,
+ phyhsic);
+ DELAY(80);
+
+#if 0
+ /* otg configuration: */
+ phyotg = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHY_OTG_SYS);
+
+ /* otg phy refrence clock: assumption its 24 Mhz now */
+ phyotg &= ~OTG_SYS_FSEL_MASK;
+ phyotg |= __SHIFTIN(OTG_SYS_FSEL_MASK, FSEL_CLKSEL_24M);
+
+ /* enable normal mode of operation */
+ phyotg &= ~(OTG_SYS_FORCESUSPEND | OTG_SYS_FORCESLEEP |
+ OTG_SYS_SIDDQ_UOTG | OTG_SYS_REFCLKSEL_MASK |
+ OTG_SYS_COMMON_ON);
+
+ /* OTG phy and link reset */
+ phyotg |= OTG_SYS_PHY0_SWRST | OTG_SYS_PHYLINK_SWRST |
+ OTG_SYS_OTGDISABLE | OTG_SYS_REFCLKSEL_MASK;
+
+ /* do the reset */
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHY_OTG_SYS, phyotg);
+ DELAY(10000);
+ phyotg &= ~(OTG_SYS_PHY0_SWRST | OTG_SYS_LINK_SWRST_UOTG |
+ OTG_SYS_PHYLINK_SWRST);
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHY_OTG_SYS, phyotg);
+#endif
+
+ /* enable EHCI DMA burst: */
+ ehcictrl = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHY_HOST_EHCICTRL);
+ ehcictrl |= HOST_EHCICTRL_ENA_INCRXALIGN |
+ HOST_EHCICTRL_ENA_INCR4 | HOST_EHCICTRL_ENA_INCR8 |
+ HOST_EHCICTRL_ENA_INCR16;
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHY_HOST_EHCICTRL, ehcictrl);
+
+ /* Set OHCI suspend */
+ ohcictrl = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHY_HOST_OHCICTRL);
+ ohcictrl |= HOST_OHCICTRL_SUSPLGCY;
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHY_HOST_OHCICTRL, ohcictrl);
+}
+
+
+static void
+exynos5422_usb2phy_enable(bus_space_handle_t usb2phy_bsh)
+{
+ aprint_error("%s not implemented\n", __func__);
+}
+#endif
+
+
+void
+exynos_usb_phy_init(bus_space_handle_t usb2phy_bsh)
+{
+ /* disable phy isolation */
+ exynos_usb2_set_isolation(false);
+
+#ifdef EXYNOS4
+ exynos4_usb2phy_enable(usb2phy_bsh);
+#endif
+#ifdef EXYNOS5
+ if (IS_EXYNOS5410_P()) {
+ exynos5410_usb2phy_enable(usb2phy_bsh);
+ /* TBD: USB3 phy init */
+ } else if (IS_EXYNOS5422_P()) {
+ exynos5422_usb2phy_enable(usb2phy_bsh);
+ /* TBD: USB3 phy init */
+ }
+#endif
+}
+
+
Index: src/sys/arch/arm/samsung/exynos_var.h
diff -u src/sys/arch/arm/samsung/exynos_var.h:1.12 src/sys/arch/arm/samsung/exynos_var.h:1.12.4.1
--- src/sys/arch/arm/samsung/exynos_var.h:1.12 Wed Jun 11 14:54:32 2014
+++ src/sys/arch/arm/samsung/exynos_var.h Sun Jan 4 11:19:00 2015
@@ -1,4 +1,5 @@
-/* $NetBSD: exynos_var.h,v 1.12 2014/06/11 14:54:32 reinoud Exp $ */
+/* $NetBSD: exynos_var.h,v 1.12.4.1 2015/01/04 11:19:00 martin Exp $ */
+
/*-
* Copyright (c) 2013, 2014 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -63,10 +64,12 @@ extern uint32_t exynos_pop_id;
#define IS_EXYNOS4_P() (EXYNOS_PRODUCT_FAMILY(exynos_soc_id) == EXYNOS4_PRODUCT_FAMILY)
#define IS_EXYNOS5410_P() (EXYNOS_PRODUCT_ID(exynos_soc_id) == 0xe5410)
+#define IS_EXYNOS5422_P() (EXYNOS_PRODUCT_ID(exynos_soc_id) == 0xe5422)
#define IS_EXYNOS5440_P() (EXYNOS_PRODUCT_ID(exynos_soc_id) == 0xe5440)
#define IS_EXYNOS5_P() (EXYNOS_PRODUCT_FAMILY(exynos_soc_id) == EXYNOS5_PRODUCT_FAMILY)
+
struct exyo_locators {
const char *loc_name;
bus_size_t loc_offset;
@@ -113,16 +116,29 @@ extern struct arm32_bus_dma_tag exynos_b
extern struct arm32_bus_dma_tag exynos_coherent_bus_dma_tag;
extern bus_space_handle_t exynos_core_bsh;
+extern bus_space_handle_t exynos_wdt_bsh;
+extern bus_space_handle_t exynos_pmu_bsh;
+extern bus_space_handle_t exynos_cmu_bsh;
+extern bus_space_handle_t exynos_sysreg_bsh;
extern void exynos_bootstrap(vaddr_t, vaddr_t);
extern void exynos_dma_bootstrap(psize_t memsize);
extern void exynos_gpio_bootstrap(void);
+extern void exynos_wdt_reset(void);
+
+extern void exynos_init_clkout_for_usb(void); // board specific
+
+extern void exynos_clocks_bootstrap(void);
+extern void exynos_sysctl_cpufreq_init(void);
+extern uint64_t exynos_get_cpufreq(void);
extern void exynos_device_register(device_t self, void *aux);
extern void exynos_device_register_post_config(device_t self, void *aux);
+extern void exynos_usb_phy_init(bus_space_handle_t usb2phy_bsh);
+extern void exynos_usb_soc_powerup(void);
+
extern void exyo_device_register(device_t self, void *aux);
extern void exyo_device_register_post_config(device_t self, void *aux);
-extern void exynos_wdt_reset(void);
extern bool exynos_gpio_pinset_available(const struct exynos_gpio_pinset *);
extern void exynos_gpio_pinset_acquire(const struct exynos_gpio_pinset *);
@@ -155,7 +171,9 @@ exynos_gpio_pindata_ctl(const struct exy
extern int exynos_do_idle(void);
extern int exynos_set_cpu_boot_addr(int cpu, vaddr_t boot_addr);
extern int exynos_cpu_boot(int cpu);
-extern int exynos_l2cc_init(void);
+#ifdef EXYNOS4
+extern int exynos4_l2cc_init(void);
+#endif
#endif
#endif /* _ARM_SAMSUNG_EXYNOS_VAR_H_ */
Index: src/sys/arch/arm/samsung/exynos_wdt.c
diff -u src/sys/arch/arm/samsung/exynos_wdt.c:1.4 src/sys/arch/arm/samsung/exynos_wdt.c:1.4.8.1
--- src/sys/arch/arm/samsung/exynos_wdt.c:1.4 Sat Apr 19 16:43:08 2014
+++ src/sys/arch/arm/samsung/exynos_wdt.c Sun Jan 4 11:19:00 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: exynos_wdt.c,v 1.4 2014/04/19 16:43:08 reinoud Exp $ */
+/* $NetBSD: exynos_wdt.c,v 1.4.8.1 2015/01/04 11:19:00 martin Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#include "exynos_wdt.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: exynos_wdt.c,v 1.4 2014/04/19 16:43:08 reinoud Exp $");
+__KERNEL_RCSID(0, "$NetBSD: exynos_wdt.c,v 1.4.8.1 2015/01/04 11:19:00 martin Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -44,6 +44,7 @@ __KERNEL_RCSID(0, "$NetBSD: exynos_wdt.c
#include <dev/sysmon/sysmonvar.h>
+#include <arm/samsung/exynos_io.h>
#include <arm/samsung/exynos_reg.h>
#include <arm/samsung/exynos_var.h>
@@ -268,24 +269,12 @@ void
exynos_wdt_reset(void)
{
bus_space_tag_t bst = &exynos_bs_tag;
- bus_space_handle_t bsh = exynos_core_bsh;
- bus_addr_t wdt_offset = 0;
-#ifdef EXYNOS4
- if (IS_EXYNOS4_P()) {
- wdt_offset = EXYNOS4_WDT_OFFSET;
- }
-#endif
-#ifdef EXYNOS5
- if (IS_EXYNOS5_P()) {
- wdt_offset = EXYNOS5_WDT_OFFSET;
- }
-#endif
- KASSERT(wdt_offset);
-
+ bus_space_handle_t bsh = exynos_wdt_bsh;
+
(void) splhigh();
- bus_space_write_4(bst, bsh, wdt_offset + EXYNOS_WDT_WTCON, 0);
- bus_space_write_4(bst, bsh, wdt_offset + EXYNOS_WDT_WTCNT, 1);
- bus_space_write_4(bst, bsh, wdt_offset + EXYNOS_WDT_WTCON,
+ bus_space_write_4(bst, bsh, EXYNOS_WDT_WTCON, 0);
+ bus_space_write_4(bst, bsh, EXYNOS_WDT_WTCNT, 1);
+ bus_space_write_4(bst, bsh, EXYNOS_WDT_WTCON,
WTCON_ENABLE | WTCON_RESET_ENABLE);
}
Index: src/sys/arch/arm/samsung/mct.c
diff -u src/sys/arch/arm/samsung/mct.c:1.3 src/sys/arch/arm/samsung/mct.c:1.3.4.1
--- src/sys/arch/arm/samsung/mct.c:1.3 Fri Aug 8 14:43:14 2014
+++ src/sys/arch/arm/samsung/mct.c Sun Jan 4 11:19:00 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: mct.c,v 1.3 2014/08/08 14:43:14 reinoud Exp $ */
+/* $NetBSD: mct.c,v 1.3.4.1 2015/01/04 11:19:00 martin Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: mct.c,v 1.3 2014/08/08 14:43:14 reinoud Exp $");
+__KERNEL_RCSID(1, "$NetBSD: mct.c,v 1.3.4.1 2015/01/04 11:19:00 martin Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -239,7 +239,7 @@ clockhandler(void *arg)
/* ack the interrupt */
mct_write_global(sc, MCT_G_INT_CSTAT, G_INT_CSTAT_CLEAR);
- /* check if we periods clock interrupts */
+ /* check if we missed clock interrupts */
if (periods > 1)
sc->sc_ev_missing_ticks.ev_count += periods - 1;
@@ -247,7 +247,8 @@ clockhandler(void *arg)
hardclock(cf);
if (sc->sc_has_blink_led) {
- sc->sc_led_timer = sc->sc_led_timer - periods - 1;
+ /* we could subtract `periods' here */
+ sc->sc_led_timer = sc->sc_led_timer - 1;
if (sc->sc_led_timer <= 0) {
sc->sc_led_state = !sc->sc_led_state;
exynos_gpio_pindata_write(&sc->sc_gpio_led,
Index: src/sys/arch/arm/samsung/mct_var.h
diff -u src/sys/arch/arm/samsung/mct_var.h:1.2 src/sys/arch/arm/samsung/mct_var.h:1.2.8.1
--- src/sys/arch/arm/samsung/mct_var.h:1.2 Fri May 9 22:21:46 2014
+++ src/sys/arch/arm/samsung/mct_var.h Sun Jan 4 11:19:00 2015
@@ -1,4 +1,5 @@
-/* $NetBSD */
+/* $NetBSD: mct_var.h,v 1.2.8.1 2015/01/04 11:19:00 martin Exp $ */
+
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
* All rights reserved.
Index: src/sys/arch/arm/samsung/sscom.c
diff -u src/sys/arch/arm/samsung/sscom.c:1.6 src/sys/arch/arm/samsung/sscom.c:1.6.2.1
--- src/sys/arch/arm/samsung/sscom.c:1.6 Sun Aug 10 16:44:33 2014
+++ src/sys/arch/arm/samsung/sscom.c Sun Jan 4 11:19:00 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: sscom.c,v 1.6 2014/08/10 16:44:33 tls Exp $ */
+/* $NetBSD: sscom.c,v 1.6.2.1 2015/01/04 11:19:00 martin Exp $ */
/*
* Copyright (c) 2002, 2003 Fujitsu Component Limited
@@ -98,7 +98,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sscom.c,v 1.6 2014/08/10 16:44:33 tls Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sscom.c,v 1.6.2.1 2015/01/04 11:19:00 martin Exp $");
#include "opt_sscom.h"
#include "opt_ddb.h"
@@ -180,7 +180,9 @@ static int sscom_to_tiocm(struct sscom_s
static void sscom_iflush(struct sscom_softc *);
static int sscomhwiflow(struct tty *tp, int block);
-#if defined(KGDB) || defined(SSCOM0CONSOLE) || defined(SSCOM1CONSOLE)
+#if defined(KGDB) || \
+ defined(SSCOM0CONSOLE) || defined(SSCOM1CONSOLE) || \
+ defined(SSCOM2CONSOLE) || defined(SSCOM3CONSOLE)
static int sscom_init(bus_space_tag_t, bus_space_handle_t,
const struct sscom_uart_info *,
int, int, tcflag_t, bus_space_handle_t *);
@@ -1835,7 +1837,9 @@ sscomintr(void *v)
}
-#if defined(KGDB) || defined(SSCOM0CONSOLE) || defined(SSCOM1CONSOLE)
+#if defined(KGDB) || \
+ defined(SSCOM0CONSOLE) || defined(SSCOM1CONSOLE) || \
+ defined(SSCOM2CONSOLE) || defined(SSCOM3CONSOLE)
/*
* Initialize UART for use as console or KGDB line.
*/
@@ -1881,7 +1885,9 @@ sscom_init(bus_space_tag_t iot, bus_spac
#endif
-#if defined(SSCOM0CONSOLE) || defined(SSCOM1CONSOLE)
+#if \
+ defined(SSCOM0CONSOLE) || defined(SSCOM1CONSOLE) || \
+ defined(SSCOM2CONSOLE) || defined(SSCOM3CONSOLE)
/*
* Following are all routines needed for SSCOM to act as console
*/
Index: src/sys/arch/evbarm/conf/ODROID-U
diff -u src/sys/arch/evbarm/conf/ODROID-U:1.9 src/sys/arch/evbarm/conf/ODROID-U:1.9.4.1
--- src/sys/arch/evbarm/conf/ODROID-U:1.9 Sun Aug 3 09:18:16 2014
+++ src/sys/arch/evbarm/conf/ODROID-U Sun Jan 4 11:19:00 2015
@@ -1,7 +1,7 @@
#
-# $NetBSD: ODROID-U,v 1.9 2014/08/03 09:18:16 martin Exp $
+# $NetBSD: ODROID-U,v 1.9.4.1 2015/01/04 11:19:00 martin Exp $
#
-# ODROID-U -- ODROID-U series Exynos Kernel
+# ODROID-U -- ODROID-U{2,3} series Exynos4x12(P) based kernel
#
include "arch/evbarm/conf/std.odroid"
@@ -18,16 +18,19 @@ options RTC_OFFSET=0 # hardware clock i
# CPU options
options CPU_CORTEX
options CPU_CORTEXA9
-options EXYNOS4120
options EXYNOS4212
options EXYNOS4412
options EXYNOS4412P
#options MULTIPROCESSOR
+
options PMAPCOUNTERS
options BUSDMA_COUNTERS
options EXYNOS_CONSOLE_EARLY
-options UVMHIST
-#options UVMHIST_PRINT,KERNHIST_DELAY=0
+#options UVMHIST
+#options UVMHIST_PRINT,KERNHIST_DELAY=0
+#options KERNHIST
+#options USBHIST
+#options USBHIST_SIZE=100000
options __HAVE_MM_MD_DIRECT_MAPPED_PHYS
options PMAP_NEED_ALLOC_POOLPAGE
@@ -91,19 +94,20 @@ options NFS_BOOT_RWSIZE=1024
options COMPAT_NETBSD32 # allow running arm (e.g. non-earm) binaries
#options COMPAT_43 # 4.3BSD compatibility.
-options COMPAT_60 # NetBSD 6.0 compatibility.
-options COMPAT_50 # NetBSD 5.0 compatibility.
-options COMPAT_40 # NetBSD 4.0 compatibility.
-options COMPAT_30 # NetBSD 3.0 compatibility.
-#options COMPAT_20 # NetBSD 2.0 compatibility.
-#options COMPAT_16 # NetBSD 1.6 compatibility.
-#options COMPAT_15 # NetBSD 1.5 compatibility.
-#options COMPAT_14 # NetBSD 1.4 compatibility.
-#options COMPAT_13 # NetBSD 1.3 compatibility.
-#options COMPAT_12 # NetBSD 1.2 compatibility.
-#options COMPAT_11 # NetBSD 1.1 compatibility.
-#options COMPAT_10 # NetBSD 1.0 compatibility.
-#options COMPAT_09 # NetBSD 0.9 compatibility.
+#options COMPAT_09 # NetBSD 0.9,
+#options COMPAT_10 # NetBSD 1.0,
+#options COMPAT_11 # NetBSD 1.1,
+#options COMPAT_12 # NetBSD 1.2,
+#options COMPAT_13 # NetBSD 1.3,
+#options COMPAT_14 # NetBSD 1.4,
+#options COMPAT_15 # NetBSD 1.5,
+#options COMPAT_16 # NetBSD 1.6,
+#options COMPAT_20 # NetBSD 2.0,
+options COMPAT_30 # NetBSD 3.0,
+options COMPAT_40 # NetBSD 4.0,
+options COMPAT_50 # NetBSD 5.0,
+options COMPAT_60 # NetBSD 6.0, and
+options COMPAT_70 # NetBSD 7.0 binary compatibility.
#options TCP_COMPAT_42 # 4.2BSD TCP/IP bug compat. Not recommended.
#options COMPAT_BSDPTY # /dev/[pt]ty?? ptys.
@@ -121,8 +125,9 @@ options SYSVSHM # System V-like memory
#options MINIROOTSIZE=1000 # Size in blocks
#options MEMORY_DISK_IS_ROOT # use memory disk as root
-options DKWEDGE_AUTODISCOVER
-options DKWEDGE_METHOD_GPT
+# Wedge support
+options DKWEDGE_AUTODISCOVER # Automatically add dk(4) instances
+options DKWEDGE_METHOD_GPT # Supports GPT partitions as wedges
# Miscellaneous kernel options
options KTRACE # system call tracing, a la ktrace(1)
@@ -141,13 +146,13 @@ options DEBUG
options LOCKDEBUG
#options PMAP_DEBUG # Enable pmap_debug_level code
#options IPKDB # remote kernel debugging
-#options VERBOSE_INIT_ARM # verbose bootstraping messages
+options VERBOSE_INIT_ARM # verbose bootstraping messages
options DDB # in-kernel debugger
options DDB_ONPANIC=1
options DDB_HISTORY_SIZE=100 # Enable history editing in DDB
#options KGDB
makeoptions DEBUG="-g" # compile full symbol table
-options SYMTAB_SPACE=800000
+makeoptions COPY_SYMTAB=1
## USB Debugging options
options USB_DEBUG
@@ -156,6 +161,7 @@ options OHCI_DEBUG
options UHUB_DEBUG
options USBVERBOSE
+
# Valid options for BOOT_ARGS:
# single Boot to single user only
# kdb Give control to kernel debugger
@@ -163,7 +169,7 @@ options USBVERBOSE
# memorydisk=<n> Set memorydisk size to <n> KB
# quiet Show aprint_naive output
# verbose Show aprint_normal and aprint_verbose output
-#options BOOT_ARGS="\"\""
+options BOOT_ARGS="\"verbose\""
config netbsd root on ? type ?
@@ -176,8 +182,8 @@ cpu0 at mainbus?
# A9 core devices
armperiph0 at mainbus?
-arml2cc0 at armperiph? # L2 Cache Controller
armgic0 at armperiph? # Interrupt Controller
+arml2cc0 at armperiph? # L2 Cache Controller
# Exynos SoC
exyo0 at mainbus?
@@ -190,7 +196,7 @@ sscom0 at exyo0 port 0 # UART0, expan
sscom1 at exyo0 port 1 # UART1, console
# Exynos Watchdog Timer
-exyowdt0 at exyo0 flags 1 # watchdog
+exyowdt0 at exyo0 flags 0 # watchdog
# GPIO
exyogpio0 at exyo0
@@ -210,16 +216,14 @@ ukphy* at mii? phy ?
exyoiic0 at exyo0
iic* at exyoiic?
-
# serial console connectivity
-# UARTS
-# sscom0 attached to expansion port
-# sscom1 is default serial UART console, enable for low-level console:
options SSCOM1CONSOLE, CONSPEED=115200
# include all USB devices
include "dev/usb/usbdevices.config"
+midi* at midibus?
+
# Pseudo-Devices
Index: src/sys/arch/evbarm/conf/std.odroid
diff -u src/sys/arch/evbarm/conf/std.odroid:1.2 src/sys/arch/evbarm/conf/std.odroid:1.2.4.1
--- src/sys/arch/evbarm/conf/std.odroid:1.2 Fri Jun 6 15:00:20 2014
+++ src/sys/arch/evbarm/conf/std.odroid Sun Jan 4 11:19:00 2015
@@ -1,4 +1,4 @@
-# $NetBSD: std.odroid,v 1.2 2014/06/06 15:00:20 reinoud Exp $
+# $NetBSD: std.odroid,v 1.2.4.1 2015/01/04 11:19:00 martin Exp $
#
# standard NetBSD/evbarm for ODROID options
@@ -8,10 +8,11 @@ include "arch/evbarm/conf/std.evbarm"
# Pull in ODROID config definitions
include "arch/evbarm/conf/files.odroid"
-#makeoptions CPUFLAGS="-mcpu=cortex-a9 -mfpu=neon"
+makeoptions CPUFLAGS="-march=armv7-a -mfpu=neon"
# To support easy transit to ../arch/arm/arm32
options MODULAR
+options MODULAR_DEFAULT_AUTOLOAD
options ARM_HAS_VBAR
options CORTEX_PMC
options __HAVE_CPU_COUNTER
@@ -23,6 +24,7 @@ options FPU_VFP
# All shipped Samsung SoC's that are not Samsung products have this
options ARM_TRUSTZONE_FIRMWARE
+options __NO_FIQ
makeoptions KERNEL_BASE_PHYS="0x80000000"
makeoptions KERNEL_BASE_VIRT="0x80000000"
Index: src/sys/arch/evbarm/odroid/odroid_machdep.c
diff -u src/sys/arch/evbarm/odroid/odroid_machdep.c:1.24 src/sys/arch/evbarm/odroid/odroid_machdep.c:1.24.4.1
--- src/sys/arch/evbarm/odroid/odroid_machdep.c:1.24 Mon Aug 4 18:14:43 2014
+++ src/sys/arch/evbarm/odroid/odroid_machdep.c Sun Jan 4 11:19:00 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: odroid_machdep.c,v 1.24 2014/08/04 18:14:43 reinoud Exp $ */
+/* $NetBSD: odroid_machdep.c,v 1.24.4.1 2015/01/04 11:19:00 martin Exp $ */
/*
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: odroid_machdep.c,v 1.24 2014/08/04 18:14:43 reinoud Exp $");
+__KERNEL_RCSID(0, "$NetBSD: odroid_machdep.c,v 1.24.4.1 2015/01/04 11:19:00 martin Exp $");
#include "opt_evbarm_boardtype.h"
#include "opt_exynos.h"
@@ -94,6 +94,15 @@ __KERNEL_RCSID(0, "$NetBSD: odroid_machd
#include <dev/usb/ukbdvar.h>
#include <net/if_ether.h>
+
+/* sanity checks */
+#ifndef EXYNOS4
+#ifndef EXYNOS5
+#error Please define _either_ an EXYNOS4 or an EXYNOS5 cpu, not mixed
+#endif
+#endif
+
+
/* serial console stuff */
#include "sscom.h"
#include "opt_sscom.h"
@@ -108,44 +117,8 @@ __KERNEL_RCSID(0, "$NetBSD: odroid_machd
#include <arm/samsung/sscom_var.h>
#include <arm/samsung/sscom_reg.h>
-static const struct sscom_uart_info exynos_uarts[] = {
-#ifdef EXYNOS5
- {
- .unit = 0,
- .iobase = EXYNOS5_UART0_OFFSET
- },
- {
- .unit = 1,
- .iobase = EXYNOS5_UART1_OFFSET
- },
- {
- .unit = 2,
- .iobase = EXYNOS5_UART2_OFFSET
- },
- {
- .unit = 3,
- .iobase = EXYNOS5_UART3_OFFSET
- },
-#endif
-#ifdef EXYNOS4
- {
- .unit = 0,
- .iobase = EXYNOS4_UART0_OFFSET
- },
- {
- .unit = 1,
- .iobase = EXYNOS4_UART1_OFFSET
- },
- {
- .unit = 2,
- .iobase = EXYNOS4_UART2_OFFSET
- },
- {
- .unit = 3,
- .iobase = EXYNOS4_UART3_OFFSET
- },
-#endif
-};
+extern const int num_exynos_uarts_entries;
+extern const struct sscom_uart_info exynos_uarts[];
/* sanity checks for serial console */
#ifndef CONSPEED
@@ -161,7 +134,7 @@ static const struct sscom_uart_info exyn
//static const bus_addr_t conaddr = CONADDR;
static const int conspeed = CONSPEED;
static const int conmode = CONMODE;
-#endif /*defined(KGDB) || defined(SSCOM0CONSOLE) || defined(SSCOM1CONSOLE) */
+#endif /*defined(KGDB) || defined(SSCOM*CONSOLE) */
/*
* uboot passes 4 arguments to us.
@@ -332,9 +305,11 @@ initarm(void *arg)
printf("initarm: cbar=%#x\n", armreg_cbar_read());
#endif
- /* init clocks */
- /* determine cpu clock source */
-curcpu()->ci_data.cpu_cc_freq = 1*1000*1000*1000; /* XXX hack XXX */
+ /* determine cpu0 clock rate */
+ exynos_clocks_bootstrap();
+#ifdef VERBOSE_INIT_ARM
+ printf("CPU0 now running on %"PRIu64" Mhz\n", exynos_get_cpufreq()/(1000*1000));
+#endif
#if NARML2CC > 0
if (CPU_ID_CORTEX_A9_P(curcpu()->ci_arm_cpuid)) {
@@ -343,7 +318,7 @@ curcpu()->ci_data.cpu_cc_freq = 1*1000*1
EXYNOS_IOPHYSTOVIRT(armreg_cbar_read());
#ifdef ARM_TRUSTZONE_FIRMWARE
- exynos_l2cc_init();
+ exynos4_l2cc_init();
#endif
arml2cc_init(&exynos_bs_tag, pl310_bh, 0x2000);
}
@@ -372,16 +347,14 @@ curcpu()->ci_data.cpu_cc_freq = 1*1000*1
ram_size = (psize_t) 0xC0000000 - 0x40000000;
#if defined(EXYNOS4)
- if (IS_EXYNOS4_P()) {
- switch (exynos_pop_id) {
- case EXYNOS_PACKAGE_ID_2_GIG:
- KASSERT(ram_size <= 2UL*1024*1024*1024);
- break;
- default:
- printf("Unknown PoP package id 0x%08x, assuming 1Gb\n",
- exynos_pop_id);
- ram_size = (psize_t) 0x10000000;
- }
+ switch (exynos_pop_id) {
+ case EXYNOS_PACKAGE_ID_2_GIG:
+ KASSERT(ram_size <= 2UL*1024*1024*1024);
+ break;
+ default:
+ printf("Unknown PoP package id 0x%08x, assuming 1Gb\n",
+ exynos_pop_id);
+ ram_size = (psize_t) 0x10000000;
}
#endif
@@ -448,7 +421,7 @@ consinit(void)
bus_space_handle_t bsh = EXYNOS_IOPHYSTOVIRT(iobase);
u_int i;
/*
- * No need to guess at the UART frequency since we can caclulate it.
+ * No need to guess at the UART frequency since we can calculate it.
*/
uint32_t freq = conspeed
* (16 * (bus_space_read_4(bst, bsh, SSCOM_UBRDIV) + 1)
@@ -456,12 +429,13 @@ consinit(void)
freq = (freq + conspeed / 2) / 1000;
freq *= 1000;
- for (i = 0; i < __arraycount(exynos_uarts); i++) {
+ /* go trough all entries */
+ for (i = 0; i < num_exynos_uarts_entries; i++) {
/* attach console */
if (exynos_uarts[i].iobase + EXYNOS_CORE_PBASE == iobase)
break;
}
- KASSERT(i < __arraycount(exynos_uarts));
+ KASSERT(i < num_exynos_uarts_entries);
printf("%s: attaching console @ %#"PRIxPTR" (%u HZ, %u bps)\n",
__func__, iobase, freq, conspeed);
if (sscom_cnattach(bst, exynos_core_bsh, &exynos_uarts[i],
@@ -536,7 +510,7 @@ odroid_exynos4_gpio_ncs(device_t self, p
prop_dictionary_set_uint32(dict, "nc-GPA1", 0x3f - 0b00001000);
prop_dictionary_set_uint32(dict, "nc-GPB", 0xff - 0b00000000);
prop_dictionary_set_uint32(dict, "nc-GPC0", 0x1f - 0b00000000);
- /* blue led at bit 0 : */
+ /* blue led at bit 0 : heartbeat */
prop_dictionary_set_uint32(dict, "nc-GPC1", 0x1f - 0b00000001);
prop_dictionary_set_uint32(dict, "nc-GPD0", 0x0f - 0b00000000);
/* i2c0 at pin 0,1 and i2c1 at pin 2,3 : */
@@ -562,8 +536,8 @@ odroid_exynos4_gpio_ncs(device_t self, p
prop_dictionary_set_uint32(dict, "nc-GPY5", 0xff - 0b00000000);
prop_dictionary_set_uint32(dict, "nc-GPY6", 0xff - 0b00000000);
prop_dictionary_set_uint32(dict, "nc-ETC0", 0x3f - 0b00000000);
- /* standard Xuhost bits at pin 5,6 */
- prop_dictionary_set_uint32(dict, "nc-ETC6", 0x7f - 0b01100000);
+ /* standard Xuhost bits at pin 6,7 */
+ prop_dictionary_set_uint32(dict, "nc-ETC6", 0xff - 0b11000000);
prop_dictionary_set_uint32(dict, "nc-GPM0", 0xff - 0b00000000);
prop_dictionary_set_uint32(dict, "nc-GPM1", 0x7f - 0b00000000);
prop_dictionary_set_uint32(dict, "nc-GPM2", 0x1f - 0b00000000);
@@ -573,7 +547,7 @@ odroid_exynos4_gpio_ncs(device_t self, p
/* expansion connector bits at pin 0,1,5 : */
prop_dictionary_set_uint32(dict, "nc-GPX1", 0xff - 0b00100011);
prop_dictionary_set_uint32(dict, "nc-GPX2", 0xff - 0b00000000);
- /* hub communication at pin 0,4,5 : */
+ /* usb hub communication at pin 0,4,5 : */
prop_dictionary_set_uint32(dict, "nc-GPX3", 0xff - 0b00110001);
prop_dictionary_set_uint32(dict, "nc-GPZ", 0xff - 0b00000000);
prop_dictionary_set_uint32(dict, "nc-GPV0", 0xff - 0b00000000);
@@ -595,7 +569,73 @@ odroid_exynos5_gpio_ncs(device_t self, p
* generated by the gpio bootstrap and the values substracted are
* explicitly allowed
*/
- /* TBD: generate these values, see exynos_gpio.c boostrap */
+ /* i2c2 at pin 6,7 */
+ prop_dictionary_set_uint32(dict, "nc-GPA0", 0xff - 0b11000000);
+ prop_dictionary_set_uint32(dict, "nc-GPA1", 0x3f - 0b00000000);
+ /* i2c4 at pin 0,1 */
+ prop_dictionary_set_uint32(dict, "nc-GPA2", 0xff - 0b00000011);
+ prop_dictionary_set_uint32(dict, "nc-GPB0", 0x1f - 0b00000000);
+ prop_dictionary_set_uint32(dict, "nc-GPB1", 0x1f - 0b00000000);
+ /* green led at bit 1 : eMMC activity */
+ /* red led at bit 2 : heartbeat */
+ prop_dictionary_set_uint32(dict, "nc-GPB2", 0x0f - 0b00000110);
+ /* i2c1 at pin 2,3 */
+ prop_dictionary_set_uint32(dict, "nc-GPB3", 0x0f - 0b00001100);
+ prop_dictionary_set_uint32(dict, "nc-GPC0", 0x7f - 0b00000000);
+ prop_dictionary_set_uint32(dict, "nc-GPC1", 0x0f - 0b00000000);
+ prop_dictionary_set_uint32(dict, "nc-GPC2", 0x7f - 0b00000000);
+ prop_dictionary_set_uint32(dict, "nc-GPC3", 0x7f - 0b00000000);
+ prop_dictionary_set_uint32(dict, "nc-GPD0", 0x0f - 0b00000000);
+ prop_dictionary_set_uint32(dict, "nc-GPD1", 0xff - 0b00000000);
+ prop_dictionary_set_uint32(dict, "nc-GPY0", 0x3f - 0b00000000);
+ prop_dictionary_set_uint32(dict, "nc-GPY1", 0x0f - 0b00000000);
+ prop_dictionary_set_uint32(dict, "nc-GPY2", 0x3f - 0b00000000);
+ prop_dictionary_set_uint32(dict, "nc-GPY3", 0xff - 0b00000000);
+ prop_dictionary_set_uint32(dict, "nc-GPY4", 0xff - 0b00000000);
+ prop_dictionary_set_uint32(dict, "nc-GPY5", 0xff - 0b00000000);
+ prop_dictionary_set_uint32(dict, "nc-GPY6", 0xff - 0b00000000);
+ prop_dictionary_set_uint32(dict, "nc-ETC0", 0x3f - 0b00000000);
+ /* standard Xuhost bits at pin 5,6 */
+ prop_dictionary_set_uint32(dict, "nc-ETC6", 0x7f - 0b01100000);
+ prop_dictionary_set_uint32(dict, "nc-ETC7", 0x1f - 0b00000000);
+ prop_dictionary_set_uint32(dict, "nc-GPC4", 0x3f - 0b00000000);
+ /* usb hub communication at bit 6,7 : */
+ prop_dictionary_set_uint32(dict, "nc-GPX0", 0xff - 0b11000000);
+ /* usb hub communication at bit 4 : */
+ prop_dictionary_set_uint32(dict, "nc-GPX1", 0xff - 0b00010000);
+ /* blue led at bit 3 : microSD activity */
+ prop_dictionary_set_uint32(dict, "nc-GPX2", 0xff - 0b00001000);
+ prop_dictionary_set_uint32(dict, "nc-GPX3", 0xff - 0b00000000);
+ prop_dictionary_set_uint32(dict, "nc-GPE0", 0xff - 0b00000000);
+ prop_dictionary_set_uint32(dict, "nc-GPE1", 0x03 - 0b00000000);
+ prop_dictionary_set_uint32(dict, "nc-GPF0", 0x0f - 0b00000000);
+ prop_dictionary_set_uint32(dict, "nc-GPF1", 0x0f - 0b00000000);
+ prop_dictionary_set_uint32(dict, "nc-GPG0", 0xff - 0b00000000);
+ prop_dictionary_set_uint32(dict, "nc-GPG1", 0xff - 0b00000000);
+ prop_dictionary_set_uint32(dict, "nc-GPG2", 0x03 - 0b00000000);
+ prop_dictionary_set_uint32(dict, "nc-GPH0", 0x0f - 0b00000000);
+ prop_dictionary_set_uint32(dict, "nc-GPH1", 0xff - 0b00000000);
+
+ prop_dictionary_set_uint32(dict, "nc-GPJ0", 0xff - 0b00000000);
+ prop_dictionary_set_uint32(dict, "nc-GPJ1", 0xff - 0b00000000);
+ prop_dictionary_set_uint32(dict, "nc-GPJ2", 0xff - 0b00000000);
+ prop_dictionary_set_uint32(dict, "nc-GPJ3", 0xff - 0b00000000);
+ prop_dictionary_set_uint32(dict, "nc-GPJ4", 0xff - 0b00000000);
+ prop_dictionary_set_uint32(dict, "nc-GPK0", 0xff - 0b00000000);
+ prop_dictionary_set_uint32(dict, "nc-GPK1", 0xff - 0b00000000);
+ /* usb3 overcur1{2,3} at bits 4,5, vbus1 at pin 7 */
+ prop_dictionary_set_uint32(dict, "nc-GPK2", 0xff - 0b10110000);
+ /* usb3 overcur0{2,3} at bits 0,1, vbus0 at pin 3 */
+ prop_dictionary_set_uint32(dict, "nc-GPK3", 0xff - 0b00001011);
+
+ prop_dictionary_set_uint32(dict, "nc-GPV0", 0xff - 0b00000000);
+ prop_dictionary_set_uint32(dict, "nc-GPV1", 0xff - 0b00000000);
+ prop_dictionary_set_uint32(dict, "nc-ETC5", 0x03 - 0b00000000);
+ prop_dictionary_set_uint32(dict, "nc-GPV2", 0xff - 0b00000000);
+ prop_dictionary_set_uint32(dict, "nc-GPV3", 0xff - 0b00000000);
+ prop_dictionary_set_uint32(dict, "nc-ETC8", 0x03 - 0b00000000);
+ prop_dictionary_set_uint32(dict, "nc-GPV4", 0x03 - 0b00000000);
+ prop_dictionary_set_uint32(dict, "nc-GPZ", 0x7f - 0b00000000);
}
#endif
@@ -633,7 +673,7 @@ odroid_device_register(device_t self, vo
}
#ifdef EXYNOS4
- if (device_is_a(self, "exyogpio") && (IS_EXYNOS4_P())) {
+ if (device_is_a(self, "exyogpio")) {
/* unused bits */
odroid_exynos4_gpio_ncs(self, dict);
@@ -646,7 +686,7 @@ odroid_device_register(device_t self, vo
prop_dictionary_set_cstring(dict, "p3v3_en", ">GPA1[3]");
}
- if (device_is_a(self, "exyoiic") && (IS_EXYNOS4_P())) {
+ if (device_is_a(self, "exyoiic")) {
prop_dictionary_set_bool(dict, "iic0_enable", true);
prop_dictionary_set_bool(dict, "iic1_enable", true);
prop_dictionary_set_bool(dict, "iic2_enable", true);
@@ -659,7 +699,7 @@ odroid_device_register(device_t self, vo
}
#endif
#ifdef EXYNOS5
- if (device_is_a(self, "exyogpio") && (IS_EXYNOS5_P())) {
+ if (device_is_a(self, "exyogpio")) {
/* unused bits */
odroid_exynos5_gpio_ncs(self, dict);
@@ -671,6 +711,17 @@ odroid_device_register(device_t self, vo
/* internal hub IIRC, unknown if this line exists */
//prop_dictionary_set_cstring(dict, "p3v3_en", ">GPA1[3]");
}
+ if (device_is_a(self, "exyoiic")) {
+ /* IIC0 not used (NC) */
+ prop_dictionary_set_bool(dict, "iic1_enable", true);
+ prop_dictionary_set_bool(dict, "iic2_enable", true);
+ /* IIC3 not used (NC) */
+ prop_dictionary_set_bool(dict, "iic4_enable", true);
+ /* IIC5 not used (NC) */
+ /* IIC6 used differently (SCLK used as led1) */
+ /* IIC7 used differently (PWM, though NC) */
+ /* IIC8 HDMI, not possible trough GPIO */
+ }
#endif
}
@@ -686,52 +737,49 @@ exynos_usb_init_usb3503_hub(device_t sel
prop_dictionary_get_cstring_nocopy(dict, "nreset", &pin_nreset);
prop_dictionary_get_cstring_nocopy(dict, "hubconnect", &pin_hubconnect);
prop_dictionary_get_cstring_nocopy(dict, "nint", &pin_nint);
- if (pin_nreset && pin_hubconnect && pin_nint) {
- ok1 = exynos_gpio_pin_reserve(pin_nreset, &nreset_pin);
- ok2 = exynos_gpio_pin_reserve(pin_hubconnect, &hubconnect_pin);
- ok3 = exynos_gpio_pin_reserve(pin_nint, &nint_pin);
- if (!ok1)
- aprint_error_dev(self,
- "can't reserve GPIO pin %s\n", pin_nreset);
- if (!ok2)
- aprint_error_dev(self,
- "can't reserve GPIO pin %s\n", pin_hubconnect);
- if (!ok3)
- aprint_error_dev(self,
- "can't reserve GPIO pin %s\n", pin_nint);
- if (!(ok1 && ok2 && ok3))
- return;
-
- /* reset pin to zero */
- exynos_gpio_pindata_write(&nreset_pin, 0);
- DELAY(10000);
-
- /* pull intn low */
- exynos_gpio_pindata_ctl(&nint_pin, GPIO_PIN_PULLDOWN);
- DELAY(10000);
-
- /* set hubconnect low */
- exynos_gpio_pindata_write(&hubconnect_pin, 0);
- DELAY(10000);
-
- /* reset pin up again, hub enters RefClk stage */
- exynos_gpio_pindata_write(&nreset_pin, 1);
- DELAY(10000);
-
- /* set hubconnect high */
- exynos_gpio_pindata_write(&hubconnect_pin, 1);
- DELAY(10000);
-
- /* release intn */
- exynos_gpio_pindata_ctl(&nint_pin, GPIO_PIN_TRISTATE);
- DELAY(10000);
-
- /* DONE! */
- } else {
+ if (!(pin_nreset && pin_hubconnect && pin_nint)) {
aprint_error_dev(self,
"failed to lookup GPIO pins for usb3503 hub init");
+ return;
}
- /* XXX leaving pins claimed! */
+
+ ok1 = exynos_gpio_pin_reserve(pin_nreset, &nreset_pin);
+ ok2 = exynos_gpio_pin_reserve(pin_hubconnect, &hubconnect_pin);
+ ok3 = exynos_gpio_pin_reserve(pin_nint, &nint_pin);
+ if (!ok1)
+ aprint_error_dev(self,
+ "can't reserve GPIO pin %s\n", pin_nreset);
+ if (!ok2)
+ aprint_error_dev(self,
+ "can't reserve GPIO pin %s\n", pin_hubconnect);
+ if (!ok3)
+ aprint_error_dev(self,
+ "can't reserve GPIO pin %s\n", pin_nint);
+ if (!(ok1 && ok2 && ok3))
+ return;
+
+ /* reset pin to zero */
+ exynos_gpio_pindata_write(&nreset_pin, 0);
+ DELAY(10000);
+
+ /* pull intn low */
+ exynos_gpio_pindata_ctl(&nint_pin, GPIO_PIN_PULLDOWN);
+
+ /* set hubconnect low */
+ exynos_gpio_pindata_write(&hubconnect_pin, 0);
+
+ /* reset pin up again, hub enters RefClk stage */
+ exynos_gpio_pindata_write(&nreset_pin, 1);
+ DELAY(10000);
+
+ /* release intn */
+ exynos_gpio_pindata_ctl(&nint_pin, GPIO_PIN_TRISTATE);
+
+ /* set hubconnect high */
+ exynos_gpio_pindata_write(&hubconnect_pin, 1);
+ DELAY(40000);
+
+ /* DONE! */
}
@@ -764,7 +812,7 @@ exynos_usb_powercycle_lan9730(device_t s
struct i2c_controller *i2c;
const char *pin_enable;
uint8_t rdata, wdata, reg;
- int error;
+ int error __diagused;
bool ok;
/*
@@ -786,14 +834,14 @@ exynos_usb_powercycle_lan9730(device_t s
error = iic_exec(i2c, I2C_OP_WRITE_WITH_STOP, chipid, ®, 1,
&wdata, sizeof(wdata), 0);
KASSERT(!error);
- DELAY(10000);
+ DELAY(20000);
/* set power level back to 3.3v */
wdata = 0x33;
error = iic_exec(i2c, I2C_OP_WRITE_WITH_STOP, chipid, ®, 1,
&wdata, sizeof(wdata), 0);
KASSERT(!error);
- DELAY(10000);
+ DELAY(20000);
/* enable the bucket explicitly */
reg = buck_ctlreg;
@@ -804,7 +852,7 @@ exynos_usb_powercycle_lan9730(device_t s
error = iic_exec(i2c, I2C_OP_WRITE_WITH_STOP, chipid, ®, 1,
&rdata, sizeof(rdata), 0);
KASSERT(!error);
- DELAY(10000);
+ DELAY(30000);
iic_release_bus(i2c, 0);
@@ -817,8 +865,9 @@ exynos_usb_powercycle_lan9730(device_t s
"can't reserve GPIO pin %s\n", pin_enable);
} else {
exynos_gpio_pindata_write(&enable_pin, 0);
- DELAY(10000);
+ DELAY(30000);
exynos_gpio_pindata_write(&enable_pin, 1);
+ DELAY(30000);
}
} else {
aprint_error_dev(self, "failed to lookup lan_power GPIO pin");
@@ -838,3 +887,26 @@ odroid_device_register_post_config(devic
}
}
+
+/*
+ * Odroid specific tweaks
+ */
+/*
+ * The external USB devices are clocked trough the DEBUG clkout
+ * XXX is this Odroid specific? XXX
+ */
+void
+exynos_init_clkout_for_usb(void)
+{
+#ifdef EXYNOS4
+ /* Select XUSBXTI as source for CLKOUT */
+ bus_space_write_4(&exynos_bs_tag, exynos_pmu_bsh,
+ EXYNOS_PMU_DEBUG_CLKOUT, 0x900);
+#endif
+#ifdef EXYNOS5
+ /* Select XUSBXTI as source for CLKOUT */
+ bus_space_write_4(&exynos_bs_tag, exynos_pmu_bsh,
+ EXYNOS_PMU_DEBUG_CLKOUT, 0x1000);
+#endif
+}
+
Index: src/sys/arch/evbarm/odroid/odroid_start.S
diff -u src/sys/arch/evbarm/odroid/odroid_start.S:1.3 src/sys/arch/evbarm/odroid/odroid_start.S:1.3.4.1
--- src/sys/arch/evbarm/odroid/odroid_start.S:1.3 Mon Aug 4 18:14:43 2014
+++ src/sys/arch/evbarm/odroid/odroid_start.S Sun Jan 4 11:19:00 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: odroid_start.S,v 1.3 2014/08/04 18:14:43 reinoud Exp $ */
+/* $NetBSD: odroid_start.S,v 1.3.4.1 2015/01/04 11:19:00 martin Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -46,7 +46,7 @@
#include <evbarm/odroid/platform.h>
-RCSID("$NetBSD: odroid_start.S,v 1.3 2014/08/04 18:14:43 reinoud Exp $")
+RCSID("$NetBSD: odroid_start.S,v 1.3.4.1 2015/01/04 11:19:00 martin Exp $")
#if defined(VERBOSE_INIT_ARM)
@@ -178,13 +178,26 @@ _C_LABEL(odroid_start):
str r0, [r4] // save pop_id
#endif
- /* Pick uart address and initial MMU table for the SoC */
- mov r2, #0
- ubfx r1, r5, #24, #8
- cmp r1, #0xe5
- movteq r2, #:upper16:(EXYNOS_CORE_PBASE + EXYNOS5_UART2_OFFSET)
- cmp r1, #0xe4
- movteq r2, #:upper16:(EXYNOS_CORE_PBASE + EXYNOS4_UART1_OFFSET)
+ /* Pick uart address for the SoC */
+#ifdef EXYNOS4
+ adr r1, .Lsscom_exynos4_table
+#endif
+#ifdef EXYNOS5
+ adr r1, .Lsscom_exynos5_table
+#endif
+#ifdef SSCOM0CONSOLE
+ ldr r2, [r1, #0*8+4]
+#endif
+#ifdef SSCOM1CONSOLE
+ ldr r2, [r1, #1*8+4]
+#endif
+#ifdef SSCOM2CONSOLE
+ ldr r2, [r1, #2*8+4]
+#endif
+#ifdef SSCOM3CONSOLE
+ ldr r2, [r1, #3*8+4]
+#endif
+ add r2, r2, #EXYNOS_CORE_PBASE
mcr p15, 0, r2, c13, c0, 3 // TPIDRURO set (uart address)
/*
@@ -237,6 +250,33 @@ _C_LABEL(odroid_start):
/* NOTREACHED */
+ .align 0
+ .global _C_LABEL(num_exynos_uarts_entries)
+_C_LABEL(num_exynos_uarts_entries):
+ .word 8 // update number of entries!!!
+ .global _C_LABEL(exynos_uarts)
+_C_LABEL(exynos_uarts):
+.Lsscom_exynos4_table:
+ .word 0
+ .word EXYNOS4_UART0_OFFSET
+ .word 1
+ .word EXYNOS4_UART1_OFFSET
+ .word 2
+ .word EXYNOS4_UART2_OFFSET
+ .word 3
+ .word EXYNOS4_UART3_OFFSET
+
+.Lsscom_exynos5_table:
+ .word 0
+ .word EXYNOS5_UART0_OFFSET
+ .word 1
+ .word EXYNOS5_UART1_OFFSET
+ .word 2
+ .word EXYNOS5_UART2_OFFSET
+ .word 3
+ .word EXYNOS5_UART3_OFFSET
+
+
#if defined(VERBOSE_INIT_ARM)
.align 0
.global xputc
Added files:
Index: src/sys/arch/evbarm/conf/ODROID-XU
diff -u /dev/null src/sys/arch/evbarm/conf/ODROID-XU:1.4.4.2
--- /dev/null Sun Jan 4 11:19:00 2015
+++ src/sys/arch/evbarm/conf/ODROID-XU Sun Jan 4 11:19:00 2015
@@ -0,0 +1,249 @@
+#
+# $NetBSD: ODROID-XU,v 1.4.4.2 2015/01/04 11:19:00 martin Exp $
+#
+# ODROID-XU -- ODROID-XU Exynos5410 based kernel
+#
+
+include "arch/evbarm/conf/std.odroid"
+
+# estimated number of users
+
+maxusers 32
+
+# Standard system options
+
+options RTC_OFFSET=0 # hardware clock is this many mins. west of GMT
+#options NTP # NTP phase/frequency locked loop
+
+# CPU options
+options CPU_CORTEX
+options CPU_CORTEXA7
+options CPU_CORTEXA15
+options EXYNOS5410
+#options MULTIPROCESSOR
+
+options PMAPCOUNTERS
+options BUSDMA_COUNTERS
+options EXYNOS_CONSOLE_EARLY
+#options UVMHIST
+options USBHIST
+options USBHIST_SIZE=100000
+#options UVMHIST_PRINT,KERNHIST_DELAY=0
+options __HAVE_MM_MD_DIRECT_MAPPED_PHYS
+options PMAP_NEED_ALLOC_POOLPAGE
+
+# Specify the memory size in megabytes (optional).
+#options MEMSIZE=2048
+
+# File systems
+file-system FFS # UFS
+#file-system LFS # log-structured file system
+file-system MFS # memory file system
+file-system NFS # Network file system
+#file-system ADOSFS # AmigaDOS-compatible file system
+#file-system EXT2FS # second extended file system (linux)
+#file-system CD9660 # ISO 9660 + Rock Ridge file system
+file-system MSDOSFS # MS-DOS file system
+#file-system FDESC # /dev/fd
+file-system KERNFS # /kern
+#file-system NULLFS # loopback file system
+file-system PROCFS # /proc
+#file-system PUFFS # Userspace file systems (e.g. ntfs-3g & sshfs)
+#file-system UMAPFS # NULLFS + uid and gid remapping
+#file-system UNION # union file system
+file-system TMPFS # memory file system
+file-system PTYFS # /dev/pts/N support
+
+# File system options
+#options QUOTA # legacy UFS quotas
+#options QUOTA2 # new, in-filesystem UFS quotas
+#options FFS_EI # FFS Endian Independent support
+#options NFSSERVER
+options WAPBL # File system journaling support
+#options FFS_NO_SNAPSHOT # No FFS snapshot support
+
+# Networking options
+
+#options GATEWAY # packet forwarding
+options INET # IP + ICMP + TCP + UDP
+options INET6 # IPV6
+#options IPSEC # IP security
+#options IPSEC_DEBUG # debug for IP security
+#options MROUTING # IP multicast routing
+#options PIM # Protocol Independent Multicast
+#options NETATALK # AppleTalk networking
+#options PPP_BSDCOMP # BSD-Compress compression support for PPP
+#options PPP_DEFLATE # Deflate compression support for PPP
+#options PPP_FILTER # Active filter support for PPP (requires bpf)
+#options TCP_DEBUG # Record last TCP_NDEBUG packets with SO_DEBUG
+
+options NFS_BOOT_BOOTP
+options NFS_BOOT_DHCP
+#options NFS_BOOT_BOOTSTATIC
+#options NFS_BOOTSTATIC_MYIP="\"192.168.1.4\""
+#options NFS_BOOTSTATIC_GWIP="\"192.168.1.1\""
+#options NFS_BOOTSTATIC_MASK="\"255.255.255.0\""
+#options NFS_BOOTSTATIC_SERVADDR="\"192.168.1.1\""
+#options NFS_BOOTSTATIC_SERVER="\"192.168.1.1:/nfs/sdp2430\""
+
+options NFS_BOOT_RWSIZE=1024
+
+# Compatibility options
+
+options COMPAT_NETBSD32 # allow running arm (e.g. non-earm) binaries
+#options COMPAT_43 # 4.3BSD compatibility.
+#options COMPAT_09 # NetBSD 0.9,
+#options COMPAT_10 # NetBSD 1.0,
+#options COMPAT_11 # NetBSD 1.1,
+#options COMPAT_12 # NetBSD 1.2,
+#options COMPAT_13 # NetBSD 1.3,
+#options COMPAT_14 # NetBSD 1.4,
+#options COMPAT_15 # NetBSD 1.5,
+#options COMPAT_16 # NetBSD 1.6,
+#options COMPAT_20 # NetBSD 2.0,
+options COMPAT_30 # NetBSD 3.0,
+options COMPAT_40 # NetBSD 4.0,
+options COMPAT_50 # NetBSD 5.0,
+options COMPAT_60 # NetBSD 6.0, and
+options COMPAT_70 # NetBSD 7.0 binary compatibility.
+#options TCP_COMPAT_42 # 4.2BSD TCP/IP bug compat. Not recommended.
+#options COMPAT_BSDPTY # /dev/[pt]ty?? ptys.
+
+# Shared memory options
+
+options SYSVMSG # System V-like message queues
+options SYSVSEM # System V-like semaphores
+options SYSVSHM # System V-like memory sharing
+
+# Device options
+
+#options MEMORY_DISK_HOOKS # boottime setup of ramdisk
+#options MEMORY_DISK_ROOT_SIZE=8192 # Size in blocks
+#options MEMORY_DISK_DYNAMIC
+#options MINIROOTSIZE=1000 # Size in blocks
+#options MEMORY_DISK_IS_ROOT # use memory disk as root
+
+# Wedge support
+options DKWEDGE_AUTODISCOVER # Automatically add dk(4) instances
+options DKWEDGE_METHOD_GPT # Supports GPT partitions as wedges
+
+# Miscellaneous kernel options
+options KTRACE # system call tracing, a la ktrace(1)
+#options KMEMSTATS # kernel memory statistics
+#options SCSIVERBOSE # Verbose SCSI errors
+#options MIIVERBOSE # Verbose MII autoconfuration messages
+#options DDB_KEYCODE=0x40
+#options USERCONF # userconf(4) support
+#options PIPE_SOCKETPAIR # smaller, but slower pipe(2)
+
+# Development and Debugging options
+
+#options PERFCTRS # performance counters
+options DIAGNOSTIC # internal consistency checks
+options DEBUG
+options LOCKDEBUG
+#options PMAP_DEBUG # Enable pmap_debug_level code
+#options IPKDB # remote kernel debugging
+options VERBOSE_INIT_ARM # verbose bootstraping messages
+options DDB # in-kernel debugger
+options DDB_ONPANIC=1
+options DDB_HISTORY_SIZE=100 # Enable history editing in DDB
+#options KGDB
+makeoptions DEBUG="-g" # compile full symbol table
+makeoptions COPY_SYMTAB=1
+
+## USB Debugging options
+options USB_DEBUG
+options EHCI_DEBUG
+options OHCI_DEBUG
+options UHUB_DEBUG
+options USBVERBOSE
+
+
+# Valid options for BOOT_ARGS:
+# single Boot to single user only
+# kdb Give control to kernel debugger
+# ask Ask for file name to reboot from
+# memorydisk=<n> Set memorydisk size to <n> KB
+# quiet Show aprint_naive output
+# verbose Show aprint_normal and aprint_verbose output
+#options BOOT_ARGS="\"\""
+options BOOT_ARGS="\"verbose\""
+
+config netbsd root on ? type ?
+
+# The main bus device
+mainbus0 at root
+
+# The boot cpu and secondary CPUs
+cpu0 at mainbus?
+#cpu? at mainbus? # Multiprocessor
+
+# A9 core devices
+armperiph0 at mainbus?
+armgic0 at armperiph? # Interrupt Controller
+armgtmr0 at armperiph? # Generic Timer
+
+# Exynos SoC
+exyo0 at mainbus?
+
+# Integrated Samsung UARTs
+#sscom* at exyo0 port ? # UART ?
+sscom2 at exyo0 port 2 # UART2
+
+# Exynos Watchdog Timer
+#exyowdt0 at exyo0 # watchdog
+
+# GPIO
+exyogpio0 at exyo0
+gpio* at exyogpio?
+
+# On-board USB
+exyousb* at exyo0
+ohci* at exyousb?
+ehci* at exyousb?
+usb* at ohci?
+usb* at ehci?
+
+# Network phy for the LAN9730
+ukphy* at mii? phy ? # generic unknown PHYs
+
+# I2C devices
+exyoiic0 at exyo0
+iic* at exyoiic?
+
+# SATA
+#ahcisata* at exyno0
+#atabus* at ata?
+#wd* at atabus? drive ?
+
+
+# serial console connectivity
+options SSCOM2CONSOLE, CONSPEED=115200
+
+# include all USB devices
+include "dev/usb/usbdevices.config"
+
+midi* at midibus?
+
+
+# Pseudo-Devices
+
+# disk/mass storage pseudo-devices
+#pseudo-device md # memory disk device (ramdisk)
+#pseudo-device vnd # disk-like interface to files
+#pseudo-device fss # file system snapshot device
+#pseudo-device putter # for puffs and pud
+pseudo-device drvctl # driver control
+
+# network pseudo-devices
+pseudo-device bpfilter # Berkeley packet filter
+pseudo-device loop # network loopback
+#pseudo-device kttcp # network loopback
+
+# miscellaneous pseudo-devices
+pseudo-device pty # pseudo-terminals
+#options RND_COM
+#pseudo-device clockctl # user control of clock subsystem
+pseudo-device ksyms # /dev/ksyms
+#pseudo-device lockstat # lock profiling
