Module Name: src
Committed By: macallan
Date: Wed Feb 18 16:47:59 UTC 2015
Modified Files:
src/sys/arch/sgimips/conf: files.sgimips
src/sys/arch/sgimips/dev: crime.c crmfb.c ctl.c dpclock.c dsclock.c
imc.c int.c pic.c zs.c
src/sys/arch/sgimips/gio: gio.c pci_gio.c
src/sys/arch/sgimips/hpc: hpc.c if_sq.c panel.c pckbc_hpc.c wdsc.c
src/sys/arch/sgimips/include: bus_defs.h bus_funcs.h pci_machdep.h
src/sys/arch/sgimips/ioc: ioc.c oioc.c
src/sys/arch/sgimips/mace: com_mace.c mace.c mcclock_mace.c pci_mace.c
pcireg_mace.h
src/sys/arch/sgimips/pci: pci_machdep.c
src/sys/arch/sgimips/sgimips: bus.c console.c
Log Message:
switch sgimips to common bus_dma and bus_space in arch/mips/
Tested on O2 and Indy.
Things that are compile-tested only for lack of hardware:
- GIO ethernet cards with PCI bridges
- IP2x hardware not found on Indy
- IP1x
To generate a diff of this commit:
cvs rdiff -u -r1.52 -r1.53 src/sys/arch/sgimips/conf/files.sgimips
cvs rdiff -u -r1.37 -r1.38 src/sys/arch/sgimips/dev/crime.c
cvs rdiff -u -r1.39 -r1.40 src/sys/arch/sgimips/dev/crmfb.c
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/sgimips/dev/ctl.c
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/sgimips/dev/dpclock.c
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/sgimips/dev/dsclock.c
cvs rdiff -u -r1.33 -r1.34 src/sys/arch/sgimips/dev/imc.c
cvs rdiff -u -r1.27 -r1.28 src/sys/arch/sgimips/dev/int.c
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/sgimips/dev/pic.c
cvs rdiff -u -r1.38 -r1.39 src/sys/arch/sgimips/dev/zs.c
cvs rdiff -u -r1.33 -r1.34 src/sys/arch/sgimips/gio/gio.c
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/sgimips/gio/pci_gio.c
cvs rdiff -u -r1.67 -r1.68 src/sys/arch/sgimips/hpc/hpc.c
cvs rdiff -u -r1.43 -r1.44 src/sys/arch/sgimips/hpc/if_sq.c
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/sgimips/hpc/panel.c
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/sgimips/hpc/pckbc_hpc.c
cvs rdiff -u -r1.33 -r1.34 src/sys/arch/sgimips/hpc/wdsc.c
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/sgimips/include/bus_defs.h \
src/sys/arch/sgimips/include/bus_funcs.h
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/sgimips/include/pci_machdep.h
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/sgimips/ioc/ioc.c
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/sgimips/ioc/oioc.c
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/sgimips/mace/com_mace.c
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/sgimips/mace/mace.c
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/sgimips/mace/mcclock_mace.c
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/sgimips/mace/pci_mace.c
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/sgimips/mace/pcireg_mace.h
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/sgimips/pci/pci_machdep.c
cvs rdiff -u -r1.65 -r1.66 src/sys/arch/sgimips/sgimips/bus.c
cvs rdiff -u -r1.43 -r1.44 src/sys/arch/sgimips/sgimips/console.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/sgimips/conf/files.sgimips
diff -u src/sys/arch/sgimips/conf/files.sgimips:1.52 src/sys/arch/sgimips/conf/files.sgimips:1.53
--- src/sys/arch/sgimips/conf/files.sgimips:1.52 Sun Jul 20 10:22:55 2014
+++ src/sys/arch/sgimips/conf/files.sgimips Wed Feb 18 16:47:58 2015
@@ -1,4 +1,4 @@
-# $NetBSD: files.sgimips,v 1.52 2014/07/20 10:22:55 alnsn Exp $
+# $NetBSD: files.sgimips,v 1.53 2015/02/18 16:47:58 macallan Exp $
maxpartitions 16
@@ -26,8 +26,7 @@ file arch/sgimips/sgimips/console.c
file arch/sgimips/sgimips/disksubr.c
file arch/sgimips/sgimips/machdep.c
-file dev/bus_dma/bus_dmamem_common.c
-
+file arch/mips/mips/bus_dma.c
file arch/mips/mips/mips3_clock.c mips3
file arch/mips/mips/mips3_clockintr.c mips3
Index: src/sys/arch/sgimips/dev/crime.c
diff -u src/sys/arch/sgimips/dev/crime.c:1.37 src/sys/arch/sgimips/dev/crime.c:1.38
--- src/sys/arch/sgimips/dev/crime.c:1.37 Sat May 17 20:44:08 2014
+++ src/sys/arch/sgimips/dev/crime.c Wed Feb 18 16:47:58 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: crime.c,v 1.37 2014/05/17 20:44:08 mrg Exp $ */
+/* $NetBSD: crime.c,v 1.38 2015/02/18 16:47:58 macallan Exp $ */
/*
* Copyright (c) 2004 Christopher SEKIYA
@@ -38,7 +38,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: crime.c,v 1.37 2014/05/17 20:44:08 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: crime.c,v 1.38 2015/02/18 16:47:58 macallan Exp $");
#include <sys/param.h>
#include <sys/device.h>
@@ -108,9 +108,9 @@ crime_attach(device_t parent, device_t s
uint32_t startctr, endctr, cps;
sc->sc_dev = self;
- crm_iot = SGIMIPS_BUS_SPACE_CRIME;
+ crm_iot = normal_memt;
- if (bus_space_map(crm_iot, ma->ma_addr, 0 /* XXX */,
+ if (bus_space_map(crm_iot, ma->ma_addr, 0x1000,
BUS_SPACE_MAP_LINEAR, &crm_ioh))
panic("%s: can't map I/O space", __func__);
Index: src/sys/arch/sgimips/dev/crmfb.c
diff -u src/sys/arch/sgimips/dev/crmfb.c:1.39 src/sys/arch/sgimips/dev/crmfb.c:1.40
--- src/sys/arch/sgimips/dev/crmfb.c:1.39 Tue Jan 20 12:13:04 2015
+++ src/sys/arch/sgimips/dev/crmfb.c Wed Feb 18 16:47:58 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: crmfb.c,v 1.39 2015/01/20 12:13:04 macallan Exp $ */
+/* $NetBSD: crmfb.c,v 1.40 2015/02/18 16:47:58 macallan Exp $ */
/*-
* Copyright (c) 2007 Jared D. McNeill <[email protected]>
@@ -32,14 +32,13 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: crmfb.c,v 1.39 2015/01/20 12:13:04 macallan Exp $");
+__KERNEL_RCSID(0, "$NetBSD: crmfb.c,v 1.40 2015/02/18 16:47:58 macallan Exp $");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/malloc.h>
-#define _SGIMIPS_BUS_DMA_PRIVATE
#include <machine/autoconf.h>
#include <sys/bus.h>
#include <machine/machtype.h>
@@ -262,7 +261,7 @@ crmfb_attach(device_t parent, device_t s
ma = (struct mainbus_attach_args *)opaque;
- sc->sc_iot = SGIMIPS_BUS_SPACE_CRIME;
+ sc->sc_iot = normal_memt;
sc->sc_dmat = &sgimips_default_bus_dma_tag;
sc->sc_wsmode = WSDISPLAYIO_MODE_EMUL;
@@ -571,7 +570,7 @@ crmfb_mmap(void *v, void *vs, off_t offs
if (offset >= 0 && offset < (0x100000 * sc->sc_tiles_x)) {
pa = bus_dmamem_mmap(sc->sc_dmat, sc->sc_dma.segs,
sc->sc_dma.nsegs, offset, prot,
- BUS_DMA_WAITOK | BUS_DMA_COHERENT);
+ BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_PREFETCHABLE);
return pa;
}
#endif
@@ -588,8 +587,8 @@ crmfb_mmap(void *v, void *vs, off_t offs
if ((offset >= 0x15010000) && (offset < 0x15030000))
return bus_dmamem_mmap(sc->sc_dmat, sc->sc_dma.segs,
sc->sc_dma.nsegs,
- offset + (0x100000 * sc->sc_tiles_x) - 0x15010000,
- prot, BUS_DMA_WAITOK | BUS_DMA_COHERENT);
+ offset + (0x100000 * sc->sc_tiles_x) - 0x15010000, prot,
+ BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_PREFETCHABLE);
return -1;
}
Index: src/sys/arch/sgimips/dev/ctl.c
diff -u src/sys/arch/sgimips/dev/ctl.c:1.3 src/sys/arch/sgimips/dev/ctl.c:1.4
--- src/sys/arch/sgimips/dev/ctl.c:1.3 Fri Jul 1 18:53:46 2011
+++ src/sys/arch/sgimips/dev/ctl.c Wed Feb 18 16:47:58 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: ctl.c,v 1.3 2011/07/01 18:53:46 dyoung Exp $ */
+/* $NetBSD: ctl.c,v 1.4 2015/02/18 16:47:58 macallan Exp $ */
/*
* Copyright (c) 2009 Stephen M. Rumble
@@ -28,7 +28,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ctl.c,v 1.3 2011/07/01 18:53:46 dyoung Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ctl.c,v 1.4 2015/02/18 16:47:58 macallan Exp $");
#include <sys/param.h>
#include <sys/kernel.h>
@@ -98,8 +98,8 @@ ctl_attach(device_t parent, device_t sel
sc->sc_dev = self;
csc = sc;
- sc->iot = SGIMIPS_BUS_SPACE_NORMAL;
- if (bus_space_map(sc->iot, ma->ma_addr, 0,
+ sc->iot = normal_memt;
+ if (bus_space_map(sc->iot, ma->ma_addr, 0x10000 /* XXX */,
BUS_SPACE_MAP_LINEAR, &sc->ioh))
panic("ctl_attach: could not allocate memory\n");
Index: src/sys/arch/sgimips/dev/dpclock.c
diff -u src/sys/arch/sgimips/dev/dpclock.c:1.5 src/sys/arch/sgimips/dev/dpclock.c:1.6
--- src/sys/arch/sgimips/dev/dpclock.c:1.5 Thu Nov 20 16:34:26 2014
+++ src/sys/arch/sgimips/dev/dpclock.c Wed Feb 18 16:47:58 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: dpclock.c,v 1.5 2014/11/20 16:34:26 christos Exp $ */
+/* $NetBSD: dpclock.c,v 1.6 2015/02/18 16:47:58 macallan Exp $ */
/*
* Copyright (c) 2001 Erik Reid
@@ -55,6 +55,7 @@ struct dpclock_softc {
/* RTC registers */
bus_space_tag_t sc_rtct;
bus_space_handle_t sc_rtch;
+ int sc_offset;
};
static int dpclock_match(device_t, cfdata_t, void *);
@@ -87,6 +88,20 @@ dpclock_match(device_t parent, cfdata_t
}
static void
+writereg(struct dpclock_softc *sc, uint32_t reg, uint8_t val)
+{
+ bus_space_write_1(sc->sc_rtct, sc->sc_rtch,
+ (reg << 2) + sc->sc_offset, val);
+}
+
+static uint8_t
+readreg(struct dpclock_softc *sc, uint32_t reg)
+{
+ return bus_space_read_1(sc->sc_rtct, sc->sc_rtch,
+ (reg << 2) + sc->sc_offset);
+}
+
+static void
dpclock_attach(device_t parent, device_t self, void *aux)
{
struct dpclock_softc *sc = device_private(self);
@@ -95,14 +110,15 @@ dpclock_attach(device_t parent, device_t
printf("\n");
+ sc->sc_rtct = normal_memt;
/*
* All machines have one byte register per word. IP6/IP10 use
* the MSB, others the LSB.
*/
if (mach_type == MACH_SGI_IP12 || mach_type == MACH_SGI_IP20)
- sc->sc_rtct = SGIMIPS_BUS_SPACE_HPC;
+ sc->sc_offset = 3;
else
- sc->sc_rtct = SGIMIPS_BUS_SPACE_IP6_DPCLOCK;
+ sc->sc_offset = 0;
if ((err = bus_space_map(sc->sc_rtct, ma->ma_addr, 0x1ffff,
BUS_SPACE_MAP_LINEAR, &sc->sc_rtch)) != 0) {
@@ -131,14 +147,14 @@ dpclock_gettime(struct todr_chip_handle
u_int8_t regs[32];
s = splhigh();
- i = bus_space_read_1(sc->sc_rtct, sc->sc_rtch, DP8573A_TIMESAVE_CTL);
+ i = readreg(sc, DP8573A_TIMESAVE_CTL);
j = i | DP8573A_TIMESAVE_CTL_EN;
- bus_space_write_1(sc->sc_rtct, sc->sc_rtch, DP8573A_TIMESAVE_CTL, j);
- bus_space_write_1(sc->sc_rtct, sc->sc_rtch, DP8573A_TIMESAVE_CTL, i);
+ writereg(sc, DP8573A_TIMESAVE_CTL, j);
+ writereg(sc, DP8573A_TIMESAVE_CTL, i);
splx(s);
for (i = 0; i < 32; i++)
- regs[i] = bus_space_read_1(sc->sc_rtct, sc->sc_rtch, i);
+ regs[i] = readreg(sc, i);
dt.dt_sec = bcdtobin(regs[DP8573A_SAVE_SEC]);
dt.dt_min = bcdtobin(regs[DP8573A_SAVE_MIN]);
@@ -194,14 +210,14 @@ dpclock_settime(struct todr_chip_handle
clock_secs_to_ymdhms((time_t)(tv->tv_sec + (tv->tv_usec > 500000)),&dt);
s = splhigh();
- i = bus_space_read_1(sc->sc_rtct, sc->sc_rtch, DP8573A_TIMESAVE_CTL);
+ i = readreg(sc, DP8573A_TIMESAVE_CTL);
j = i | DP8573A_TIMESAVE_CTL_EN;
- bus_space_write_1(sc->sc_rtct, sc->sc_rtch, DP8573A_TIMESAVE_CTL, j);
- bus_space_write_1(sc->sc_rtct, sc->sc_rtch, DP8573A_TIMESAVE_CTL, i);
+ writereg(sc, DP8573A_TIMESAVE_CTL, j);
+ writereg(sc, DP8573A_TIMESAVE_CTL, i);
splx(s);
for (i = 0; i < 32; i++)
- regs[i] = bus_space_read_1(sc->sc_rtct, sc->sc_rtch, i);
+ regs[i] = readreg(sc, i);
regs[DP8573A_SUBSECOND] = 0;
regs[DP8573A_SECOND] = bintobcd(dt.dt_sec);
@@ -213,15 +229,14 @@ dpclock_settime(struct todr_chip_handle
regs[DP8573A_YEAR] = bintobcd(TO_IRIX_YEAR(dt.dt_year));
s = splhigh();
- i = bus_space_read_1(sc->sc_rtct, sc->sc_rtch, DP8573A_RT_MODE);
+ i = readreg(sc, DP8573A_RT_MODE);
j = i & ~DP8573A_RT_MODE_CLKSS;
- bus_space_write_1(sc->sc_rtct, sc->sc_rtch, DP8573A_RT_MODE, j);
+ writereg(sc, DP8573A_RT_MODE, j);
for (i = 0; i < 10; i++)
- bus_space_write_1(sc->sc_rtct, sc->sc_rtch, DP8573A_COUNTERS +i,
- regs[DP8573A_COUNTERS + i]);
+ writereg(sc, DP8573A_COUNTERS +i, regs[DP8573A_COUNTERS + i]);
- bus_space_write_1(sc->sc_rtct, sc->sc_rtch, DP8573A_RT_MODE, i);
+ writereg(sc, DP8573A_RT_MODE, i);
splx(s);
return (0);
Index: src/sys/arch/sgimips/dev/dsclock.c
diff -u src/sys/arch/sgimips/dev/dsclock.c:1.6 src/sys/arch/sgimips/dev/dsclock.c:1.7
--- src/sys/arch/sgimips/dev/dsclock.c:1.6 Thu Nov 20 16:34:26 2014
+++ src/sys/arch/sgimips/dev/dsclock.c Wed Feb 18 16:47:58 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: dsclock.c,v 1.6 2014/11/20 16:34:26 christos Exp $ */
+/* $NetBSD: dsclock.c,v 1.7 2015/02/18 16:47:58 macallan Exp $ */
/*
* Copyright (c) 2001 Rafal K. Boni
@@ -34,7 +34,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: dsclock.c,v 1.6 2014/11/20 16:34:26 christos Exp $");
+__KERNEL_RCSID(0, "$NetBSD: dsclock.c,v 1.7 2015/02/18 16:47:58 macallan Exp $");
#include <sys/param.h>
#include <sys/kernel.h>
@@ -72,9 +72,9 @@ CFATTACH_DECL_NEW(dsclock, sizeof(struct
dsclock_match, dsclock_attach, NULL, NULL);
#define ds1286_write(sc, reg, datum) \
- bus_space_write_1((sc)->sc_rtct, (sc)->sc_rtch, (reg), (datum))
+ bus_space_write_1((sc)->sc_rtct, (sc)->sc_rtch, (reg << 2) + 3, (datum))
#define ds1286_read(sc, reg) \
- bus_space_read_1((sc)->sc_rtct, (sc)->sc_rtch, (reg))
+ bus_space_read_1((sc)->sc_rtct, (sc)->sc_rtch, (reg << 2) + 3)
static int
dsclock_match(device_t parent, cfdata_t cf, void *aux)
@@ -96,7 +96,7 @@ dsclock_attach(device_t parent, device_t
aprint_normal("\n");
- sc->sc_rtct = SGIMIPS_BUS_SPACE_HPC;
+ sc->sc_rtct = normal_memt;
if ((err = bus_space_map(sc->sc_rtct, ma->ma_addr, 0x1ffff,
BUS_SPACE_MAP_LINEAR, &sc->sc_rtch)) != 0) {
aprint_error_dev(self,
Index: src/sys/arch/sgimips/dev/imc.c
diff -u src/sys/arch/sgimips/dev/imc.c:1.33 src/sys/arch/sgimips/dev/imc.c:1.34
--- src/sys/arch/sgimips/dev/imc.c:1.33 Sat Oct 27 17:18:09 2012
+++ src/sys/arch/sgimips/dev/imc.c Wed Feb 18 16:47:58 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: imc.c,v 1.33 2012/10/27 17:18:09 chs Exp $ */
+/* $NetBSD: imc.c,v 1.34 2015/02/18 16:47:58 macallan Exp $ */
/*
* Copyright (c) 2001 Rafal K. Boni
@@ -28,7 +28,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: imc.c,v 1.33 2012/10/27 17:18:09 chs Exp $");
+__KERNEL_RCSID(0, "$NetBSD: imc.c,v 1.34 2015/02/18 16:47:58 macallan Exp $");
#include <sys/param.h>
#include <sys/device.h>
@@ -103,8 +103,8 @@ imc_attach(device_t parent, device_t sel
struct mainbus_attach_args *ma = aux;
uint32_t sysid;
- isc.iot = SGIMIPS_BUS_SPACE_HPC;
- if (bus_space_map(isc.iot, ma->ma_addr, 0,
+ isc.iot = normal_memt;
+ if (bus_space_map(isc.iot, ma->ma_addr, 0x100,
BUS_SPACE_MAP_LINEAR, &isc.ioh))
panic("imc_attach: could not allocate memory\n");
Index: src/sys/arch/sgimips/dev/int.c
diff -u src/sys/arch/sgimips/dev/int.c:1.27 src/sys/arch/sgimips/dev/int.c:1.28
--- src/sys/arch/sgimips/dev/int.c:1.27 Tue Jun 3 12:15:00 2014
+++ src/sys/arch/sgimips/dev/int.c Wed Feb 18 16:47:58 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: int.c,v 1.27 2014/06/03 12:15:00 macallan Exp $ */
+/* $NetBSD: int.c,v 1.28 2015/02/18 16:47:58 macallan Exp $ */
/*
* Copyright (c) 2009 Stephen M. Rumble
@@ -33,7 +33,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: int.c,v 1.27 2014/06/03 12:15:00 macallan Exp $");
+__KERNEL_RCSID(0, "$NetBSD: int.c,v 1.28 2015/02/18 16:47:58 macallan Exp $");
#define __INTR_PRIVATE
#include "opt_cputype.h"
@@ -141,8 +141,12 @@ int_attach(device_t parent, device_t sel
printf(" addr 0x%x\n", address);
- bus_space_map(iot, address, 0, 0, &ioh);
- iot = SGIMIPS_BUS_SPACE_NORMAL;
+ iot = normal_memt;
+ /*
+ * XXX INT1 registers are spread *way* out, but for now this should
+ * work
+ */
+ bus_space_map(iot, address, 0x100, 0, &ioh);
switch (mach_type) {
case MACH_SGI_IP6 | MACH_SGI_IP10:
Index: src/sys/arch/sgimips/dev/pic.c
diff -u src/sys/arch/sgimips/dev/pic.c:1.16 src/sys/arch/sgimips/dev/pic.c:1.17
--- src/sys/arch/sgimips/dev/pic.c:1.16 Sat Oct 27 17:18:09 2012
+++ src/sys/arch/sgimips/dev/pic.c Wed Feb 18 16:47:58 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: pic.c,v 1.16 2012/10/27 17:18:09 chs Exp $ */
+/* $NetBSD: pic.c,v 1.17 2015/02/18 16:47:58 macallan Exp $ */
/*
* Copyright (c) 2002 Steve Rumble
@@ -28,7 +28,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pic.c,v 1.16 2012/10/27 17:18:09 chs Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pic.c,v 1.17 2015/02/18 16:47:58 macallan Exp $");
#include <sys/param.h>
#include <sys/device.h>
@@ -95,8 +95,8 @@ pic_attach(device_t parent, device_t sel
struct pic_attach_args iaa;
struct mainbus_attach_args *ma = aux;
- psc.iot = SGIMIPS_BUS_SPACE_HPC;
- if (bus_space_map(psc.iot, ma->ma_addr, 0,
+ psc.iot = normal_memt;
+ if (bus_space_map(psc.iot, ma->ma_addr, 0x20010,
BUS_SPACE_MAP_LINEAR, &psc.ioh))
panic("pic_attach: could not allocate memory\n");
Index: src/sys/arch/sgimips/dev/zs.c
diff -u src/sys/arch/sgimips/dev/zs.c:1.38 src/sys/arch/sgimips/dev/zs.c:1.39
--- src/sys/arch/sgimips/dev/zs.c:1.38 Mon Mar 24 19:10:34 2014
+++ src/sys/arch/sgimips/dev/zs.c Wed Feb 18 16:47:58 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: zs.c,v 1.38 2014/03/24 19:10:34 christos Exp $ */
+/* $NetBSD: zs.c,v 1.39 2015/02/18 16:47:58 macallan Exp $ */
/*-
* Copyright (c) 1996, 2000 The NetBSD Foundation, Inc.
@@ -37,7 +37,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.38 2014/03/24 19:10:34 christos Exp $");
+__KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.39 2015/02/18 16:47:58 macallan Exp $");
#include "opt_ddb.h"
#include "opt_kgdb.h"
@@ -530,9 +530,11 @@ zs_read_reg(struct zs_chanstate *cs, uin
uint8_t val;
struct zs_channel *zsc = (struct zs_channel *)cs;
- bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, reg);
+ bus_space_write_1(zsc->cs_bustag, zsc->cs_regs,
+ (ZS_REG_CSR << 2) + 3, reg);
ZS_DELAY();
- val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR);
+ val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs,
+ (ZS_REG_CSR << 2) + 3);
ZS_DELAY();
return val;
}
@@ -542,9 +544,11 @@ zs_write_reg(struct zs_chanstate *cs, ui
{
struct zs_channel *zsc = (struct zs_channel *)cs;
- bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, reg);
+ bus_space_write_1(zsc->cs_bustag, zsc->cs_regs,
+ (ZS_REG_CSR << 2) + 3, reg);
ZS_DELAY();
- bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, val);
+ bus_space_write_1(zsc->cs_bustag, zsc->cs_regs,
+ (ZS_REG_CSR << 2) + 3, val);
ZS_DELAY();
}
@@ -554,7 +558,8 @@ zs_read_csr(struct zs_chanstate *cs)
struct zs_channel *zsc = (struct zs_channel *)cs;
uint8_t val;
- val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR);
+ val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs,
+ (ZS_REG_CSR << 2) + 3);
ZS_DELAY();
return val;
}
@@ -564,7 +569,8 @@ zs_write_csr(struct zs_chanstate *cs, ui
{
struct zs_channel *zsc = (struct zs_channel *)cs;
- bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, val);
+ bus_space_write_1(zsc->cs_bustag, zsc->cs_regs,
+ (ZS_REG_CSR << 2) + 3, val);
ZS_DELAY();
}
@@ -574,7 +580,8 @@ zs_read_data(struct zs_chanstate *cs)
struct zs_channel *zsc = (struct zs_channel *)cs;
uint8_t val;
- val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_DATA);
+ val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs,
+ (ZS_REG_DATA << 2) + 3);
ZS_DELAY();
return val;
}
@@ -584,7 +591,8 @@ zs_write_data(struct zs_chanstate *cs, u
{
struct zs_channel *zsc = (struct zs_channel *)cs;
- bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_DATA, val);
+ bus_space_write_1(zsc->cs_bustag, zsc->cs_regs,
+ (ZS_REG_DATA << 2) + 3, val);
ZS_DELAY();
}
Index: src/sys/arch/sgimips/gio/gio.c
diff -u src/sys/arch/sgimips/gio/gio.c:1.33 src/sys/arch/sgimips/gio/gio.c:1.34
--- src/sys/arch/sgimips/gio/gio.c:1.33 Sat Oct 27 17:18:09 2012
+++ src/sys/arch/sgimips/gio/gio.c Wed Feb 18 16:47:58 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: gio.c,v 1.33 2012/10/27 17:18:09 chs Exp $ */
+/* $NetBSD: gio.c,v 1.34 2015/02/18 16:47:58 macallan Exp $ */
/*
* Copyright (c) 2000 Soren S. Jorvang
@@ -33,7 +33,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: gio.c,v 1.33 2012/10/27 17:18:09 chs Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gio.c,v 1.34 2015/02/18 16:47:58 macallan Exp $");
#include "opt_ddb.h"
@@ -41,7 +41,6 @@ __KERNEL_RCSID(0, "$NetBSD: gio.c,v 1.33
#include <sys/systm.h>
#include <sys/device.h>
-#define _SGIMIPS_BUS_DMA_PRIVATE
#include <sys/bus.h>
#include <machine/machtype.h>
#include <machine/sysconf.h>
@@ -208,7 +207,8 @@ gio_attach(device_t parent, device_t sel
ga.ga_slot = -1;
ga.ga_addr = gfx_bases[i].base;
- ga.ga_iot = SGIMIPS_BUS_SPACE_NORMAL;
+ ga.ga_iot = normal_memt;
+ /* XXX bus_space_map() */
ga.ga_ioh = MIPS_PHYS_TO_KSEG1(ga.ga_addr);
ga.ga_dmat = &sgimips_default_bus_dma_tag;
ga.ga_product = -1;
@@ -252,7 +252,7 @@ gio_attach(device_t parent, device_t sel
ga.ga_slot = slot_bases[i].slot;
ga.ga_addr = slot_bases[i].base;
- ga.ga_iot = SGIMIPS_BUS_SPACE_NORMAL;
+ ga.ga_iot = normal_memt;
ga.ga_ioh = MIPS_PHYS_TO_KSEG1(ga.ga_addr);
ga.ga_dmat = &sgimips_default_bus_dma_tag;
@@ -366,7 +366,7 @@ gio_cnattach(void)
ga.ga_slot = -1;
ga.ga_addr = gfx_bases[i].base;
- ga.ga_iot = SGIMIPS_BUS_SPACE_NORMAL;
+ ga.ga_iot = normal_memt;
ga.ga_ioh = MIPS_PHYS_TO_KSEG1(ga.ga_addr);
ga.ga_dmat = &sgimips_default_bus_dma_tag;
ga.ga_product = -1;
Index: src/sys/arch/sgimips/gio/pci_gio.c
diff -u src/sys/arch/sgimips/gio/pci_gio.c:1.13 src/sys/arch/sgimips/gio/pci_gio.c:1.14
--- src/sys/arch/sgimips/gio/pci_gio.c:1.13 Wed Apr 2 00:46:11 2014
+++ src/sys/arch/sgimips/gio/pci_gio.c Wed Feb 18 16:47:58 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: pci_gio.c,v 1.13 2014/04/02 00:46:11 ozaki-r Exp $ */
+/* $NetBSD: pci_gio.c,v 1.14 2015/02/18 16:47:58 macallan Exp $ */
/*
* Copyright (c) 2006 Stephen M. Rumble
@@ -25,7 +25,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_gio.c,v 1.13 2014/04/02 00:46:11 ozaki-r Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_gio.c,v 1.14 2015/02/18 16:47:58 macallan Exp $");
/*
* Glue for PCI devices that are connected to the GIO bus by various little
@@ -102,6 +102,10 @@ static void giopci_intr_disestablish(voi
CFATTACH_DECL_NEW(giopci, sizeof(struct giopci_softc),
giopci_match, giopci_attach, NULL, NULL);
+static void pcimem_bus_mem_init(bus_space_tag_t, void *);
+static struct mips_bus_space pcimem_mbst;
+bus_space_tag_t gio_pci_memt = NULL;
+
static int
giopci_match(device_t parent, cfdata_t match, void *aux)
{
@@ -145,6 +149,9 @@ giopci_attach(device_t parent, device_t
sc->sc_slot = ga->ga_slot;
sc->sc_gprid = GIO_PRODUCT_PRODUCTID(ga->ga_product);
+ pcimem_bus_mem_init(&pcimem_mbst, NULL);
+ gio_pci_memt = &pcimem_mbst;
+
if (mach_type == MACH_SGI_IP22 &&
mach_subtype == MACH_SGI_IP22_FULLHOUSE)
arb = GIO_ARB_RT | GIO_ARB_MST | GIO_ARB_PIPE;
@@ -220,7 +227,7 @@ giopci_attach(device_t parent, device_t
#endif
memset(&pba, 0, sizeof(pba));
- pba.pba_memt = SGIMIPS_BUS_SPACE_MEM;
+ pba.pba_memt = gio_pci_memt;
pba.pba_dmat = ga->ga_dmat;
pba.pba_pc = pc;
pba.pba_flags = PCI_FLAGS_MEM_OKAY;
@@ -322,3 +329,14 @@ giopci_intr_disestablish(void *cookie)
panic("giopci_intr_disestablish: impossible.");
}
+
+#define CHIP pcimem
+#define CHIP_MEM /* defined */
+#define CHIP_WRONG_ENDIAN
+
+#define CHIP_W1_BUS_START(v) 0x00000000UL
+#define CHIP_W1_BUS_END(v) 0xffffffffUL
+#define CHIP_W1_SYS_START(v) 0x00000000UL
+#define CHIP_W1_SYS_END(v) 0xffffffffUL
+
+#include <mips/mips/bus_space_alignstride_chipdep.c>
Index: src/sys/arch/sgimips/hpc/hpc.c
diff -u src/sys/arch/sgimips/hpc/hpc.c:1.67 src/sys/arch/sgimips/hpc/hpc.c:1.68
--- src/sys/arch/sgimips/hpc/hpc.c:1.67 Sat Oct 27 17:18:09 2012
+++ src/sys/arch/sgimips/hpc/hpc.c Wed Feb 18 16:47:58 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: hpc.c,v 1.67 2012/10/27 17:18:09 chs Exp $ */
+/* $NetBSD: hpc.c,v 1.68 2015/02/18 16:47:58 macallan Exp $ */
/*
* Copyright (c) 2000 Soren S. Jorvang
@@ -35,7 +35,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: hpc.c,v 1.67 2012/10/27 17:18:09 chs Exp $");
+__KERNEL_RCSID(0, "$NetBSD: hpc.c,v 1.68 2015/02/18 16:47:58 macallan Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -44,7 +44,6 @@ __KERNEL_RCSID(0, "$NetBSD: hpc.c,v 1.67
#include <sys/reboot.h>
#include <sys/callout.h>
-#define _SGIMIPS_BUS_DMA_PRIVATE
#include <sys/bus.h>
#include <machine/machtype.h>
#include <machine/sysconf.h>
@@ -372,6 +371,12 @@ static int hpc_read_eeprom(int, bus_spac
CFATTACH_DECL_NEW(hpc, sizeof(struct hpc_softc),
hpc_match, hpc_attach, NULL, NULL);
+static void hpc_bus_mem_init(bus_space_tag_t, void *);
+
+static struct mips_bus_space hpc_mbst;
+bus_space_tag_t hpc_memt = NULL;
+
+
static int
hpc_match(device_t parent, cfdata_t cf, void *aux)
{
@@ -498,12 +503,15 @@ hpc_attach(device_t parent, device_t sel
}
}
- sc->sc_ct = SGIMIPS_BUS_SPACE_HPC;
+ hpc_bus_mem_init(&hpc_mbst, NULL);
+ hpc_memt = &hpc_mbst;
+
+ sc->sc_ct = normal_memt;
sc->sc_ch = ga->ga_ioh;
sc->sc_base = ga->ga_addr;
- hpc_read_eeprom(hpctype, SGIMIPS_BUS_SPACE_HPC,
+ hpc_read_eeprom(hpctype, normal_memt,
MIPS_PHYS_TO_KSEG1(sc->sc_base), ha.hpc_eeprom,
sizeof(ha.hpc_eeprom));
@@ -518,7 +526,7 @@ hpc_attach(device_t parent, device_t sel
ha.ha_irq = hd->hd_irq;
/* XXX This is disgusting. */
- ha.ha_st = SGIMIPS_BUS_SPACE_HPC;
+ ha.ha_st = normal_memt;
ha.ha_sh = MIPS_PHYS_TO_KSEG1(sc->sc_base);
ha.ha_dmat = &sgimips_default_bus_dma_tag;
if (hpctype == 3)
@@ -730,7 +738,7 @@ hpc_read_eeprom(int hpctype, bus_space_t
offset = (hpctype == 3) ? HPC3_EEPROM_DATA : HPC1_AUX_REGS;
- tag = SGIMIPS_BUS_SPACE_NORMAL;
+ tag = normal_memt;
if (bus_space_subregion(t, h, offset, 1, &bsh) != 0)
return (1);
@@ -755,3 +763,14 @@ hpc_read_eeprom(int hpctype, bus_space_t
return (0);
}
+
+#define CHIP hpc
+#define CHIP_MEM /* defined */
+#define CHIP_ALIGN_STRIDE 2
+#define CHIP_ACCESS_SIZE 4
+#define CHIP_W1_BUS_START(v) 0x00000000UL
+#define CHIP_W1_BUS_END(v) 0xffffffffUL
+#define CHIP_W1_SYS_START(v) 0x00000000UL
+#define CHIP_W1_SYS_END(v) 0xffffffffUL
+
+#include <mips/mips/bus_space_alignstride_chipdep.c>
Index: src/sys/arch/sgimips/hpc/if_sq.c
diff -u src/sys/arch/sgimips/hpc/if_sq.c:1.43 src/sys/arch/sgimips/hpc/if_sq.c:1.44
--- src/sys/arch/sgimips/hpc/if_sq.c:1.43 Thu Feb 2 19:43:00 2012
+++ src/sys/arch/sgimips/hpc/if_sq.c Wed Feb 18 16:47:58 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: if_sq.c,v 1.43 2012/02/02 19:43:00 tls Exp $ */
+/* $NetBSD: if_sq.c,v 1.44 2015/02/18 16:47:58 macallan Exp $ */
/*
* Copyright (c) 2001 Rafal K. Boni
@@ -33,7 +33,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_sq.c,v 1.43 2012/02/02 19:43:00 tls Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_sq.c,v 1.44 2015/02/18 16:47:58 macallan Exp $");
#include <sys/param.h>
@@ -124,9 +124,9 @@ CFATTACH_DECL_NEW(sq, sizeof(struct sq_s
#define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN)
#define sq_seeq_read(sc, off) \
- bus_space_read_1(sc->sc_regt, sc->sc_regh, off)
+ bus_space_read_1(sc->sc_regt, sc->sc_regh, (off << 2) + 3)
#define sq_seeq_write(sc, off, val) \
- bus_space_write_1(sc->sc_regt, sc->sc_regh, off, val)
+ bus_space_write_1(sc->sc_regt, sc->sc_regh, (off << 2) + 3, val)
#define sq_hpc_read(sc, off) \
bus_space_read_4(sc->sc_hpct, sc->sc_hpch, off)
Index: src/sys/arch/sgimips/hpc/panel.c
diff -u src/sys/arch/sgimips/hpc/panel.c:1.2 src/sys/arch/sgimips/hpc/panel.c:1.3
--- src/sys/arch/sgimips/hpc/panel.c:1.2 Wed Feb 16 23:44:19 2011
+++ src/sys/arch/sgimips/hpc/panel.c Wed Feb 18 16:47:58 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: panel.c,v 1.2 2011/02/16 23:44:19 jmcneill Exp $ */
+/* $NetBSD: panel.c,v 1.3 2015/02/18 16:47:58 macallan Exp $ */
/*-
* Copyright (c) 2009 Michael Lorenz
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: panel.c,v 1.2 2011/02/16 23:44:19 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: panel.c,v 1.3 2015/02/18 16:47:58 macallan Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -96,7 +96,7 @@ panel_attach(device_t parent, device_t s
aprint_normal("\n");
if (bus_space_subregion(haa->ha_st, haa->ha_sh, haa->ha_devoff,
- 0x1, /* just a single register */
+ 0x4, /* just a single register */
&sc->sc_hreg)) {
aprint_error(": unable to map panel register\n");
return;
@@ -126,8 +126,8 @@ panel_intr(void *cookie)
struct panel_softc *sc = cookie;
uint8_t reg;
- reg = bus_space_read_1(sc->sc_tag, sc->sc_hreg, 0);
- bus_space_write_1(sc->sc_tag, sc->sc_hreg, 0,
+ reg = bus_space_read_4(sc->sc_tag, sc->sc_hreg, 0);
+ bus_space_write_4(sc->sc_tag, sc->sc_hreg, 0,
IOC_PANEL_VDOWN_IRQ | IOC_PANEL_VUP_IRQ | IOC_PANEL_POWER_IRQ);
if ((reg & IOC_PANEL_POWER_IRQ) == 0) {
if (!sc->sc_fired)
Index: src/sys/arch/sgimips/hpc/pckbc_hpc.c
diff -u src/sys/arch/sgimips/hpc/pckbc_hpc.c:1.9 src/sys/arch/sgimips/hpc/pckbc_hpc.c:1.10
--- src/sys/arch/sgimips/hpc/pckbc_hpc.c:1.9 Sat Mar 15 13:23:24 2008
+++ src/sys/arch/sgimips/hpc/pckbc_hpc.c Wed Feb 18 16:47:58 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: pckbc_hpc.c,v 1.9 2008/03/15 13:23:24 cube Exp $ */
+/* $NetBSD: pckbc_hpc.c,v 1.10 2015/02/18 16:47:58 macallan Exp $ */
/*
* Copyright (c) 2003 Christopher SEKIYA
@@ -33,7 +33,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pckbc_hpc.c,v 1.9 2008/03/15 13:23:24 cube Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pckbc_hpc.c,v 1.10 2015/02/18 16:47:58 macallan Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -111,7 +111,7 @@ pckbc_hpc_attach(device_t parent, device
t = malloc(sizeof(struct pckbc_internal), M_DEVBUF,
M_WAITOK | M_ZERO);
- t->t_iot = haa->ha_st;
+ t->t_iot = hpc_memt;
t->t_ioh_d = ioh_d;
t->t_ioh_c = ioh_c;
t->t_addr = haa->ha_sh;
Index: src/sys/arch/sgimips/hpc/wdsc.c
diff -u src/sys/arch/sgimips/hpc/wdsc.c:1.33 src/sys/arch/sgimips/hpc/wdsc.c:1.34
--- src/sys/arch/sgimips/hpc/wdsc.c:1.33 Sat Oct 27 17:18:09 2012
+++ src/sys/arch/sgimips/hpc/wdsc.c Wed Feb 18 16:47:58 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: wdsc.c,v 1.33 2012/10/27 17:18:09 chs Exp $ */
+/* $NetBSD: wdsc.c,v 1.34 2015/02/18 16:47:58 macallan Exp $ */
/*
* Copyright (c) 2001 Wayne Knowles
@@ -37,7 +37,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: wdsc.c,v 1.33 2012/10/27 17:18:09 chs Exp $");
+__KERNEL_RCSID(0, "$NetBSD: wdsc.c,v 1.34 2015/02/18 16:47:58 macallan Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -105,9 +105,6 @@ wdsc_match(device_t parent, cfdata_t cf,
haa->hpc_regs->scsi0_ctl);
asr = MIPS_PHYS_TO_KSEG1(haa->ha_sh + haa->ha_devoff);
- /* XXX: hpc1 offset due to SGIMIPS_BUS_SPACE_HPC brain damage */
- asr = (asr + 3) & ~0x3;
-
if (platform.badaddr((void *)reset, sizeof(reset)))
return 0;
@@ -149,14 +146,14 @@ wdsc_attach(device_t parent, device_t se
wsc->sc_hpcdma.hpc = haa->hpc_regs;
if ((err = bus_space_subregion(haa->ha_st, haa->ha_sh,
- haa->ha_devoff + 0, 4, &sc->sc_asr_regh)) != 0) {
+ haa->ha_devoff + 0 + 3, 1, &sc->sc_asr_regh)) != 0) {
printf(": unable to map asr reg, err=%d\n", err);
return;
}
if ((err = bus_space_subregion(haa->ha_st, haa->ha_sh,
- haa->ha_devoff + 4, 4, &sc->sc_data_regh)) != 0) {
- printf(": unable to map asr reg, err=%d\n", err);
+ haa->ha_devoff + 4 + 3, 1, &sc->sc_data_regh)) != 0) {
+ printf(": unable to map data reg, err=%d\n", err);
return;
}
Index: src/sys/arch/sgimips/include/bus_defs.h
diff -u src/sys/arch/sgimips/include/bus_defs.h:1.1 src/sys/arch/sgimips/include/bus_defs.h:1.2
--- src/sys/arch/sgimips/include/bus_defs.h:1.1 Fri Jul 1 17:10:01 2011
+++ src/sys/arch/sgimips/include/bus_defs.h Wed Feb 18 16:47:58 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: bus_defs.h,v 1.1 2011/07/01 17:10:01 dyoung Exp $ */
+/* $NetBSD: bus_defs.h,v 1.2 2015/02/18 16:47:58 macallan Exp $ */
/*
* Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc.
@@ -35,173 +35,22 @@
#include <mips/locore.h>
-#define __BUS_SPACE_HAS_STREAM_METHODS
-
-/*
- * Utility macros; do not use outside this file.
- */
-#define __PB_TYPENAME_PREFIX(BITS) ___CONCAT(u_int,BITS)
-#define __PB_TYPENAME(BITS) ___CONCAT(__PB_TYPENAME_PREFIX(BITS),_t)
-
-/*
- * Bus address and size types
- */
-typedef uint64_t bus_addr_t;
-typedef uint64_t bus_size_t;
-
-/*
- * Access methods for bus resources and address space.
- */
-typedef int bus_space_tag_t;
-typedef u_long bus_space_handle_t;
-
/*
* Values for sgimips bus space tag, not to be used directly by MI code.
+ * XXX these need spacial handling
*/
-#define SGIMIPS_BUS_SPACE_NORMAL 0
-#define SGIMIPS_BUS_SPACE_IP6_DPCLOCK 1
-#define SGIMIPS_BUS_SPACE_HPC 2
-#define SGIMIPS_BUS_SPACE_MEM 3
-#define SGIMIPS_BUS_SPACE_MACE 4
-#define SGIMIPS_BUS_SPACE_IO 5
-#define SGIMIPS_BUS_SPACE_CRIME 6
-
-/*
- * int bus_space_map(bus_space_tag_t t, bus_addr_t addr,
- * bus_size_t size, int flags, bus_space_handle_t *bshp);
- *
- * Map a region of bus space.
- */
-
-#define BUS_SPACE_MAP_CACHEABLE 0x01
-#define BUS_SPACE_MAP_LINEAR 0x02
-#define BUS_SPACE_MAP_PREFETCHABLE 0x04
-
-#define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */
-#define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */
-
-#define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t)
-
-/*
- * Flags used in various bus DMA methods.
- */
-#define BUS_DMA_WAITOK 0x000 /* safe to sleep (pseudo-flag) */
-#define BUS_DMA_NOWAIT 0x001 /* not safe to sleep */
-#define BUS_DMA_ALLOCNOW 0x002 /* perform resource allocation now */
-#define BUS_DMA_COHERENT 0x004 /* hint: map memory DMA coherent */
-#define BUS_DMA_STREAMING 0x008 /* hint: sequential, unidirectional */
-#define BUS_DMA_BUS1 0x010 /* placeholders for bus functions... */
-#define BUS_DMA_BUS2 0x020
-#define BUS_DMA_BUS3 0x040
-#define BUS_DMA_BUS4 0x080
-#define BUS_DMA_READ 0x100 /* mapping is device -> memory only */
-#define BUS_DMA_WRITE 0x200 /* mapping is memory -> device only */
-#define BUS_DMA_NOCACHE 0x400 /* hint: map non-cached memory */
-
-#define SGIMIPS_DMAMAP_COHERENT 0x10000 /* no cache flush necessary on sync */
-
-/* Forwards needed by prototypes below. */
-struct mbuf;
-struct uio;
-/*
- * Operations performed by bus_dmamap_sync().
- */
-#define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */
-#define BUS_DMASYNC_POSTREAD 0x02 /* post-read synchronization */
-#define BUS_DMASYNC_PREWRITE 0x04 /* pre-write synchronization */
-#define BUS_DMASYNC_POSTWRITE 0x08 /* post-write synchronization */
+#include <mips/bus_space_defs.h>
-typedef struct sgimips_bus_dma_tag *bus_dma_tag_t;
-typedef struct sgimips_bus_dmamap *bus_dmamap_t;
+extern bus_space_tag_t normal_memt; /* normal, non-spaced */
+extern bus_space_tag_t mace_isa_memt; /* spaced, for MACE 'ISA' */
+extern bus_space_tag_t mace_pci_memt; /* address-twiddled to look little */
+extern bus_space_tag_t mace_pci_iot; /* endian with <32bit accesses */
+extern bus_space_tag_t gio_pci_memt; /* same, without windows */
+extern bus_space_tag_t hpc_memt; /* 8bit regs at 32bit spacing */
-#define BUS_DMA_TAG_VALID(t) ((t) != (bus_dma_tag_t)0)
-
-/*
- * bus_dma_segment_t
- *
- * Describes a single contiguous DMA transaction. Values
- * are suitable for programming into DMA registers.
- */
-struct sgimips_bus_dma_segment {
- bus_addr_t ds_addr; /* DMA address */
- bus_size_t ds_len; /* length of transfer */
- vaddr_t _ds_vaddr; /* virtual address, 0 if invalid */
-};
-typedef struct sgimips_bus_dma_segment bus_dma_segment_t;
+#include <mips/bus_dma_defs.h>
+#define SGIMIPS_DMAMAP_COHERENT _BUS_DMAMAP_COHERENT
-/*
- * bus_dma_tag_t
- *
- * A machine-dependent opaque type describing the implementation of
- * DMA for a given bus.
- */
-
-struct sgimips_bus_dma_tag {
- /*
- * XXX soren O2: 0x40000000
- * ikke endnu (bus.c)
- */
-#if 0
- bus_addr_t _wbase; /* DMA window base */
- bus_addr_t _wbase_swap; /* DMA window base (byteswapped) */
-#endif
-
- /*
- * DMA mapping methods.
- */
- int (*_dmamap_create)(bus_dma_tag_t, bus_size_t, int,
- bus_size_t, bus_size_t, int, bus_dmamap_t *);
- void (*_dmamap_destroy)(bus_dma_tag_t, bus_dmamap_t);
- int (*_dmamap_load)(bus_dma_tag_t, bus_dmamap_t, void *,
- bus_size_t, struct proc *, int);
- int (*_dmamap_load_mbuf)(bus_dma_tag_t, bus_dmamap_t,
- struct mbuf *, int);
- int (*_dmamap_load_uio)(bus_dma_tag_t, bus_dmamap_t,
- struct uio *, int);
- int (*_dmamap_load_raw)(bus_dma_tag_t, bus_dmamap_t,
- bus_dma_segment_t *, int, bus_size_t, int);
- void (*_dmamap_unload)(bus_dma_tag_t, bus_dmamap_t);
- void (*_dmamap_sync)(bus_dma_tag_t, bus_dmamap_t,
- bus_addr_t, bus_size_t, int);
-
- /*
- * DMA memory utility functions.
- */
- int (*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t,
- bus_size_t, bus_dma_segment_t *, int, int *, int);
- void (*_dmamem_free)(bus_dma_tag_t,
- bus_dma_segment_t *, int);
- int (*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *,
- int, size_t, void **, int);
- void (*_dmamem_unmap)(bus_dma_tag_t, void *, size_t);
- paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *,
- int, off_t, int, int);
-};
-
-/*
- * bus_dmamap_t
- *
- * Describes a DMA mapping.
- */
-struct sgimips_bus_dmamap {
- /*
- * PRIVATE MEMBERS: not for use my machine-independent code.
- */
- bus_size_t _dm_size; /* largest DMA transfer mappable */
- int _dm_segcnt; /* number of segs this map can map */
- bus_size_t _dm_maxmaxsegsz; /* fixed largest possible segment */
- bus_size_t _dm_boundary; /* don't cross this */
- int _dm_flags; /* misc. flags */
- struct vmspace *_dm_vmspace; /* vmspace that owns the mapping */
-
- /*
- * PUBLIC MEMBERS: these are used by machine-independent code.
- */
- bus_size_t dm_maxsegsz; /* largest possible segment */
- bus_size_t dm_mapsize; /* size of the mapping */
- int dm_nsegs; /* # valid segments in mapping */
- bus_dma_segment_t dm_segs[1]; /* segments; variable length */
-};
#endif /* _SGIMIPS_BUS_DEFS_H_ */
Index: src/sys/arch/sgimips/include/bus_funcs.h
diff -u src/sys/arch/sgimips/include/bus_funcs.h:1.1 src/sys/arch/sgimips/include/bus_funcs.h:1.2
--- src/sys/arch/sgimips/include/bus_funcs.h:1.1 Fri Jul 1 17:10:01 2011
+++ src/sys/arch/sgimips/include/bus_funcs.h Wed Feb 18 16:47:58 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: bus_funcs.h,v 1.1 2011/07/01 17:10:01 dyoung Exp $ */
+/* $NetBSD: bus_funcs.h,v 1.2 2015/02/18 16:47:58 macallan Exp $ */
/*
* Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc.
@@ -35,100 +35,15 @@
/* Initialization for bus_dmamap_sync, which differs from MIPS1 to MIPS3 */
+void mace_init_bus(void);
void sgimips_bus_dma_init(void);
-#define bus_space_read_stream_1 bus_space_read_1
-#define bus_space_write_stream_1 bus_space_write_1
-#define bus_space_read_region_stream_1 bus_space_read_reigion_1
-#define bus_space_read_multi_stream_1 bus_space_read_multi_1
-#define bus_space_write_multi_stream_1 bus_space_write_multi_1
-#define bus_space_write_region_stream_1 bus_space_write_region_1
+#include <mips/bus_space_funcs.h>
+
+#include <mips/bus_dma_funcs.h>
+extern struct mips_bus_dma_tag sgimips_default_bus_dma_tag;
-/*
- * Bus read/write barrier methods.
- *
- * void bus_space_barrier(bus_space_tag_t tag,
- * bus_space_handle_t bsh, bus_size_t offset,
- * bus_size_t len, int flags);
- *
- * On the MIPS, we just flush the write buffer.
- */
-#define bus_space_barrier(t, h, o, l, f) \
- ((void)((void)(t), (void)(h), (void)(o), (void)(l), (void)(f), \
- wbflush()))
-
-/* Forwards needed by prototypes below. */
-struct mbuf;
-struct uio;
-
-#define bus_dmamap_create(t, s, n, m, b, f, p) \
- (*(t)->_dmamap_create)((t), (s), (n), (m), (b), (f), (p))
-#define bus_dmamap_destroy(t, p) \
- (*(t)->_dmamap_destroy)((t), (p))
-#define bus_dmamap_load(t, m, b, s, p, f) \
- (*(t)->_dmamap_load)((t), (m), (b), (s), (p), (f))
-#define bus_dmamap_load_mbuf(t, m, b, f) \
- (*(t)->_dmamap_load_mbuf)((t), (m), (b), (f))
-#define bus_dmamap_load_uio(t, m, u, f) \
- (*(t)->_dmamap_load_uio)((t), (m), (u), (f))
-#define bus_dmamap_load_raw(t, m, sg, n, s, f) \
- (*(t)->_dmamap_load_raw)((t), (m), (sg), (n), (s), (f))
-#define bus_dmamap_unload(t, p) \
- (*(t)->_dmamap_unload)((t), (p))
-#define bus_dmamap_sync(t, p, o, l, ops) \
- (*(t)->_dmamap_sync)((t), (p), (o), (l), (ops))
-
-#define bus_dmamem_alloc(t, s, a, b, sg, n, r, f) \
- (*(t)->_dmamem_alloc)((t), (s), (a), (b), (sg), (n), (r), (f))
-#define bus_dmamem_free(t, sg, n) \
- (*(t)->_dmamem_free)((t), (sg), (n))
-#define bus_dmamem_map(t, sg, n, s, k, f) \
- (*(t)->_dmamem_map)((t), (sg), (n), (s), (k), (f))
-#define bus_dmamem_unmap(t, k, s) \
- (*(t)->_dmamem_unmap)((t), (k), (s))
-#define bus_dmamem_mmap(t, sg, n, o, p, f) \
- (*(t)->_dmamem_mmap)((t), (sg), (n), (o), (p), (f))
-
-#define bus_dmatag_subregion(t, mna, mxa, nt, f) EOPNOTSUPP
-#define bus_dmatag_destroy(t)
-
-#ifdef _SGIMIPS_BUS_DMA_PRIVATE
-
-int _bus_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t,
- bus_size_t, int, bus_dmamap_t *);
-void _bus_dmamap_destroy(bus_dma_tag_t, bus_dmamap_t);
-int _bus_dmamap_load(bus_dma_tag_t, bus_dmamap_t, void *,
- bus_size_t, struct proc *, int);
-int _bus_dmamap_load_mbuf(bus_dma_tag_t, bus_dmamap_t,
- struct mbuf *, int);
-int _bus_dmamap_load_uio(bus_dma_tag_t, bus_dmamap_t,
- struct uio *, int);
-int _bus_dmamap_load_raw(bus_dma_tag_t, bus_dmamap_t,
- bus_dma_segment_t *, int, bus_size_t, int);
-void _bus_dmamap_unload(bus_dma_tag_t, bus_dmamap_t);
void _bus_dmamap_sync_mips1(bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
bus_size_t, int);
-void _bus_dmamap_sync_mips3(bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
- bus_size_t, int);
-
-int _bus_dmamem_alloc(bus_dma_tag_t tag, bus_size_t size,
- bus_size_t alignment, bus_size_t boundary,
- bus_dma_segment_t *segs, int nsegs, int *rsegs, int flags);
-void _bus_dmamem_free(bus_dma_tag_t tag, bus_dma_segment_t *segs,
- int nsegs);
-int _bus_dmamem_map(bus_dma_tag_t tag, bus_dma_segment_t *segs,
- int nsegs, size_t size, void **kvap, int flags);
-void _bus_dmamem_unmap(bus_dma_tag_t tag, void *kva,
- size_t size);
-paddr_t _bus_dmamem_mmap(bus_dma_tag_t tag, bus_dma_segment_t *segs,
- int nsegs, off_t off, int prot, int flags);
-
-int _bus_dmamem_alloc_range(bus_dma_tag_t tag, bus_size_t size,
- bus_size_t alignment, bus_size_t boundary,
- bus_dma_segment_t *segs, int nsegs, int *rsegs, int flags,
- vaddr_t low, vaddr_t high);
-
-extern struct sgimips_bus_dma_tag sgimips_default_bus_dma_tag;
-#endif /* _SGIMIPS_BUS_DMA_PRIVATE */
#endif /* _SGIMIPS_BUS_FUNCS_H_ */
Index: src/sys/arch/sgimips/include/pci_machdep.h
diff -u src/sys/arch/sgimips/include/pci_machdep.h:1.13 src/sys/arch/sgimips/include/pci_machdep.h:1.14
--- src/sys/arch/sgimips/include/pci_machdep.h:1.13 Tue Apr 1 12:57:46 2014
+++ src/sys/arch/sgimips/include/pci_machdep.h Wed Feb 18 16:47:58 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: pci_machdep.h,v 1.13 2014/04/01 12:57:46 ozaki-r Exp $ */
+/* $NetBSD: pci_machdep.h,v 1.14 2015/02/18 16:47:58 macallan Exp $ */
/*
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
@@ -76,7 +76,7 @@ struct sgimips_pci_chipset {
struct extent *pc_ioext; /* PCI I/O space extent */
};
-extern struct sgimips_bus_dma_tag pci_bus_dma_tag;
+extern struct mips_bus_dma_tag pci_bus_dma_tag;
/*
* Functions provided to machine-independent PCI code.
Index: src/sys/arch/sgimips/ioc/ioc.c
diff -u src/sys/arch/sgimips/ioc/ioc.c:1.10 src/sys/arch/sgimips/ioc/ioc.c:1.11
--- src/sys/arch/sgimips/ioc/ioc.c:1.10 Sat Oct 27 17:18:10 2012
+++ src/sys/arch/sgimips/ioc/ioc.c Wed Feb 18 16:47:58 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: ioc.c,v 1.10 2012/10/27 17:18:10 chs Exp $ */
+/* $NetBSD: ioc.c,v 1.11 2015/02/18 16:47:58 macallan Exp $ */
/*
* Copyright (c) 2003 Christopher Sekiya
@@ -37,7 +37,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ioc.c,v 1.10 2012/10/27 17:18:10 chs Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ioc.c,v 1.11 2015/02/18 16:47:58 macallan Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -103,9 +103,9 @@ ioc_attach(device_t parent, device_t sel
callout_init(&ioc_blink_ch, 0);
#endif
- sc->sc_iot = SGIMIPS_BUS_SPACE_HPC;
+ sc->sc_iot = normal_memt;
- if (bus_space_map(sc->sc_iot, maa->ma_addr, 0,
+ if (bus_space_map(sc->sc_iot, maa->ma_addr, 0x100,
BUS_SPACE_MAP_LINEAR, &sc->sc_ioh))
panic("ioc_attach: could not allocate memory\n");
@@ -188,7 +188,7 @@ ioc_search(device_t parent, cfdata_t cf,
do {
iaa.iaa_offset = cf->cf_loc[IOCCF_OFFSET];
iaa.iaa_intr = cf->cf_loc[IOCCF_INTR];
- iaa.iaa_st = SGIMIPS_BUS_SPACE_HPC;
+ iaa.iaa_st = normal_memt;
iaa.iaa_sh = sc->sc_ioh; /* XXX */
tryagain = 0;
Index: src/sys/arch/sgimips/ioc/oioc.c
diff -u src/sys/arch/sgimips/ioc/oioc.c:1.3 src/sys/arch/sgimips/ioc/oioc.c:1.4
--- src/sys/arch/sgimips/ioc/oioc.c:1.3 Sat Oct 27 17:18:10 2012
+++ src/sys/arch/sgimips/ioc/oioc.c Wed Feb 18 16:47:58 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: oioc.c,v 1.3 2012/10/27 17:18:10 chs Exp $ */
+/* $NetBSD: oioc.c,v 1.4 2015/02/18 16:47:58 macallan Exp $ */
/*
* Copyright (c) 2009 Stephen M. Rumble
@@ -37,12 +37,11 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: oioc.c,v 1.3 2012/10/27 17:18:10 chs Exp $");
+__KERNEL_RCSID(0, "$NetBSD: oioc.c,v 1.4 2015/02/18 16:47:58 macallan Exp $");
#include <sys/param.h>
#include <sys/device.h>
-#define _SGIMIPS_BUS_DMA_PRIVATE
#include <machine/cpu.h>
#include <machine/locore.h>
#include <machine/autoconf.h>
@@ -99,8 +98,8 @@ oioc_attach(device_t parent, device_t se
uint32_t reg1, reg2;
int oiocrev, i;
- sc->sc_iot = SGIMIPS_BUS_SPACE_NORMAL;
- if (bus_space_map(sc->sc_iot, ma->ma_addr, 0,
+ sc->sc_iot = normal_memt;
+ if (bus_space_map(sc->sc_iot, ma->ma_addr, OIOC_SCSI_REGS_SIZE,
BUS_SPACE_MAP_LINEAR, &sc->sc_ioh))
panic("oioc_attach: could not allocate memory\n");
@@ -146,7 +145,7 @@ oioc_attach(device_t parent, device_t se
oa.oa_name = oioc_devices[i].od_name;
oa.oa_irq = oioc_devices[i].od_irq;
oa.oa_burst_dma = sc->sc_burst_dma;
- oa.oa_st = SGIMIPS_BUS_SPACE_NORMAL;
+ oa.oa_st = normal_memt;
oa.oa_sh = sc->sc_ioh;
oa.oa_dmat = &sgimips_default_bus_dma_tag;
config_found_ia(self, "oioc", &oa, oioc_print);
Index: src/sys/arch/sgimips/mace/com_mace.c
diff -u src/sys/arch/sgimips/mace/com_mace.c:1.9 src/sys/arch/sgimips/mace/com_mace.c:1.10
--- src/sys/arch/sgimips/mace/com_mace.c:1.9 Fri Jul 1 18:53:47 2011
+++ src/sys/arch/sgimips/mace/com_mace.c Wed Feb 18 16:47:59 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: com_mace.c,v 1.9 2011/07/01 18:53:47 dyoung Exp $ */
+/* $NetBSD: com_mace.c,v 1.10 2015/02/18 16:47:59 macallan Exp $ */
/*
* Copyright (c) 2000 Soren S. Jorvang
@@ -33,7 +33,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: com_mace.c,v 1.9 2011/07/01 18:53:47 dyoung Exp $");
+__KERNEL_RCSID(0, "$NetBSD: com_mace.c,v 1.10 2015/02/18 16:47:59 macallan Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -96,7 +96,7 @@ com_mace_attach(device_t parent, device_
*/
ioh = maa->maa_sh + maa->maa_offset;
/* note that ioh on mac is *also* the iobase address */
- COM_INIT_REGS(sc->sc_regs, maa->maa_st, ioh, ioh);
+ COM_INIT_REGS(sc->sc_regs, mace_isa_memt, ioh, 0);
sc->sc_frequency = COM_FREQ;
Index: src/sys/arch/sgimips/mace/mace.c
diff -u src/sys/arch/sgimips/mace/mace.c:1.20 src/sys/arch/sgimips/mace/mace.c:1.21
--- src/sys/arch/sgimips/mace/mace.c:1.20 Mon Dec 16 15:45:29 2013
+++ src/sys/arch/sgimips/mace/mace.c Wed Feb 18 16:47:59 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: mace.c,v 1.20 2013/12/16 15:45:29 mrg Exp $ */
+/* $NetBSD: mace.c,v 1.21 2015/02/18 16:47:59 macallan Exp $ */
/*
* Copyright (c) 2003 Christopher Sekiya
@@ -45,7 +45,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mace.c,v 1.20 2013/12/16 15:45:29 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mace.c,v 1.21 2015/02/18 16:47:59 macallan Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -61,7 +61,6 @@ __KERNEL_RCSID(0, "$NetBSD: mace.c,v 1.2
#include <uvm/uvm_extern.h>
-#define _SGIMIPS_BUS_DMA_PRIVATE
#include <sys/bus.h>
#include <machine/cpu.h>
#include <machine/locore.h>
@@ -107,6 +106,12 @@ static int mace_search(device_t, cfdata_
CFATTACH_DECL_NEW(mace, sizeof(struct mace_softc),
mace_match, mace_attach, NULL, NULL);
+static void mace_isa_bus_mem_init(bus_space_tag_t, void *);
+
+static struct mips_bus_space mace_isa_mbst;
+bus_space_tag_t mace_isa_memt = NULL;
+static int mace_isa_init = 0;
+
#if defined(BLINK)
static callout_t mace_blink_ch;
static void mace_blink(void *);
@@ -125,6 +130,16 @@ mace_match(device_t parent, struct cfdat
return 0;
}
+void
+mace_init_bus(void)
+{
+ if (mace_isa_init == 1)
+ return;
+ mace_isa_init = 1;
+ mace_isa_bus_mem_init(&mace_isa_mbst, NULL);
+ mace_isa_memt = &mace_isa_mbst;
+}
+
static void
mace_attach(device_t parent, device_t self, void *aux)
{
@@ -137,7 +152,7 @@ mace_attach(device_t parent, device_t se
callout_init(&mace_blink_ch, 0);
#endif
- sc->iot = SGIMIPS_BUS_SPACE_MACE;
+ sc->iot = normal_memt; /* for mace registers */
sc->dmat = &sgimips_default_bus_dma_tag;
if (bus_space_map(sc->iot, ma->ma_addr, 0,
@@ -151,6 +166,8 @@ mace_attach(device_t parent, device_t se
aprint_debug("%s: isa msk %#"PRIx64"\n", device_xname(self),
bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_INT_MASK));
+ mace_init_bus();
+
/*
* Turn on most ISA interrupts. These are actually masked and
* registered via the CRIME, as the MACE ISA interrupt mask is
@@ -212,7 +229,7 @@ mace_search(device_t parent, struct cfda
maa.maa_offset = cf->cf_loc[MACECF_OFFSET];
maa.maa_intr = cf->cf_loc[MACECF_INTR];
maa.maa_intrmask = cf->cf_loc[MACECF_INTRMASK];
- maa.maa_st = SGIMIPS_BUS_SPACE_MACE;
+ maa.maa_st = normal_memt;
maa.maa_sh = sc->ioh; /* XXX */
maa.maa_dmat = &sgimips_default_bus_dma_tag;
maa.isa_ringbuffer = sc->isa_ringbuffer;
@@ -344,3 +361,14 @@ mace_blink(void *self)
}
#endif
+
+#define CHIP mace_isa
+#define CHIP_MEM /* defined */
+#define CHIP_ALIGN_STRIDE 8
+#define CHIP_ACCESS_SIZE 8
+#define CHIP_W1_BUS_START(v) 0x00000000UL
+#define CHIP_W1_BUS_END(v) 0xffffffffUL
+#define CHIP_W1_SYS_START(v) 0x00000000UL
+#define CHIP_W1_SYS_END(v) 0xffffffffUL
+
+#include <mips/mips/bus_space_alignstride_chipdep.c>
Index: src/sys/arch/sgimips/mace/mcclock_mace.c
diff -u src/sys/arch/sgimips/mace/mcclock_mace.c:1.16 src/sys/arch/sgimips/mace/mcclock_mace.c:1.17
--- src/sys/arch/sgimips/mace/mcclock_mace.c:1.16 Thu Nov 20 16:34:26 2014
+++ src/sys/arch/sgimips/mace/mcclock_mace.c Wed Feb 18 16:47:59 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: mcclock_mace.c,v 1.16 2014/11/20 16:34:26 christos Exp $ */
+/* $NetBSD: mcclock_mace.c,v 1.17 2015/02/18 16:47:59 macallan Exp $ */
/*
* Copyright (c) 2001 Antti Kantee. All Rights Reserved.
@@ -65,7 +65,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mcclock_mace.c,v 1.16 2014/11/20 16:34:26 christos Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mcclock_mace.c,v 1.17 2015/02/18 16:47:59 macallan Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -165,7 +165,7 @@ ds1687_read(void *arg, unsigned int addr
{
struct mcclock_mace_softc *sc = arg;
- return bus_space_read_1(sc->sc_st, sc->sc_sh, addr);
+ return bus_space_read_1(sc->sc_st, sc->sc_sh, (addr << 8) + 7);
}
void
@@ -173,7 +173,7 @@ ds1687_write(void *arg, unsigned int add
{
struct mcclock_mace_softc *sc = arg;
- bus_space_write_1(sc->sc_st, sc->sc_sh, addr, data);
+ bus_space_write_1(sc->sc_st, sc->sc_sh, (addr << 8) + 7, data);
}
static int
Index: src/sys/arch/sgimips/mace/pci_mace.c
diff -u src/sys/arch/sgimips/mace/pci_mace.c:1.17 src/sys/arch/sgimips/mace/pci_mace.c:1.18
--- src/sys/arch/sgimips/mace/pci_mace.c:1.17 Sat Mar 29 19:28:30 2014
+++ src/sys/arch/sgimips/mace/pci_mace.c Wed Feb 18 16:47:59 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: pci_mace.c,v 1.17 2014/03/29 19:28:30 christos Exp $ */
+/* $NetBSD: pci_mace.c,v 1.18 2015/02/18 16:47:59 macallan Exp $ */
/*
* Copyright (c) 2001,2003 Christopher Sekiya
@@ -34,7 +34,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_mace.c,v 1.17 2014/03/29 19:28:30 christos Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_mace.c,v 1.18 2015/02/18 16:47:59 macallan Exp $");
#include "opt_pci.h"
#include "pci.h"
@@ -84,6 +84,13 @@ static int macepci_intr(void *);
CFATTACH_DECL_NEW(macepci, sizeof(struct macepci_softc),
macepci_match, macepci_attach, NULL, NULL);
+static void pcimem_bus_mem_init(bus_space_tag_t, void *);
+static void pciio_bus_mem_init(bus_space_tag_t, void *);
+static struct mips_bus_space pcimem_mbst;
+static struct mips_bus_space pciio_mbst;
+bus_space_tag_t mace_pci_memt = NULL;
+bus_space_tag_t mace_pci_iot = NULL;
+
static int
macepci_match(device_t parent, cfdata_t match, void *aux)
{
@@ -110,6 +117,11 @@ macepci_attach(device_t parent, device_t
rev = bus_space_read_4(pc->iot, pc->ioh, MACEPCI_REVISION);
printf(": rev %d\n", rev);
+ pcimem_bus_mem_init(&pcimem_mbst, NULL);
+ mace_pci_memt = &pcimem_mbst;
+ pciio_bus_mem_init(&pciio_mbst, NULL);
+ mace_pci_iot = &pciio_mbst;
+
pc->pc_bus_maxdevs = macepci_bus_maxdevs;
pc->pc_conf_read = macepci_conf_read;
pc->pc_conf_write = macepci_conf_write;
@@ -151,8 +163,8 @@ macepci_attach(device_t parent, device_t
pci_configure_bus(pc, pc->pc_ioext, pc->pc_memext, NULL, 0,
mips_cache_info.mci_dcache_align);
memset(&pba, 0, sizeof pba);
-/*XXX*/ pba.pba_iot = SGIMIPS_BUS_SPACE_IO;
-/*XXX*/ pba.pba_memt = SGIMIPS_BUS_SPACE_MEM;
+/*XXX*/ pba.pba_iot = mace_pci_iot;
+/*XXX*/ pba.pba_memt = mace_pci_memt;
pba.pba_dmat = &pci_bus_dma_tag;
pba.pba_dmat64 = NULL;
pba.pba_bus = 0;
@@ -347,3 +359,55 @@ macepci_intr(void *arg)
}
return 0;
}
+
+/*
+ * use the 32MB windows to access PCI space when running a 32bit kernel,
+ * use full views at >4GB in LP64
+ * XXX access to PCI space is endian-twiddled which can't be turned off so we
+ * need to instruct bus_space to un-twiddle them for us so 8bit and 16bit
+ * accesses look little-endian
+ */
+#define CHIP pcimem
+#define CHIP_MEM /* defined */
+#define CHIP_WRONG_ENDIAN
+
+/*
+ * the lower 2GB of PCI space are two views of system memory, with and without
+ * endianness twiddling
+ */
+#define CHIP_W1_BUS_START(v) 0x80000000UL
+#define CHIP_W1_BUS_END(v) 0xffffffffUL
+#ifdef _LP64
+#define CHIP_W1_SYS_START(v) MACE_PCI_HI_MEMORY
+#define CHIP_W1_SYS_END(v) MACE_PCI_HI_MEMORY + 0x7fffffffUL
+#else
+#define CHIP_W1_SYS_START(v) MACE_PCI_LOW_MEMORY
+#define CHIP_W1_SYS_END(v) MACE_PCI_LOW_MEMORY + 0x01ffffffUL
+#endif
+
+#include <mips/mips/bus_space_alignstride_chipdep.c>
+
+#undef CHIP
+#undef CHIP_W1_BUS_START
+#undef CHIP_W1_BUS_END
+#undef CHIP_W1_SYS_START
+#undef CHIP_W1_SYS_END
+
+#define CHIP pciio
+/*
+ * Even though it's PCI IO space, it's memory mapped so there is no reason not
+ * to allow linear mappings or mmapings into userland. In fact we may need to
+ * do just that in order to use things like PCI graphics cards in X.
+ */
+#define CHIP_MEM /* defined */
+#define CHIP_W1_BUS_START(v) 0x00000000UL
+#define CHIP_W1_BUS_END(v) 0xffffffffUL
+#ifdef _LP64
+#define CHIP_W1_SYS_START(v) MACE_PCI_HI_IO
+#define CHIP_W1_SYS_END(v) MACE_PCI_HI_IO + 0xffffffffUL
+#else
+#define CHIP_W1_SYS_START(v) MACE_PCI_LOW_IO
+#define CHIP_W1_SYS_END(v) MACE_PCI_LOW_IO + 0x01ffffffUL
+#endif
+
+#include <mips/mips/bus_space_alignstride_chipdep.c>
Index: src/sys/arch/sgimips/mace/pcireg_mace.h
diff -u src/sys/arch/sgimips/mace/pcireg_mace.h:1.2 src/sys/arch/sgimips/mace/pcireg_mace.h:1.3
--- src/sys/arch/sgimips/mace/pcireg_mace.h:1.2 Sun Dec 11 12:18:54 2005
+++ src/sys/arch/sgimips/mace/pcireg_mace.h Wed Feb 18 16:47:59 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: pcireg_mace.h,v 1.2 2005/12/11 12:18:54 christos Exp $ */
+/* $NetBSD: pcireg_mace.h,v 1.3 2015/02/18 16:47:59 macallan Exp $ */
/*
* Copyright (c) 2000 Soren S. Jorvang
@@ -83,6 +83,7 @@
#define CONTROL_INT5_INVAL_BUFS 0x00200000
#define CONTROL_INT6_INVAL_BUFS 0x00400000
#define CONTROL_INT7_INVAL_BUFS 0x00800000
+#define CONTROL_INT_INVAL_MASK 0x00ff0000
#define CONTROL_OVERRUN_COND_I 0x01000000
#define CONTROL_PARITY_ERROR_I 0x02000000
#define CONTROL_SYSTEM_ERROR_I 0x04000000
Index: src/sys/arch/sgimips/pci/pci_machdep.c
diff -u src/sys/arch/sgimips/pci/pci_machdep.c:1.24 src/sys/arch/sgimips/pci/pci_machdep.c:1.25
--- src/sys/arch/sgimips/pci/pci_machdep.c:1.24 Sat Mar 29 19:28:30 2014
+++ src/sys/arch/sgimips/pci/pci_machdep.c Wed Feb 18 16:47:59 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: pci_machdep.c,v 1.24 2014/03/29 19:28:30 christos Exp $ */
+/* $NetBSD: pci_machdep.c,v 1.25 2015/02/18 16:47:59 macallan Exp $ */
/*
* Copyright (c) 2000 Soren S. Jorvang
@@ -33,7 +33,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.24 2014/03/29 19:28:30 christos Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.25 2015/02/18 16:47:59 macallan Exp $");
#include "opt_pci.h"
#include "pci.h"
@@ -47,7 +47,6 @@ __KERNEL_RCSID(0, "$NetBSD: pci_machdep.
#include <uvm/uvm_extern.h>
-#define _SGIMIPS_BUS_DMA_PRIVATE
#include <sys/bus.h>
#include <machine/intr.h>
#include <machine/sysconf.h>
@@ -57,7 +56,7 @@ __KERNEL_RCSID(0, "$NetBSD: pci_machdep.
#include <dev/pci/pcidevs.h>
#include <dev/pci/pciconf.h>
-struct sgimips_bus_dma_tag pci_bus_dma_tag;
+struct mips_bus_dma_tag pci_bus_dma_tag;
void
pci_attach_hook(device_t parent, device_t self, struct pcibus_attach_args *pba)
Index: src/sys/arch/sgimips/sgimips/bus.c
diff -u src/sys/arch/sgimips/sgimips/bus.c:1.65 src/sys/arch/sgimips/sgimips/bus.c:1.66
--- src/sys/arch/sgimips/sgimips/bus.c:1.65 Tue Oct 2 23:54:54 2012
+++ src/sys/arch/sgimips/sgimips/bus.c Wed Feb 18 16:47:59 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: bus.c,v 1.65 2012/10/02 23:54:54 christos Exp $ */
+/* $NetBSD: bus.c,v 1.66 2015/02/18 16:47:59 macallan Exp $ */
/*
* Copyright (c) 1998 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: bus.c,v 1.65 2012/10/02 23:54:54 christos Exp $");
+__KERNEL_RCSID(0, "$NetBSD: bus.c,v 1.66 2015/02/18 16:47:59 macallan Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -43,13 +43,12 @@ __KERNEL_RCSID(0, "$NetBSD: bus.c,v 1.65
#include <sys/proc.h>
#include <sys/mbuf.h>
-#define _SGIMIPS_BUS_DMA_PRIVATE
+#define _MIPS_BUS_DMA_PRIVATE
+
#include <sys/bus.h>
#include <machine/cpu.h>
#include <machine/machtype.h>
-#include <dev/bus_dma/bus_dmamem_common.h>
-
#include <uvm/uvm_extern.h>
#include <mips/cpuregs.h>
@@ -60,51 +59,53 @@ __KERNEL_RCSID(0, "$NetBSD: bus.c,v 1.65
#include "opt_sgimace.h"
-static int _bus_dmamap_load_buffer(bus_dmamap_t, void *, bus_size_t,
- struct vmspace *, int, vaddr_t *, int *, int);
-
-struct sgimips_bus_dma_tag sgimips_default_bus_dma_tag = {
- _bus_dmamap_create,
- _bus_dmamap_destroy,
- _bus_dmamap_load,
- _bus_dmamap_load_mbuf,
- _bus_dmamap_load_uio,
- _bus_dmamap_load_raw,
- _bus_dmamap_unload,
- NULL,
- _bus_dmamem_alloc,
- _bus_dmamem_free,
- _bus_dmamem_map,
- _bus_dmamem_unmap,
- _bus_dmamem_mmap,
+struct mips_bus_dma_tag sgimips_default_bus_dma_tag = {
+ ._dmamap_ops = _BUS_DMAMAP_OPS_INITIALIZER,
+ ._dmamem_ops = _BUS_DMAMEM_OPS_INITIALIZER,
+ ._dmatag_ops = _BUS_DMATAG_OPS_INITIALIZER,
};
+static void normal_bus_mem_init(bus_space_tag_t, void *);
+
+static struct mips_bus_space normal_mbst;
+bus_space_tag_t normal_memt = NULL;
+
+/*
+ * XXX
+ * I'm not sure how well the common MIPS bus_dma.c handles MIPS-I and I don't
+ * have any IP1x hardware, so I'll leave this in just in case it needs to be
+ * put back
+ */
+
void
sgimips_bus_dma_init(void)
{
+ printf("%s\n", __func__);
+ normal_bus_mem_init(&normal_mbst, NULL);
+ normal_memt = &normal_mbst;
+
+#if 0
switch (mach_type) {
/* R2000/R3000 */
case MACH_SGI_IP6 | MACH_SGI_IP10:
case MACH_SGI_IP12:
- sgimips_default_bus_dma_tag._dmamap_sync =
+ sgimips_default_bus_dma_tag._dmamap_ops.dmamap_sync =
_bus_dmamap_sync_mips1;
break;
- /* >=R4000*/
- case MACH_SGI_IP20:
- case MACH_SGI_IP22:
- case MACH_SGI_IP30:
- case MACH_SGI_IP32:
- sgimips_default_bus_dma_tag._dmamap_sync =
- _bus_dmamap_sync_mips3;
- break;
-
default:
panic("sgimips_bus_dma_init: unsupported mach type IP%d\n",
mach_type);
}
+#endif
}
+/*
+ * XXX
+ * left in for illustrative purposes
+ */
+
+#if 0
u_int8_t
bus_space_read_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o)
{
@@ -126,698 +127,8 @@ bus_space_read_1(bus_space_tag_t t, bus_
panic("no bus tag");
}
}
-
-void
-bus_space_write_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o, u_int8_t v)
-{
- switch (t) {
- case SGIMIPS_BUS_SPACE_NORMAL:
- *(volatile u_int8_t *)(vaddr_t)(h + o) = v;
- break;
- case SGIMIPS_BUS_SPACE_IP6_DPCLOCK:
- *(volatile u_int8_t *)(vaddr_t)(h + (o << 2)) = v;
- break;
- case SGIMIPS_BUS_SPACE_HPC:
- *(volatile u_int8_t *)(vaddr_t)(h + (o << 2) + 3) = v;
- break;
- case SGIMIPS_BUS_SPACE_MEM:
- case SGIMIPS_BUS_SPACE_IO:
- *(volatile u_int8_t *)(vaddr_t)(h + (o | 3) - (o & 3)) = v;
- break;
- case SGIMIPS_BUS_SPACE_MACE:
- *(volatile u_int8_t *)(vaddr_t)(h + (o << 8) + 7) = v;
- break;
- default:
- panic("no bus tag");
- }
-
- wbflush(); /* XXX */
-}
-
-u_int16_t
-bus_space_read_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o)
-{
- wbflush(); /* XXX ? */
-
- switch (t) {
- case SGIMIPS_BUS_SPACE_NORMAL:
- return *(volatile u_int16_t *)(vaddr_t)(h + o);
- case SGIMIPS_BUS_SPACE_HPC:
- return *(volatile u_int16_t *)(vaddr_t)(h + (o << 2) + 1);
- case SGIMIPS_BUS_SPACE_MEM:
- case SGIMIPS_BUS_SPACE_IO:
- return *(volatile u_int16_t *)(vaddr_t)(h + (o | 2) - (o & 3));
- default:
- panic("no bus tag");
- }
-}
-
-void
-bus_space_write_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o, u_int16_t v)
-{
- switch (t) {
- case SGIMIPS_BUS_SPACE_NORMAL:
- *(volatile u_int16_t *)(vaddr_t)(h + o) = v;
- break;
- case SGIMIPS_BUS_SPACE_HPC:
- *(volatile u_int16_t *)(vaddr_t)(h + (o << 2) + 1) = v;
- break;
- case SGIMIPS_BUS_SPACE_MEM:
- case SGIMIPS_BUS_SPACE_IO:
- *(volatile u_int16_t *)(vaddr_t)(h + (o | 2) - (o & 3)) = v;
- break;
- default:
- panic("no bus tag");
- }
-
- wbflush(); /* XXX */
-}
-
-u_int32_t
-bus_space_read_4(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t o)
-{
- u_int32_t reg;
-#ifdef MACE_NEEDS_DELAYS
- int s;
-#endif
-
- switch (tag) {
- case SGIMIPS_BUS_SPACE_MACE:
-#ifdef MACE_NEEDS_DELAYS
- s = splhigh();
- delay(10);
-#endif
- wbflush();
- reg = (*(volatile u_int32_t *)(vaddr_t)(bsh + o));
-#ifdef MACE_NEEDS_DELAYS
- delay(10);
- splx(s);
-#endif
- break;
- default:
- wbflush();
- reg = (*(volatile u_int32_t *)(vaddr_t)(bsh + o));
- break;
- }
- return reg;
-}
-
-
-void
-bus_space_write_4(bus_space_tag_t tag, bus_space_handle_t bsh,
- bus_size_t o, u_int32_t v)
-{
-#ifdef MACE_NEEDS_DELAYS
- int s;
-#endif
-
- switch (tag) {
- case SGIMIPS_BUS_SPACE_MACE:
-#ifdef MACE_NEEDS_DELAYS
- s = splhigh();
- delay(10);
-#endif
- *(volatile u_int32_t *)(vaddr_t)((bsh) + (o)) = (v);
- wbflush();
-#ifdef MACE_NEEDS_DELAYS
- delay(10);
- splx(s);
-#endif
- break;
- default:
- *(volatile u_int32_t *)(vaddr_t)((bsh) + (o)) = (v);
- wbflush(); /* XXX */
- break;
- }
-}
-
-u_int16_t
-bus_space_read_stream_2(bus_space_tag_t t, bus_space_handle_t h,
- bus_size_t o)
-{
- u_int16_t v;
- wbflush(); /* XXX ? */
-
- switch (t) {
- case SGIMIPS_BUS_SPACE_NORMAL:
- return *(volatile u_int16_t *)(vaddr_t)(h + o);
- case SGIMIPS_BUS_SPACE_HPC:
- return *(volatile u_int16_t *)(vaddr_t)(h + (o << 2) + 1);
- case SGIMIPS_BUS_SPACE_MEM:
- case SGIMIPS_BUS_SPACE_IO:
- v = *(volatile u_int16_t *)(vaddr_t)(h + (o | 2) - (o & 3));
- return htole16(v);
- default:
- panic("no bus tag");
- }
-}
-
-u_int32_t
-bus_space_read_stream_4(bus_space_tag_t t, bus_space_handle_t bsh,
- bus_size_t o)
-{
- u_int32_t reg;
-#ifdef MACE_NEEDS_DELAYS
- int s;
-#endif
-
- switch (t) {
- case SGIMIPS_BUS_SPACE_MACE:
-#ifdef MACE_NEEDS_DELAYS
- s = splhigh();
- delay(10);
-#endif
- wbflush();
- reg = (*(volatile u_int32_t *)(vaddr_t)(bsh + o));
-#ifdef MACE_NEEDS_DELAYS
- delay(10);
- splx(s);
-#endif
- break;
- case SGIMIPS_BUS_SPACE_MEM:
- case SGIMIPS_BUS_SPACE_IO:
- wbflush();
- reg = (*(volatile u_int32_t *)(vaddr_t)(bsh + o));
- reg = htole32(reg);
- break;
- default:
- wbflush();
- reg = (*(volatile u_int32_t *)(vaddr_t)(bsh + o));
- break;
- }
- return reg;
-}
-
-void
-bus_space_write_stream_2(bus_space_tag_t t, bus_space_handle_t h,
- bus_size_t o, u_int16_t v)
-{
- switch (t) {
- case SGIMIPS_BUS_SPACE_NORMAL:
- *(volatile u_int16_t *)(vaddr_t)(h + o) = v;
- break;
- case SGIMIPS_BUS_SPACE_HPC:
- *(volatile u_int16_t *)(vaddr_t)(h + (o << 2) + 1) = v;
- break;
- case SGIMIPS_BUS_SPACE_MEM:
- case SGIMIPS_BUS_SPACE_IO:
- v = le16toh(v);
- *(volatile u_int16_t *)(vaddr_t)(h + (o | 2) - (o & 3)) = v;
- break;
- default:
- panic("no bus tag");
- }
-
- wbflush(); /* XXX */
-}
-
-void
-bus_space_write_stream_4(bus_space_tag_t tag, bus_space_handle_t bsh,
- bus_size_t o, u_int32_t v)
-{
-#ifdef MACE_NEEDS_DELAYS
- int s;
-#endif
-
- switch (tag) {
- case SGIMIPS_BUS_SPACE_MACE:
-#ifdef MACE_NEEDS_DELAYS
- s = splhigh();
- delay(10);
-#endif
- *(volatile u_int32_t *)(vaddr_t)((bsh) + (o)) = (v);
- wbflush();
-#ifdef MACE_NEEDS_DELAYS
- delay(10);
- splx(s);
-#endif
- break;
- case SGIMIPS_BUS_SPACE_IO:
- case SGIMIPS_BUS_SPACE_MEM:
- v = le32toh(v);
- *(volatile u_int32_t *)(vaddr_t)((bsh) + (o)) = (v);
- wbflush(); /* XXX */
- break;
- default:
- *(volatile u_int32_t *)(vaddr_t)((bsh) + (o)) = (v);
- wbflush(); /* XXX */
- break;
- }
-}
-
-#if defined(MIPS3)
-u_int64_t
-bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t o)
-{
- u_int64_t reg;
-#ifdef MACE_NEEDS_DELAYS
- int s;
-#endif
-
- /* see if we're properly aligned */
- KASSERT((o & 7) == 0);
-
- switch (tag) {
- case SGIMIPS_BUS_SPACE_MACE:
-#ifdef MACE_NEEDS_DELAYS
- s = splhigh();
- delay(10);
-#endif
- reg = mips3_ld((volatile uint64_t *)(vaddr_t)(bsh + o));
-#ifdef MACE_NEEDS_DELAYS
- delay(10);
- splx(s);
-#endif
- break;
- default:
- reg = mips3_ld((volatile uint64_t *)(vaddr_t)(bsh + o));
- break;
- }
- return reg;
-}
-
-void
-bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t o, u_int64_t v)
-{
-#ifdef MACE_NEEDS_DELAYS
- int s;
-#endif
-
- /* see if we're properly aligned */
- KASSERT((o & 7) == 0);
-
- switch (tag) {
- case SGIMIPS_BUS_SPACE_MACE:
-#ifdef MACE_NEEDS_DELAYS
- s = splhigh();
- delay(10);
-#endif
- mips3_sd((volatile uint64_t *)(vaddr_t)(bsh + o), v);
-#ifdef MACE_NEEDS_DELAYS
- delay(10);
- splx(s);
-#endif
- break;
- default:
- mips3_sd((volatile uint64_t *)(vaddr_t)(bsh + o), v);
- break;
- }
-}
-#endif /* MIPS3 */
-
-int
-bus_space_map(bus_space_tag_t t, bus_addr_t bpa, bus_size_t size,
- int flags, bus_space_handle_t *bshp)
-{
- int cacheable = flags & BUS_SPACE_MAP_CACHEABLE;
-
- if (cacheable)
- *bshp = MIPS_PHYS_TO_KSEG0(bpa);
- else
- *bshp = MIPS_PHYS_TO_KSEG1(bpa);
-
-/*
- * XXX
- */
- /* XXX O2 */
- if (bpa > 0x80000000 && bpa < 0x82000000)
- *bshp = MIPS_PHYS_TO_KSEG1(MACE_PCI_LOW_MEMORY +
- (bpa & 0xfffffff));
- if (bpa < 0x00010000)
- *bshp = MIPS_PHYS_TO_KSEG1(MACE_PCI_LOW_IO + bpa);
-
- return 0;
-}
-
-int
-bus_space_alloc(bus_space_tag_t t, bus_addr_t rstart, bus_addr_t rend,
- bus_size_t size, bus_size_t alignment, bus_size_t boundary,
- int flags, bus_addr_t *bpap, bus_space_handle_t *bshp)
-{
- panic("bus_space_alloc: not implemented");
-}
-
-void
-bus_space_free(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t size)
-{
- panic("bus_space_free: not implemented");
-}
-
-void
-bus_space_unmap(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t size)
-{
- return;
-}
-
-int
-bus_space_subregion(bus_space_tag_t t, bus_space_handle_t bsh,
- bus_size_t offset, bus_size_t size,
- bus_space_handle_t *nbshp)
-{
-
- *nbshp = bsh + offset;
- return 0;
-}
-
-void *
-bus_space_vaddr(bus_space_tag_t t, bus_space_handle_t bsh)
-{
- switch(t) {
- case SGIMIPS_BUS_SPACE_NORMAL:
- return ((void *)bsh);
-
- case SGIMIPS_BUS_SPACE_HPC:
- panic("bus_space_vaddr not supported on HPC space!");
-
- case SGIMIPS_BUS_SPACE_MEM:
- return ((void *)bsh);
-
- case SGIMIPS_BUS_SPACE_IO:
- panic("bus_space_vaddr not supported on I/O space!");
-
- default:
- panic("no bus tag");
- }
-}
-
-/*
- * Common function for DMA map creation. May be called by bus-specific
- * DMA map creation functions.
- */
-int
-_bus_dmamap_create(bus_dma_tag_t t, bus_size_t size, int nsegments,
- bus_size_t maxsegsz, bus_size_t boundary, int flags,
- bus_dmamap_t *dmamp)
-{
- struct sgimips_bus_dmamap *map;
- void *mapstore;
- size_t mapsize;
-
- /*
- * Allocate and initialize the DMA map. The end of the map
- * is a variable-sized array of segments, so we allocate enough
- * room for them in one shot.
- *
- * Note we don't preserve the WAITOK or NOWAIT flags. Preservation
- * of ALLOCNOW notifies others that we've reserved these resources,
- * and they are not to be freed.
- *
- * The bus_dmamap_t includes one bus_dma_segment_t, hence
- * the (nsegments - 1).
- */
- mapsize = sizeof(struct sgimips_bus_dmamap) +
- (sizeof(bus_dma_segment_t) * (nsegments - 1));
- if ((mapstore = malloc(mapsize, M_DMAMAP,
- (flags & BUS_DMA_NOWAIT) ? M_NOWAIT : M_WAITOK)) == NULL)
- return ENOMEM;
-
- memset(mapstore, 0, mapsize);
- map = (struct sgimips_bus_dmamap *)mapstore;
- map->_dm_size = size;
- map->_dm_segcnt = nsegments;
- map->_dm_maxmaxsegsz = maxsegsz;
- map->_dm_boundary = boundary;
- map->_dm_flags = flags & ~(BUS_DMA_WAITOK|BUS_DMA_NOWAIT);
- map->_dm_vmspace = NULL;
- map->dm_maxsegsz = maxsegsz;
- map->dm_mapsize = 0; /* no valid mappings */
- map->dm_nsegs = 0;
-
- *dmamp = map;
- return 0;
-}
-
-/*
- * Common function for DMA map destruction. May be called by bus-specific
- * DMA map destruction functions.
- */
-void
-_bus_dmamap_destroy(bus_dma_tag_t t, bus_dmamap_t map)
-{
-
- free(map, M_DMAMAP);
-}
-extern paddr_t kvtophys(vaddr_t); /* XXX */
-
-/*
- * Utility function to load a linear buffer. lastaddrp holds state
- * between invocations (for multiple-buffer loads). segp contains
- * the starting segment on entrance, and the ending segment on exit.
- * first indicates if this is the first invocation of this function.
- */
-int
-_bus_dmamap_load_buffer(bus_dmamap_t map, void *buf, bus_size_t buflen,
- struct vmspace *vm, int flags, vaddr_t *lastaddrp,
- int *segp, int first)
-{
- bus_size_t sgsize;
- bus_addr_t lastaddr, baddr, bmask;
- paddr_t curaddr;
- vaddr_t vaddr = (vaddr_t)buf;
- int seg;
-
- lastaddr = *lastaddrp;
- bmask = ~(map->_dm_boundary - 1);
-
- for (seg = *segp; buflen > 0 ; ) {
- /*
- * Get the physical address for this segment.
- */
- if (!VMSPACE_IS_KERNEL_P(vm))
- (void) pmap_extract(vm_map_pmap(&vm->vm_map),
- vaddr, &curaddr);
- else
- curaddr = kvtophys(vaddr);
-
- /*
- * Compute the segment size, and adjust counts.
- */
- sgsize = PAGE_SIZE - ((u_long)vaddr & PGOFSET);
- if (buflen < sgsize)
- sgsize = buflen;
-
- /*
- * Make sure we don't cross any boundaries.
- */
- if (map->_dm_boundary > 0) {
- baddr = (curaddr + map->_dm_boundary) & bmask;
- if (sgsize > (baddr - curaddr))
- sgsize = (baddr - curaddr);
- }
-
- /*
- * Insert chunk into a segment, coalescing with
- * the previous segment if possible.
- */
- if (first) {
- map->dm_segs[seg].ds_addr = curaddr;
- map->dm_segs[seg].ds_len = sgsize;
- map->dm_segs[seg]._ds_vaddr = vaddr;
- first = 0;
- } else {
- if (curaddr == lastaddr &&
- (map->dm_segs[seg].ds_len + sgsize) <=
- map->dm_maxsegsz &&
- (map->_dm_boundary == 0 ||
- (map->dm_segs[seg].ds_addr & bmask) ==
- (curaddr & bmask)))
- map->dm_segs[seg].ds_len += sgsize;
- else {
- if (++seg >= map->_dm_segcnt)
- break;
- map->dm_segs[seg].ds_addr = curaddr;
- map->dm_segs[seg].ds_len = sgsize;
- map->dm_segs[seg]._ds_vaddr = vaddr;
- }
- }
-
- lastaddr = curaddr + sgsize;
- vaddr += sgsize;
- buflen -= sgsize;
- }
-
- *segp = seg;
- *lastaddrp = lastaddr;
-
- /*
- * Did we fit?
- */
- if (buflen != 0)
- return EFBIG; /* XXX Better return value here? */
-
- return 0;
-}
-
-/*
- * Common function for loading a direct-mapped DMA map with a linear
- * buffer.
- */
-int
-_bus_dmamap_load(bus_dma_tag_t t, bus_dmamap_t map, void *buf,
- bus_size_t buflen, struct proc *p, int flags)
-{
- vaddr_t lastaddr;
- int seg, error;
- struct vmspace *vm;
-
- /*
- * Make sure that on error condition we return "no valid mappings".
- */
- map->dm_mapsize = 0;
- map->dm_nsegs = 0;
- KASSERT(map->dm_maxsegsz <= map->_dm_maxmaxsegsz);
-
- if (buflen > map->_dm_size)
- return EINVAL;
-
- if (p != NULL) {
- vm = p->p_vmspace;
- } else {
- vm = vmspace_kernel();
- }
-
- seg = 0;
- error = _bus_dmamap_load_buffer(map, buf, buflen,
- vm, flags, &lastaddr, &seg, 1);
- if (error == 0) {
- map->dm_mapsize = buflen;
- map->dm_nsegs = seg + 1;
- map->_dm_vmspace = vm;
-
- /*
- * For linear buffers, we support marking the mapping
- * as COHERENT.
- *
- * XXX Check TLB entries for cache-inhibit bits?
- */
- if (buf >= (void *)MIPS_KSEG1_START &&
- buf < (void *)MIPS_KSEG2_START)
- map->_dm_flags |= SGIMIPS_DMAMAP_COHERENT;
- }
- return error;
-}
-
-/*
- * Like _bus_dmamap_load(), but for mbufs.
- */
-int
-_bus_dmamap_load_mbuf(bus_dma_tag_t t, bus_dmamap_t map, struct mbuf *m0,
- int flags)
-{
- vaddr_t lastaddr;
- int seg, error, first;
- struct mbuf *m;
-
- /*
- * Make sure that on error condition we return "no valid mappings."
- */
- map->dm_mapsize = 0;
- map->dm_nsegs = 0;
- KASSERT(map->dm_maxsegsz <= map->_dm_maxmaxsegsz);
-
-#ifdef DIAGNOSTIC
- if ((m0->m_flags & M_PKTHDR) == 0)
- panic("_bus_dmamap_load_mbuf: no packet header");
#endif
- if (m0->m_pkthdr.len > map->_dm_size)
- return EINVAL;
-
- first = 1;
- seg = 0;
- error = 0;
- for (m = m0; m != NULL && error == 0; m = m->m_next) {
- if (m->m_len == 0)
- continue;
- error = _bus_dmamap_load_buffer(map, m->m_data, m->m_len,
- vmspace_kernel(), flags, &lastaddr, &seg, first);
- first = 0;
- }
- if (error == 0) {
- map->dm_mapsize = m0->m_pkthdr.len;
- map->dm_nsegs = seg + 1;
- map->_dm_vmspace = vmspace_kernel(); /* always kernel */
- }
- return error;
-}
-
-/*
- * Like _bus_dmamap_load(), but for uios.
- */
-int
-_bus_dmamap_load_uio(bus_dma_tag_t t, bus_dmamap_t map, struct uio *uio,
- int flags)
-{
- vaddr_t lastaddr;
- int seg, i, error, first;
- bus_size_t minlen, resid;
- struct iovec *iov;
- void *addr;
-
- /*
- * Make sure that on error condition we return "no valid mappings."
- */
- map->dm_mapsize = 0;
- map->dm_nsegs = 0;
- KASSERT(map->dm_maxsegsz <= map->_dm_maxmaxsegsz);
-
- resid = uio->uio_resid;
- iov = uio->uio_iov;
-
- first = 1;
- seg = 0;
- error = 0;
- for (i = 0; i < uio->uio_iovcnt && resid != 0 && error == 0; i++) {
- /*
- * Now at the first iovec to load. Load each iovec
- * until we have exhausted the residual count.
- */
- minlen = resid < iov[i].iov_len ? resid : iov[i].iov_len;
- addr = (void *)iov[i].iov_base;
-
- error = _bus_dmamap_load_buffer(map, addr, minlen,
- uio->uio_vmspace, flags, &lastaddr, &seg, first);
- first = 0;
-
- resid -= minlen;
- }
- if (error == 0) {
- map->dm_mapsize = uio->uio_resid;
- map->dm_nsegs = seg + 1;
- map->_dm_vmspace = uio->uio_vmspace;
- }
- return error;
-}
-
-/*
- * Like _bus_dmamap_load(), but for raw memory.
- */
-int
-_bus_dmamap_load_raw(bus_dma_tag_t t, bus_dmamap_t map, bus_dma_segment_t *segs,
- int nsegs, bus_size_t size, int flags)
-{
-
- panic("_bus_dmamap_load_raw: not implemented");
-}
-
-/*
- * Common function for unloading a DMA map. May be called by
- * chipset-specific DMA map unload functions.
- */
-void
-_bus_dmamap_unload(bus_dma_tag_t t, bus_dmamap_t map)
-{
-
- /*
- * No resources to free; just mark the mappings as
- * invalid.
- */
- map->dm_maxsegsz = map->_dm_maxmaxsegsz;
- map->dm_mapsize = 0;
- map->dm_nsegs = 0;
- map->_dm_flags &= ~SGIMIPS_DMAMAP_COHERENT;
-}
-
/* Common function from DMA map synchronization. May be called
* by chipset-specific DMA map synchronization functions.
*
@@ -920,285 +231,7 @@ _bus_dmamap_sync_mips1(bus_dma_tag_t t,
}
}
-/*
- * Common function for DMA map synchronization. May be called
- * by chipset-specific DMA map synchronization functions.
- *
- * This is the R4x00/R5k version.
- */
-void
-_bus_dmamap_sync_mips3(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset,
- bus_size_t len, int ops)
-{
- bus_size_t minlen;
- vaddr_t vaddr, start, end, preboundary, firstboundary, lastboundary;
- int i, useindex;
-
- /*
- * Mixing PRE and POST operations is not allowed.
- */
- if ((ops & (BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE)) != 0 &&
- (ops & (BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE)) != 0)
- panic("_bus_dmamap_sync_mips3: mix PRE and POST");
-
-#ifdef DIAGNOSTIC
- if (offset >= map->dm_mapsize)
- panic("_bus_dmamap_sync_mips3: bad offset %"PRIxPSIZE
- "(map size is %"PRIxPSIZE")", offset, map->dm_mapsize);
- if (len == 0 || (offset + len) > map->dm_mapsize)
- panic("_bus_dmamap_sync_mips3: bad length");
-#endif
-
- /*
- * Since we're dealing with a virtually-indexed, write-back
- * cache, we need to do the following things:
- *
- * PREREAD -- Invalidate D-cache. Note we might have
- * to also write-back here if we have to use an Index
- * op, or if the buffer start/end is not cache-line aligned.
- *
- * PREWRITE -- Write-back the D-cache. If we have to use
- * an Index op, we also have to invalidate. Note that if
- * we are doing PREREAD|PREWRITE, we can collapse everything
- * into a single op.
- *
- * POSTREAD -- Nothing.
- *
- * POSTWRITE -- Nothing.
- */
-
- /*
- * Flush the write buffer.
- * XXX Is this always necessary?
- */
- wbflush();
-
- /*
- * No cache flushes are necessary if we're only doing
- * POSTREAD or POSTWRITE (i.e. not doing PREREAD or PREWRITE).
- */
- ops &= (BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
- if (ops == 0)
- return;
-
- /*
- * If the mapping is of COHERENT DMA-safe memory, no cache
- * flush is necessary.
- */
- if (map->_dm_flags & SGIMIPS_DMAMAP_COHERENT)
- return;
-
- /*
- * If the mapping belongs to the kernel, or it belongs
- * to the currently-running process (XXX actually, vmspace),
- * then we can use Hit ops. Otherwise, Index ops.
- *
- * This should be true the vast majority of the time.
- */
- if (__predict_true(VMSPACE_IS_KERNEL_P(map->_dm_vmspace) ||
- map->_dm_vmspace == curproc->p_vmspace))
- useindex = 0;
- else
- useindex = 1;
-
- for (i = 0; i < map->dm_nsegs && len != 0; i++) {
- /* Find the beginning segment. */
- if (offset >= map->dm_segs[i].ds_len) {
- offset -= map->dm_segs[i].ds_len;
- continue;
- }
-
- /*
- * Now at the first segment to sync; nail
- * each segment until we have exhausted the
- * length.
- */
- minlen = len < map->dm_segs[i].ds_len - offset ?
- len : map->dm_segs[i].ds_len - offset;
-
- vaddr = map->dm_segs[i]._ds_vaddr;
-
-#ifdef BUS_DMA_DEBUG
- printf("bus_dmamap_sync_mips3: flushing segment %d "
- "(0x%lx+%lx, 0x%lx+0x%lx) (olen = %ld)...", i,
- vaddr, offset, vaddr, offset + minlen - 1, len);
-#endif
-
- /*
- * If we are forced to use Index ops, it's always a
- * Write-back,Invalidate, so just do one test.
- */
- if (__predict_false(useindex)) {
- mips_dcache_wbinv_range_index(vaddr + offset, minlen);
-#ifdef BUS_DMA_DEBUG
- printf("\n");
-#endif
- offset = 0;
- len -= minlen;
- continue;
- }
-
- /* The code that follows is more correct than that in
- mips/bus_dma.c. */
- start = vaddr + offset;
- switch (ops) {
- case BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE:
- mips_dcache_wbinv_range(start, minlen);
- break;
-
- case BUS_DMASYNC_PREREAD: {
- struct mips_cache_info * const mci = &mips_cache_info;
- end = start + minlen;
- preboundary = start & ~mci->mci_dcache_align_mask;
- firstboundary = (start + mci->mci_dcache_align_mask)
- & ~mci->mci_dcache_align_mask;
- lastboundary = end & ~mci->mci_dcache_align_mask;
- if (preboundary < start && preboundary < lastboundary)
- mips_dcache_wbinv_range(preboundary,
- mci->mci_dcache_align);
- if (firstboundary < lastboundary)
- mips_dcache_inv_range(firstboundary,
- lastboundary - firstboundary);
- if (lastboundary < end)
- mips_dcache_wbinv_range(lastboundary,
- mci->mci_dcache_align);
- break;
- }
-
- case BUS_DMASYNC_PREWRITE:
- mips_dcache_wb_range(start, minlen);
- break;
- }
-#ifdef BUS_DMA_DEBUG
- printf("\n");
-#endif
- offset = 0;
- len -= minlen;
- }
-}
-
-/*
- * Common function for DMA-safe memory allocation. May be called
- * by bus-specific DMA memory allocation functions.
- */
-int
-_bus_dmamem_alloc(bus_dma_tag_t t, bus_size_t size, bus_size_t alignment,
- bus_size_t boundary, bus_dma_segment_t *segs,
- int nsegs, int *rsegs, int flags)
-{
- return (_bus_dmamem_alloc_range_common(t, size, alignment, boundary,
- segs, nsegs, rsegs, flags,
- mips_avail_start /*low*/, mips_avail_end - PAGE_SIZE /*high*/));
-}
-
-/*
- * Common function for freeing DMA-safe memory. May be called by
- * bus-specific DMA memory free functions.
- */
-void
-_bus_dmamem_free(bus_dma_tag_t t, bus_dma_segment_t *segs, int nsegs)
-{
-
- _bus_dmamem_free_common(t, segs, nsegs);
-}
-
-/*
- * Common function for mapping DMA-safe memory. May be called by
- * bus-specific DMA memory map functions.
- */
-int
-_bus_dmamem_map(bus_dma_tag_t t, bus_dma_segment_t *segs, int nsegs,
- size_t size, void **kvap, int flags)
-{
- vaddr_t va;
- bus_addr_t addr;
- int curseg;
- const uvm_flag_t kmflags =
- (flags & BUS_DMA_NOWAIT) != 0 ? UVM_KMF_NOWAIT : 0;
- u_int pmapflags;
-
- /*
- * If we're only mapping 1 segment, use KSEG0 or KSEG1, to avoid
- * TLB thrashing.
- */
-
- if (nsegs == 1) {
- if (flags & BUS_DMA_COHERENT)
- *kvap = (void *)MIPS_PHYS_TO_KSEG1(segs[0].ds_addr);
- else
- *kvap = (void *)MIPS_PHYS_TO_KSEG0(segs[0].ds_addr);
- return 0;
- }
-
- size = round_page(size);
-
- va = uvm_km_alloc(kernel_map, size, 0, UVM_KMF_VAONLY | kmflags);
-
- if (va == 0)
- return (ENOMEM);
-
- *kvap = (void *)va;
-
- pmapflags = VM_PROT_READ | VM_PROT_WRITE | PMAP_WIRED;
- if (flags & BUS_DMA_COHERENT)
- pmapflags |= PMAP_NOCACHE;
-
- for (curseg = 0; curseg < nsegs; curseg++) {
- for (addr = segs[curseg].ds_addr;
- addr < (segs[curseg].ds_addr + segs[curseg].ds_len);
- addr += PAGE_SIZE, va += PAGE_SIZE, size -= PAGE_SIZE) {
- if (size == 0)
- panic("_bus_dmamem_map: size botch");
- pmap_enter(pmap_kernel(), va, addr,
- VM_PROT_READ | VM_PROT_WRITE,
- pmapflags);
- }
- }
- pmap_update(pmap_kernel());
-
- return 0;
-}
-
-/*
- * Common function for unmapping DMA-safe memory. May be called by
- * bus-specific DMA memory unmapping functions.
- */
-void
-_bus_dmamem_unmap(bus_dma_tag_t t, void *kva, size_t size)
-{
-
- /*
- * Nothing to do if we mapped it with KSEG0 or KSEG1 (i.e.
- * not in KSEG2).
- */
- if (kva >= (void *)MIPS_KSEG0_START &&
- kva < (void *)MIPS_KSEG2_START)
- return;
-
- _bus_dmamem_unmap_common(t, kva, size);
-}
-
-/*
- * Common functin for mmap(2)'ing DMA-safe memory. May be called by
- * bus-specific DMA mmap(2)'ing functions.
- */
-paddr_t
-_bus_dmamem_mmap(bus_dma_tag_t t, bus_dma_segment_t *segs, int nsegs,
- off_t off, int prot, int flags)
-{
- bus_addr_t rv;
-
- rv = _bus_dmamem_mmap_common(t, segs, nsegs, off, prot, flags);
- if (rv == (bus_addr_t)-1)
- return (-1);
-
-#if defined(_MIPS_PADDR_T_64BIT) || defined(_LP64)
- return (mips_btop(rv | PGC_NOCACHE));
-#else
- return (mips_btop(rv));
-#endif
-}
-
+#if 0
paddr_t
bus_space_mmap(bus_space_tag_t space, bus_addr_t addr, off_t off,
int prot, int flags)
@@ -1215,382 +248,13 @@ bus_space_mmap(bus_space_tag_t space, bu
return mips_btop((MIPS_KSEG1_TO_PHYS(addr) + off));
#endif
}
+#endif
-/*
- * Utility macros; do not use outside this file.
- */
-#define __PB_TYPENAME_PREFIX(BITS) ___CONCAT(u_int,BITS)
-#define __PB_TYPENAME(BITS) ___CONCAT(__PB_TYPENAME_PREFIX(BITS),_t)
-
-/*
- * void bus_space_read_multi_N(bus_space_tag_t tag,
- * bus_space_handle_t bsh, bus_size_t offset,
- * u_intN_t *addr, bus_size_t count);
- *
- * Read `count' 1, 2, 4, or 8 byte quantities from bus space
- * described by tag/handle/offset and copy into buffer provided.
- */
-
-#define __SGIMIPS_bus_space_read_multi(BYTES,BITS) \
-void __CONCAT(bus_space_read_multi_,BYTES) \
- (bus_space_tag_t, bus_space_handle_t, bus_size_t, \
- __PB_TYPENAME(BITS) *, bus_size_t); \
- \
-void \
-__CONCAT(bus_space_read_multi_,BYTES)( \
- bus_space_tag_t t, \
- bus_space_handle_t h, \
- bus_size_t o, \
- __PB_TYPENAME(BITS) *a, \
- bus_size_t c) \
-{ \
- \
- while (c--) \
- *a++ = __CONCAT(bus_space_read_,BYTES)(t, h, o); \
-}
-
-__SGIMIPS_bus_space_read_multi(1,8)
-__SGIMIPS_bus_space_read_multi(2,16)
-__SGIMIPS_bus_space_read_multi(4,32)
-
-#undef __SGIMIPS_bus_space_read_multi
-
-#define __SGIMIPS_bus_space_read_multi_stream(BYTES,BITS) \
-void __CONCAT(bus_space_read_multi_stream_,BYTES) \
- (bus_space_tag_t, bus_space_handle_t, bus_size_t, \
- __PB_TYPENAME(BITS) *, bus_size_t); \
- \
-void \
-__CONCAT(bus_space_read_multi_stream_,BYTES)( \
- bus_space_tag_t t, \
- bus_space_handle_t h, \
- bus_size_t o, \
- __PB_TYPENAME(BITS) *a, \
- bus_size_t c) \
-{ \
- \
- while (c--) \
- *a++ = __CONCAT(bus_space_read_stream_,BYTES)(t, h, o); \
-}
-
-
-__SGIMIPS_bus_space_read_multi_stream(2,16)
-__SGIMIPS_bus_space_read_multi_stream(4,32)
-
-#undef __SGIMIPS_bus_space_read_multi_stream
-
-/*
- * void bus_space_read_region_N(bus_space_tag_t tag,
- * bus_space_handle_t bsh, bus_size_t offset,
- * u_intN_t *addr, bus_size_t count);
- *
- * Read `count' 1, 2, 4, or 8 byte quantities from bus space
- * described by tag/handle and starting at `offset' and copy into
- * buffer provided.
- */
-
-#define __SGIMIPS_bus_space_read_region(BYTES,BITS) \
-void __CONCAT(bus_space_read_region_,BYTES) \
- (bus_space_tag_t, bus_space_handle_t, bus_size_t, \
- __PB_TYPENAME(BITS) *, bus_size_t); \
- \
-void \
-__CONCAT(bus_space_read_region_,BYTES)( \
- bus_space_tag_t t, \
- bus_space_handle_t h, \
- bus_size_t o, \
- __PB_TYPENAME(BITS) *a, \
- bus_size_t c) \
-{ \
- \
- while (c--) { \
- *a++ = __CONCAT(bus_space_read_,BYTES)(t, h, o); \
- o += BYTES; \
- } \
-}
-
-__SGIMIPS_bus_space_read_region(1,8)
-__SGIMIPS_bus_space_read_region(2,16)
-__SGIMIPS_bus_space_read_region(4,32)
-
-#undef __SGIMIPS_bus_space_read_region
-
-/*
- * void bus_space_read_region_stream_N(bus_space_tag_t tag,
- * bus_space_handle_t bsh, bus_size_t offset,
- * u_intN_t *addr, bus_size_t count);
- *
- * Read `count' 1, 2, 4, or 8 byte quantities from bus space
- * described by tag/handle and starting at `offset' and copy into
- * buffer provided. No byte order translation is done.
- */
-
-#define __SGIMIPS_bus_space_read_region_stream(BYTES,BITS) \
-void __CONCAT(bus_space_read_region_stream_,BYTES) \
- (bus_space_tag_t, bus_space_handle_t, bus_size_t, \
- __PB_TYPENAME(BITS) *, bus_size_t); \
- \
-void \
-__CONCAT(bus_space_read_region_stream_,BYTES)( \
- bus_space_tag_t t, \
- bus_space_handle_t h, \
- bus_size_t o, \
- __PB_TYPENAME(BITS) *a, \
- bus_size_t c) \
-{ \
- \
- while (c--) { \
- *a++ = __CONCAT(bus_space_read_stream_,BYTES)(t, h, o); \
- o += BYTES; \
- } \
-}
-
-__SGIMIPS_bus_space_read_region_stream(2,16)
-__SGIMIPS_bus_space_read_region_stream(4,32)
-
-#undef __SGIMIPS_bus_space_read_region_stream
-
-/*
- * void bus_space_write_multi_N(bus_space_tag_t tag,
- * bus_space_handle_t bsh, bus_size_t offset,
- * const u_intN_t *addr, bus_size_t count);
- *
- * Write `count' 1, 2, 4, or 8 byte quantities from the buffer
- * provided to bus space described by tag/handle/offset.
- */
-
-#define __SGIMIPS_bus_space_write_multi(BYTES,BITS) \
-void __CONCAT(bus_space_write_multi_,BYTES) \
- (bus_space_tag_t, bus_space_handle_t, bus_size_t, \
- const __PB_TYPENAME(BITS) *, bus_size_t); \
- \
-void \
-__CONCAT(bus_space_write_multi_,BYTES)( \
- bus_space_tag_t t, \
- bus_space_handle_t h, \
- bus_size_t o, \
- const __PB_TYPENAME(BITS) *a, \
- bus_size_t c) \
-{ \
- \
- while (c--) \
- __CONCAT(bus_space_write_,BYTES)(t, h, o, *a++); \
-}
-
-__SGIMIPS_bus_space_write_multi(1,8)
-__SGIMIPS_bus_space_write_multi(2,16)
-__SGIMIPS_bus_space_write_multi(4,32)
-
-#undef __SGIMIPS_bus_space_write_multi
-
-#define __SGIMIPS_bus_space_write_multi_stream(BYTES,BITS) \
-void __CONCAT(bus_space_write_multi_stream_,BYTES) \
- (bus_space_tag_t, bus_space_handle_t, bus_size_t, \
- const __PB_TYPENAME(BITS) *, bus_size_t); \
- \
-void \
-__CONCAT(bus_space_write_multi_stream_,BYTES)( \
- bus_space_tag_t t, \
- bus_space_handle_t h, \
- bus_size_t o, \
- const __PB_TYPENAME(BITS) *a, \
- bus_size_t c) \
-{ \
- \
- while (c--) \
- __CONCAT(bus_space_write_stream_,BYTES)(t, h, o, *a++); \
-}
-
-__SGIMIPS_bus_space_write_multi_stream(2,16)
-__SGIMIPS_bus_space_write_multi_stream(4,32)
-
-#undef __SGIMIPS_bus_space_write_multi_stream
-
-/*
- * void bus_space_write_region_N(bus_space_tag_t tag,
- * bus_space_handle_t bsh, bus_size_t offset,
- * const u_intN_t *addr, bus_size_t count);
- *
- * Write `count' 1, 2, 4, or 8 byte quantities from the buffer provided
- * to bus space described by tag/handle starting at `offset'.
- */
-
-#define __SGIMIPS_bus_space_write_region(BYTES,BITS) \
-void __CONCAT(bus_space_write_region_,BYTES) \
- (bus_space_tag_t, bus_space_handle_t, bus_size_t, \
- const __PB_TYPENAME(BITS) *, bus_size_t); \
- \
-void \
-__CONCAT(bus_space_write_region_,BYTES)( \
- bus_space_tag_t t, \
- bus_space_handle_t h, \
- bus_size_t o, \
- const __PB_TYPENAME(BITS) *a, \
- bus_size_t c) \
-{ \
- \
- while (c--) { \
- __CONCAT(bus_space_write_,BYTES)(t, h, o, *a++); \
- o += BYTES; \
- } \
-}
-
-__SGIMIPS_bus_space_write_region(1,8)
-__SGIMIPS_bus_space_write_region(2,16)
-__SGIMIPS_bus_space_write_region(4,32)
-
-#undef __SGIMIPS_bus_space_write_region
-
-/*
- * void bus_space_write_region_stream_N(bus_space_tag_t tag,
- * bus_space_handle_t bsh, bus_size_t offset,
- * const u_intN_t *addr, bus_size_t count);
- *
- * Write `count' 1, 2, 4, or 8 byte quantities from the buffer provided
- * to bus space described by tag/handle starting at `offset', but without
- * byte-order translation
- */
-
-#define __SGIMIPS_bus_space_write_region_stream(BYTES,BITS) \
-void __CONCAT(bus_space_write_region_stream_,BYTES) \
- (bus_space_tag_t, bus_space_handle_t, bus_size_t, \
- const __PB_TYPENAME(BITS) *, bus_size_t); \
- \
-void \
-__CONCAT(bus_space_write_region_stream_,BYTES)( \
- bus_space_tag_t t, \
- bus_space_handle_t h, \
- bus_size_t o, \
- const __PB_TYPENAME(BITS) *a, \
- bus_size_t c) \
-{ \
- \
- while (c--) { \
- __CONCAT(bus_space_write_stream_,BYTES)(t, h, o, *a++); \
- o += BYTES; \
- } \
-}
-
-__SGIMIPS_bus_space_write_region_stream(2,16)
-__SGIMIPS_bus_space_write_region_stream(4,32)
-
-#undef __SGIMIPS_bus_space_write_region_stream
-
-/*
- * void bus_space_set_multi_N(bus_space_tag_t tag,
- * bus_space_handle_t bsh, bus_size_t offset, u_intN_t val,
- * bus_size_t count);
- *
- * Write the 1, 2, 4, or 8 byte value `val' to bus space described
- * by tag/handle/offset `count' times.
- */
-
-#define __SGIMIPS_bus_space_set_multi(BYTES,BITS) \
-void __CONCAT(bus_space_set_multi_,BYTES) \
- (bus_space_tag_t, bus_space_handle_t, bus_size_t, \
- __PB_TYPENAME(BITS), bus_size_t); \
- \
-void \
-__CONCAT(bus_space_set_multi_,BYTES)( \
- bus_space_tag_t t, \
- bus_space_handle_t h, \
- bus_size_t o, \
- __PB_TYPENAME(BITS) v, \
- bus_size_t c) \
-{ \
- \
- while (c--) \
- __CONCAT(bus_space_write_,BYTES)(t, h, o, v); \
-}
-
-__SGIMIPS_bus_space_set_multi(1,8)
-__SGIMIPS_bus_space_set_multi(2,16)
-__SGIMIPS_bus_space_set_multi(4,32)
-
-#undef __SGIMIPS_bus_space_set_multi
-
-/*
- * void bus_space_set_region_N(bus_space_tag_t tag,
- * bus_space_handle_t bsh, bus_size_t offset, u_intN_t val,
- * bus_size_t count);
- *
- * Write `count' 1, 2, 4, or 8 byte value `val' to bus space described
- * by tag/handle starting at `offset'.
- */
-
-#define __SGIMIPS_bus_space_set_region(BYTES,BITS) \
-void __CONCAT(bus_space_set_region_,BYTES) \
- (bus_space_tag_t, bus_space_handle_t, bus_size_t, \
- __PB_TYPENAME(BITS), bus_size_t); \
- \
-void \
-__CONCAT(bus_space_set_region_,BYTES)( \
- bus_space_tag_t t, \
- bus_space_handle_t h, \
- bus_size_t o, \
- __PB_TYPENAME(BITS) v, \
- bus_size_t c) \
-{ \
- \
- while (c--) { \
- __CONCAT(bus_space_write_,BYTES)(t, h, o, v); \
- o += BYTES; \
- } \
-}
-
-__SGIMIPS_bus_space_set_region(1,8)
-__SGIMIPS_bus_space_set_region(2,16)
-__SGIMIPS_bus_space_set_region(4,32)
-
-#undef __SGIMIPS_bus_space_set_region
-
-/*
- * void bus_space_copy_region_N(bus_space_tag_t tag,
- * bus_space_handle_t bsh1, bus_size_t off1,
- * bus_space_handle_t bsh2, bus_size_t off2,
- * bus_size_t count);
- *
- * Copy `count' 1, 2, 4, or 8 byte values from bus space starting
- * at tag/bsh1/off1 to bus space starting at tag/bsh2/off2.
- */
-
-#define __SGIMIPS_copy_region(BYTES) \
-void __CONCAT(bus_space_copy_region_,BYTES) \
- (bus_space_tag_t, \
- bus_space_handle_t bsh1, bus_size_t off1, \
- bus_space_handle_t bsh2, bus_size_t off2, \
- bus_size_t count); \
- \
-void \
-__CONCAT(bus_space_copy_region_,BYTES)( \
- bus_space_tag_t t, \
- bus_space_handle_t h1, \
- bus_size_t o1, \
- bus_space_handle_t h2, \
- bus_size_t o2, \
- bus_size_t c) \
-{ \
- bus_size_t o; \
- \
- if ((h1 + o1) >= (h2 + o2)) { \
- /* src after dest: copy forward */ \
- for (o = 0; c != 0; c--, o += BYTES) \
- __CONCAT(bus_space_write_,BYTES)(t, h2, o2 + o, \
- __CONCAT(bus_space_read_,BYTES)(t, h1, o1 + o)); \
- } else { \
- /* dest after src: copy backwards */ \
- for (o = (c - 1) * BYTES; c != 0; c--, o -= BYTES) \
- __CONCAT(bus_space_write_,BYTES)(t, h2, o2 + o, \
- __CONCAT(bus_space_read_,BYTES)(t, h1, o1 + o)); \
- } \
-}
-
-__SGIMIPS_copy_region(1)
-__SGIMIPS_copy_region(2)
-__SGIMIPS_copy_region(4)
-
-#undef __SGIMIPS_copy_region
-
-#undef __PB_TYPENAME_PREFIX
-#undef __PB_TYPENAME
+#define CHIP normal
+#define CHIP_MEM /* defined */
+#define CHIP_W1_BUS_START(v) 0x00000000UL
+#define CHIP_W1_BUS_END(v) 0xffffffffUL
+#define CHIP_W1_SYS_START(v) 0x00000000UL
+#define CHIP_W1_SYS_END(v) 0xffffffffUL
+#include <mips/mips/bus_space_alignstride_chipdep.c>
Index: src/sys/arch/sgimips/sgimips/console.c
diff -u src/sys/arch/sgimips/sgimips/console.c:1.43 src/sys/arch/sgimips/sgimips/console.c:1.44
--- src/sys/arch/sgimips/sgimips/console.c:1.43 Sat Oct 13 17:58:54 2012
+++ src/sys/arch/sgimips/sgimips/console.c Wed Feb 18 16:47:59 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: console.c,v 1.43 2012/10/13 17:58:54 jdc Exp $ */
+/* $NetBSD: console.c,v 1.44 2015/02/18 16:47:59 macallan Exp $ */
/*
* Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
@@ -28,7 +28,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: console.c,v 1.43 2012/10/13 17:58:54 jdc Exp $");
+__KERNEL_RCSID(0, "$NetBSD: console.c,v 1.44 2015/02/18 16:47:59 macallan Exp $");
#include "opt_kgdb.h"
@@ -115,7 +115,8 @@ consinit(void)
#if notyet
#if (NPCKBC > 0)
/* XXX Hardcoded iotag, MACE address XXX */
- pckbc_cnattach(SGIMIPS_BUS_SPACE_NORMAL,
+ mace_init_bus();
+ pckbc_cnattach(mace_isa_memt,
MACE_BASE + 0x320000, 8,
PCKBC_KBD_SLOT, 0);
#endif
@@ -191,7 +192,7 @@ gio_video_init(const char *consdev)
case MACH_SGI_IP22:
#if (NPCKBC > 0)
/* XXX Hardcoded iotag, HPC address XXX */
- pckbc_cnattach(SGIMIPS_BUS_SPACE_HPC,
+ pckbc_cnattach(normal_memt,
HPC_BASE_ADDRESS_0 +
HPC3_PBUS_CH6_DEVREGS + IOC_KB_REGS, KBCMDP,
PCKBC_KBD_SLOT, 0);
@@ -225,7 +226,8 @@ mace_serial_init(const char *consdev)
delay(10000);
/* XXX: hardcoded MACE iotag */
- if (comcnattach(SGIMIPS_BUS_SPACE_MACE, MIPS_PHYS_TO_KSEG1(MACE_BASE + base),
+ mace_init_bus();
+ if (comcnattach(mace_isa_memt, MIPS_PHYS_TO_KSEG1(MACE_BASE + base),
speed, COM_FREQ, COM_TYPE_NORMAL, comcnmode) == 0)
return (1);
}
@@ -240,9 +242,11 @@ kgdb_port_init(void)
{
# if (NCOM > 0)
# define KGDB_DEVMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8)
- if (mach_type == MACH_SGI_IP32)
- com_kgdb_attach(SGIMIPS_BUS_SPACE_MACE, 0xbf398000, 9600, COM_FREQ, COM_TYPE_NORMAL,
+ if (mach_type == MACH_SGI_IP32) {
+ mace_init_bus();
+ com_kgdb_attach(mace_isa_memt, 0xbf398000, 9600, COM_FREQ, COM_TYPE_NORMAL,
KGDB_DEVMODE);
+ }
# endif /* (NCOM > 0) */
# if (NZSC > 0)
