Module Name: src
Committed By: jmcneill
Date: Fri Feb 27 20:40:09 UTC 2015
Modified Files:
src/sys/arch/arm/cortex: armperiph.c pl310.c
Log Message:
allow arml2cc to be used on Cortex-A5 if the "offset" property is specified
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/arm/cortex/armperiph.c
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/arm/cortex/pl310.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/armperiph.c
diff -u src/sys/arch/arm/cortex/armperiph.c:1.6 src/sys/arch/arm/cortex/armperiph.c:1.7
--- src/sys/arch/arm/cortex/armperiph.c:1.6 Fri Feb 27 18:43:28 2015
+++ src/sys/arch/arm/cortex/armperiph.c Fri Feb 27 20:40:09 2015
@@ -31,7 +31,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: armperiph.c,v 1.6 2015/02/27 18:43:28 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: armperiph.c,v 1.7 2015/02/27 20:40:09 jmcneill Exp $");
#include <sys/param.h>
#include <sys/device.h>
@@ -64,6 +64,7 @@ static const struct armperiph_info a5_de
{ "armgic", 0x1000, 0x0100 },
{ "a9tmr", 0x0200, 0 },
{ "a9wdt", 0x0600, 0 },
+ { "arml2cc", 0, 0 }, /* external; needs "offset" property */
{ "", 0, 0 },
};
#endif
Index: src/sys/arch/arm/cortex/pl310.c
diff -u src/sys/arch/arm/cortex/pl310.c:1.16 src/sys/arch/arm/cortex/pl310.c:1.17
--- src/sys/arch/arm/cortex/pl310.c:1.16 Mon Dec 1 22:39:06 2014
+++ src/sys/arch/arm/cortex/pl310.c Fri Feb 27 20:40:09 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: pl310.c,v 1.16 2014/12/01 22:39:06 matt Exp $ */
+/* $NetBSD: pl310.c,v 1.17 2015/02/27 20:40:09 jmcneill Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pl310.c,v 1.16 2014/12/01 22:39:06 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pl310.c,v 1.17 2015/02/27 20:40:09 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -99,7 +99,8 @@ arml2cc_match(device_t parent, cfdata_t
if (arml2cc_sc)
return 0;
- if (!CPU_ID_CORTEX_A9_P(curcpu()->ci_arm_cpuid))
+ if (!CPU_ID_CORTEX_A9_P(curcpu()->ci_arm_cpuid) &&
+ !CPU_ID_CORTEX_A5_P(curcpu()->ci_arm_cpuid))
return 0;
if (strcmp(mpcaa->mpcaa_name, cf->cf_name) != 0)
@@ -138,7 +139,17 @@ arml2cc_attach(device_t parent, device_t
prop_dictionary_t dict = device_properties(self);
uint32_t off;
+ aprint_naive("\n");
+
if (!prop_dictionary_get_uint32(dict, "offset", &off)) {
+ if (CPU_ID_CORTEX_A5_P(curcpu()->ci_arm_cpuid)) {
+ /*
+ * PL310 on Cortex-A5 is external to PERIPHBASE, so
+ * "offset" property is required.
+ */
+ aprint_normal(": not configured\n");
+ return;
+ }
off = L2CC_BASE;
}
@@ -172,7 +183,6 @@ arml2cc_attach(device_t parent, device_t
const bool enabled_p = arml2cc_read_4(sc, L2C_CTL) != 0;
- aprint_naive("\n");
aprint_normal(": ARM PL310%s L2 Cache Controller%s\n",
revstr, enabled_p ? "" : " (disabled)");
