Module Name: src Committed By: macallan Date: Sat Mar 7 15:49:20 UTC 2015
Modified Files: src/sys/dev/ic: com.c comreg.h Log Message: more Ingenic support: - make sure we always set FIFO_UART_ON - deal with the absence of DCD support - enable the TX FIFO timeout interrupt - set COM_HW_NOIEN - pretend the FIFO is only 16 bytes deep ( supposed to be 64 but I get overruns with that ) now this works as CI20 console To generate a diff of this commit: cvs rdiff -u -r1.329 -r1.330 src/sys/dev/ic/com.c cvs rdiff -u -r1.23 -r1.24 src/sys/dev/ic/comreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/dev/ic/com.c diff -u src/sys/dev/ic/com.c:1.329 src/sys/dev/ic/com.c:1.330 --- src/sys/dev/ic/com.c:1.329 Sat Nov 22 15:14:35 2014 +++ src/sys/dev/ic/com.c Sat Mar 7 15:49:20 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: com.c,v 1.329 2014/11/22 15:14:35 macallan Exp $ */ +/* $NetBSD: com.c,v 1.330 2015/03/07 15:49:20 macallan Exp $ */ /*- * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. @@ -66,7 +66,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: com.c,v 1.329 2014/11/22 15:14:35 macallan Exp $"); +__KERNEL_RCSID(0, "$NetBSD: com.c,v 1.330 2015/03/07 15:49:20 macallan Exp $"); #include "opt_com.h" #include "opt_ddb.h" @@ -382,6 +382,8 @@ com_enable_debugport(struct com_softc *s sc->sc_ier = IER_ERXRDY; if (sc->sc_type == COM_TYPE_PXA2x0) sc->sc_ier |= IER_EUART | IER_ERXTOUT; + if (sc->sc_type == COM_TYPE_INGENIC) + sc->sc_ier |= IER_ERXTOUT; CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); SET(sc->sc_mcr, MCR_DTR | MCR_RTS); CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); @@ -461,16 +463,22 @@ com_attach_subr(struct com_softc *sc) goto fifodelay; case COM_TYPE_INGENIC: - sc->sc_fifolen = 64; + sc->sc_fifolen = 16; fifo_msg = "Ingenic UART, working fifo"; SET(sc->sc_hwflags, COM_HW_FIFO); + SET(sc->sc_hwflags, COM_HW_NOIEN); goto fifodelay; } sc->sc_fifolen = 1; /* look for a NS 16550AF UART with FIFOs */ - CSR_WRITE_1(regsp, COM_REG_FIFO, - FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); + if(sc->sc_type == COM_TYPE_INGENIC) { + CSR_WRITE_1(regsp, COM_REG_FIFO, + FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | + FIFO_TRIGGER_14 | FIFO_UART_ON); + } else + CSR_WRITE_1(regsp, COM_REG_FIFO, + FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); delay(100); if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) == IIR_FIFO_MASK) @@ -519,6 +527,9 @@ com_attach_subr(struct com_softc *sc) uint8_t iir1, iir2; const uint8_t fcr = FIFO_ENABLE | FIFO_TRIGGER_14; + if(sc->sc_type == COM_TYPE_INGENIC) + fcr |= FIFO_UART_ON; + lcr = CSR_READ_1(regsp, COM_REG_LCR); CSR_WRITE_1(regsp, COM_REG_LCR, lcr & ~LCR_DLAB); CSR_WRITE_1(regsp, COM_REG_FIFO, fcr | FIFO_64B_ENABLE); @@ -557,7 +568,10 @@ com_attach_subr(struct com_softc *sc) fifo_msg = "ns16550, broken fifo"; else fifo_msg = "ns8250 or ns16450, no fifo"; - CSR_WRITE_1(regsp, COM_REG_FIFO, 0); + if(sc->sc_type == COM_TYPE_INGENIC) { + CSR_WRITE_1(regsp, COM_REG_FIFO, FIFO_UART_ON); + } else + CSR_WRITE_1(regsp, COM_REG_FIFO, 0); fifodelay: /* * Some chips will clear down both Tx and Rx FIFOs when zero is @@ -800,7 +814,8 @@ com_shutdown(struct com_softc *sc) /* Turn off interrupts. */ if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { sc->sc_ier = IER_ERXRDY; /* interrupt on break */ - if (sc->sc_type == COM_TYPE_PXA2x0) + if ((sc->sc_type == COM_TYPE_PXA2x0) || + (sc->sc_type == COM_TYPE_INGENIC)) sc->sc_ier |= IER_ERXTOUT; } else sc->sc_ier = 0; @@ -882,6 +897,8 @@ comopen(dev_t dev, int flag, int mode, s if (sc->sc_type == COM_TYPE_PXA2x0) sc->sc_ier |= IER_EUART | IER_ERXTOUT; + else if (sc->sc_type == COM_TYPE_INGENIC) + sc->sc_ier |= IER_ERXTOUT; CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); /* Fetch the current modem control status, needed later. */ @@ -1266,8 +1283,12 @@ com_to_tiocm(struct com_softc *sc) SET(ttybits, TIOCM_RTS); combits = sc->sc_msr; - if (ISSET(combits, MSR_DCD)) + if (sc->sc_type == COM_TYPE_INGENIC) { SET(ttybits, TIOCM_CD); + } else { + if (ISSET(combits, MSR_DCD)) + SET(ttybits, TIOCM_CD); + } if (ISSET(combits, MSR_CTS)) SET(ttybits, TIOCM_CTS); if (ISSET(combits, MSR_DSR)) @@ -1458,6 +1479,9 @@ comparam(struct tty *tp, struct termios } else sc->sc_fifo = 0; + if(sc->sc_type == COM_TYPE_INGENIC) + sc->sc_fifo |= FIFO_UART_ON; + /* And copy to tty. */ tp->t_ispeed = t->c_ospeed; tp->t_ospeed = t->c_ospeed; @@ -1496,7 +1520,11 @@ comparam(struct tty *tp, struct termios * CLOCAL or MDMBUF. We don't hang up here; we only do that by * explicit request. */ - (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); + if (sc->sc_type == COM_TYPE_INGENIC) { + /* no DCD here */ + (void) (*tp->t_linesw->l_modem)(tp, 1); + } else + (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); #ifdef COM_DEBUG if (com_debug) @@ -1878,7 +1906,10 @@ com_rxsoft(struct com_softc *sc, struct if (sc->sc_type == COM_TYPE_PXA2x0) SET(sc->sc_ier, IER_ERXTOUT); #endif - CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); + if (sc->sc_type == COM_TYPE_INGENIC) + sc->sc_ier |= IER_ERXTOUT; + CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, + sc->sc_ier); } if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); @@ -2080,6 +2111,9 @@ again: do { CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); else #endif + if (sc->sc_type == COM_TYPE_INGENIC) + sc->sc_ier |= IER_ERXRDY|IER_ERXTOUT; + else CLR(sc->sc_ier, IER_ERXRDY); CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); } @@ -2296,7 +2330,8 @@ cominit(struct com_regs *regsp, int rate CSR_WRITE_2(regsp, COM_REG_DLBL, rate); } else { /* no EFR on alchemy */ - if (type != COM_TYPE_16550_NOERS) { + if ((type != COM_TYPE_16550_NOERS) && + (type != COM_TYPE_INGENIC)) { CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); CSR_WRITE_1(regsp, COM_REG_EFR, 0); } Index: src/sys/dev/ic/comreg.h diff -u src/sys/dev/ic/comreg.h:1.23 src/sys/dev/ic/comreg.h:1.24 --- src/sys/dev/ic/comreg.h:1.23 Sat Nov 22 15:14:35 2014 +++ src/sys/dev/ic/comreg.h Sat Mar 7 15:49:20 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: comreg.h,v 1.23 2014/11/22 15:14:35 macallan Exp $ */ +/* $NetBSD: comreg.h,v 1.24 2015/03/07 15:49:20 macallan Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -50,6 +50,7 @@ #define IER_ERTS 0x40 /* Enable RTS interrupt */ #define IER_ECTS 0x80 /* Enable CTS interrupt */ /* PXA2X0's ns16550 ports have extra bits in this register */ +/* Ingenic's got this one too */ #define IER_ERXTOUT 0x10 /* Enable rx timeout interrupt */ #define IER_EUART 0x40 /* Enable UART */ @@ -111,7 +112,9 @@ /* modem control register */ #define MCR_PRESCALE 0x80 /* 16650/16950: Baud rate prescaler select */ +#define MCR_MDCE 0x80 /* Ingenic: modem control enable */ #define MCR_TCR_TLR 0x40 /* OMAP: enables access to the TCR & TLR regs */ +#define MCR_FCM 0x40 /* Ingenic: 1 - hardware flow control */ #define MCR_XONENABLE 0x20 /* OMAP XON_EN */ #define MCR_AFE 0x20 /* tl16c750: Flow Control Enable */ #define MCR_LOOPBACK 0x10 /* Loop test: echos from TX to RX */