Module Name: src
Committed By: skrll
Date: Fri Mar 13 07:57:08 UTC 2015
Modified Files:
src/sys/arch/arm/omap: if_cpsw.c if_cpswreg.h
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/omap/if_cpsw.c
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/omap/if_cpswreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/omap/if_cpsw.c
diff -u src/sys/arch/arm/omap/if_cpsw.c:1.7 src/sys/arch/arm/omap/if_cpsw.c:1.8
--- src/sys/arch/arm/omap/if_cpsw.c:1.7 Sun Feb 1 19:32:59 2015
+++ src/sys/arch/arm/omap/if_cpsw.c Fri Mar 13 07:57:08 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: if_cpsw.c,v 1.7 2015/02/01 19:32:59 christos Exp $ */
+/* $NetBSD: if_cpsw.c,v 1.8 2015/03/13 07:57:08 skrll Exp $ */
/*
* Copyright (c) 2013 Jonathan A. Kollasch
@@ -53,7 +53,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: if_cpsw.c,v 1.7 2015/02/01 19:32:59 christos Exp $");
+__KERNEL_RCSID(1, "$NetBSD: if_cpsw.c,v 1.8 2015/03/13 07:57:08 skrll Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -1460,7 +1460,7 @@ cpsw_ale_mc_entry_set(struct cpsw_softc
for (i = 0; i < CPSW_MAX_ALE_ENTRIES; i++) {
cpsw_ale_read_entry(sc, i, ale_entry);
- /* Entry Type[61:60] is 0 for free entry */
+ /* Entry Type[61:60] is 0 for free entry */
if (free_index < 0 && ((ale_entry[1] >> 28) & 3) == 0) {
free_index = i;
}
Index: src/sys/arch/arm/omap/if_cpswreg.h
diff -u src/sys/arch/arm/omap/if_cpswreg.h:1.2 src/sys/arch/arm/omap/if_cpswreg.h:1.3
--- src/sys/arch/arm/omap/if_cpswreg.h:1.2 Wed Feb 26 03:58:33 2014
+++ src/sys/arch/arm/omap/if_cpswreg.h Fri Mar 13 07:57:08 2015
@@ -132,7 +132,7 @@ struct cpsw_cpdma_bd {
/* Interrupt offsets */
#define CPSW_INTROFF_RXTH 0
-#define CPSW_INTROFF_RX 1
+#define CPSW_INTROFF_RX 1
#define CPSW_INTROFF_TX 2
#define CPSW_INTROFF_MISC 3
@@ -166,7 +166,7 @@ struct cpsw_cpdma_bd {
#define GMIISEL_RGMII2_IDMODE __BIT32(5)
#define GMIISEL_RGMII1_IDMODE __BIT32(4)
#define GMIISEL_GMII2_SEL(val) ((0x3 & (val)) << 2)
-#define GMIISEL_GMII1_SEL(val) ((0x3 & (val)) << 0)
+#define GMIISEL_GMII1_SEL(val) ((0x3 & (val)) << 0)
#define GMII_MODE 0
#define RMII_MODE 1
#define RGMII_MODE 2
