Module Name: src
Committed By: hkenken
Date: Fri Mar 27 05:31:23 UTC 2015
Modified Files:
src/sys/arch/arm/imx: files.imx51 files.imx6 imx51_i2c.c imx51reg.h
imx6_i2c.c imx6_reg.h imxi2c.c imxi2cvar.h
Removed Files:
src/sys/arch/arm/imx: imxi2creg.h
Log Message:
Rewritten to take advantage of motoi2c code.
To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/arm/imx/files.imx51
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/imx/files.imx6
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/imx/imx51_i2c.c \
src/sys/arch/arm/imx/imx6_i2c.c src/sys/arch/arm/imx/imxi2c.c \
src/sys/arch/arm/imx/imxi2cvar.h
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/imx/imx51reg.h
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/imx/imx6_reg.h
cvs rdiff -u -r1.2 -r0 src/sys/arch/arm/imx/imxi2creg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/imx/files.imx51
diff -u src/sys/arch/arm/imx/files.imx51:1.11 src/sys/arch/arm/imx/files.imx51:1.12
--- src/sys/arch/arm/imx/files.imx51:1.11 Fri Jul 25 07:49:56 2014
+++ src/sys/arch/arm/imx/files.imx51 Fri Mar 27 05:31:23 2015
@@ -1,4 +1,4 @@
-# $NetBSD: files.imx51,v 1.11 2014/07/25 07:49:56 hkenken Exp $
+# $NetBSD: files.imx51,v 1.12 2015/03/27 05:31:23 hkenken Exp $
#
# Configuration info for the Freescale i.MX5x
#
@@ -103,7 +103,7 @@ attach sdhc at axi with sdhc_axi
file arch/arm/imx/imx51_esdhc.c sdhc_axi
# iic Controler
-device imxi2c: i2cbus
+device imxi2c: motoi2c, i2cbus, i2cexec
attach imxi2c at axi
file arch/arm/imx/imxi2c.c imxi2c
file arch/arm/imx/imx51_i2c.c imxi2c
Index: src/sys/arch/arm/imx/files.imx6
diff -u src/sys/arch/arm/imx/files.imx6:1.4 src/sys/arch/arm/imx/files.imx6:1.5
--- src/sys/arch/arm/imx/files.imx6:1.4 Tue Oct 7 09:36:09 2014
+++ src/sys/arch/arm/imx/files.imx6 Fri Mar 27 05:31:23 2015
@@ -1,4 +1,4 @@
-# $NetBSD: files.imx6,v 1.4 2014/10/07 09:36:09 ryo Exp $
+# $NetBSD: files.imx6,v 1.5 2015/03/27 05:31:23 hkenken Exp $
#
# Configuration info for the Freescale i.MX6
#
@@ -62,7 +62,7 @@ attach imxiomux at axi
file arch/arm/imx/imx6_iomux.c imxiomux
# iMX iic Controler
-device imxi2c: i2cbus
+device imxi2c: motoi2c, i2cbus, i2cexec
attach imxi2c at axi
file arch/arm/imx/imxi2c.c imxi2c
file arch/arm/imx/imx6_i2c.c imxi2c
Index: src/sys/arch/arm/imx/imx51_i2c.c
diff -u src/sys/arch/arm/imx/imx51_i2c.c:1.1 src/sys/arch/arm/imx/imx51_i2c.c:1.2
--- src/sys/arch/arm/imx/imx51_i2c.c:1.1 Fri Jul 25 07:07:47 2014
+++ src/sys/arch/arm/imx/imx51_i2c.c Fri Mar 27 05:31:23 2015
@@ -1,7 +1,7 @@
-/* $NetBSD: imx51_i2c.c,v 1.1 2014/07/25 07:07:47 hkenken Exp $ */
+/* $NetBSD: imx51_i2c.c,v 1.2 2015/03/27 05:31:23 hkenken Exp $ */
/*
- * Copyright (c) 2012 Genetec Corporation. All rights reserved.
+ * Copyright (c) 2012, 2015 Genetec Corporation. All rights reserved.
* Written by Hashimoto Kenichi for Genetec Corporation.
*
* Redistribution and use in source and binary forms, with or without
@@ -27,24 +27,32 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: imx51_i2c.c,v 1.1 2014/07/25 07:07:47 hkenken Exp $");
+__KERNEL_RCSID(0, "$NetBSD: imx51_i2c.c,v 1.2 2015/03/27 05:31:23 hkenken Exp $");
+
+#include "opt_imx.h"
#include <sys/param.h>
#include <sys/bus.h>
#include <sys/device.h>
-#include "opt_imx.h"
-
-#include <arm/imx/imxi2cvar.h>
#include <arm/imx/imx51reg.h>
#include <arm/imx/imx51var.h>
#include <arm/imx/imx51_ccmvar.h>
+#include <arm/imx/imxi2cvar.h>
int
imxi2c_match(device_t parent, cfdata_t cf, void *aux)
{
- if (strcmp(cf->cf_name, "imxi2c") == 0)
+ struct axi_attach_args *aa = aux;
+
+ switch (aa->aa_addr) {
+ case I2C1_BASE:
+ case I2C2_BASE:
+#ifdef IMX50
+ case I2C3_BASE:
+#endif
return 1;
+ }
return 0;
}
@@ -53,15 +61,11 @@ void
imxi2c_attach(device_t parent, device_t self, void *aux)
{
struct axi_attach_args * aa = aux;
- struct imxi2c_softc *sc = device_private(self);
- struct i2cbus_attach_args iba;
- imxi2c_attach_common(parent, self,
- aa->aa_iot, aa->aa_addr, aa->aa_size, aa->aa_irq, 0);
+ if (aa->aa_size <= 0)
+ aa->aa_size = I2C_SIZE;
imxi2c_set_freq(self, imx51_get_clock(IMX51CLK_PERCLK_ROOT), 400000);
-
- memset(&iba, 0, sizeof(iba));
- iba.iba_tag = &sc->sc_i2c;
- config_found_ia(sc->sc_dev, "i2cbus", &iba, iicbus_print);
+ imxi2c_attach_common(parent, self,
+ aa->aa_iot, aa->aa_addr, aa->aa_size, aa->aa_irq, 0);
}
Index: src/sys/arch/arm/imx/imx6_i2c.c
diff -u src/sys/arch/arm/imx/imx6_i2c.c:1.1 src/sys/arch/arm/imx/imx6_i2c.c:1.2
--- src/sys/arch/arm/imx/imx6_i2c.c:1.1 Tue Oct 7 09:36:09 2014
+++ src/sys/arch/arm/imx/imx6_i2c.c Fri Mar 27 05:31:23 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: imx6_i2c.c,v 1.1 2014/10/07 09:36:09 ryo Exp $ */
+/* $NetBSD: imx6_i2c.c,v 1.2 2015/03/27 05:31:23 hkenken Exp $ */
/*
* Copyright (c) 2014 Ryo Shimizu <[email protected]>
@@ -31,7 +31,9 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: imx6_i2c.c,v 1.1 2014/10/07 09:36:09 ryo Exp $");
+__KERNEL_RCSID(0, "$NetBSD: imx6_i2c.c,v 1.2 2015/03/27 05:31:23 hkenken Exp $");
+
+#include "opt_imx.h"
#include <sys/bus.h>
#include <sys/device.h>
@@ -46,9 +48,7 @@ __KERNEL_RCSID(0, "$NetBSD: imx6_i2c.c,v
int
imxi2c_match(device_t parent __unused, struct cfdata *match __unused, void *aux)
{
- struct axi_attach_args *aa;
-
- aa = aux;
+ struct axi_attach_args *aa = aux;
switch (aa->aa_addr) {
case IMX6_AIPS2_BASE + AIPS2_I2C1_BASE:
@@ -64,20 +64,13 @@ imxi2c_match(device_t parent __unused, s
void
imxi2c_attach(device_t parent __unused, device_t self, void *aux)
{
- struct imxi2c_softc *sc;
- struct axi_attach_args *aa;
- struct i2cbus_attach_args iba;
+ struct axi_attach_args *aa = aux;
- aa = aux;
- sc = device_private(self);
-
- imxi2c_attach_common(parent, self, aa->aa_iot, aa->aa_addr, aa->aa_size,
- aa->aa_irq, 0);
+ if (aa->aa_size <= 0)
+ aa->aa_size = I2C_SIZE;
imxi2c_set_freq(self, imx6_get_clock(IMX6CLK_PERCLK), 400000);
-
- memset(&iba, 0, sizeof(iba));
- iba.iba_tag = &sc->sc_i2c;
- config_found_ia(sc->sc_dev, "i2cbus", &iba, iicbus_print);
+ imxi2c_attach_common(parent, self,
+ aa->aa_iot, aa->aa_addr, aa->aa_size, aa->aa_irq, 0);
}
Index: src/sys/arch/arm/imx/imxi2c.c
diff -u src/sys/arch/arm/imx/imxi2c.c:1.1 src/sys/arch/arm/imx/imxi2c.c:1.2
--- src/sys/arch/arm/imx/imxi2c.c:1.1 Fri Jul 25 07:07:47 2014
+++ src/sys/arch/arm/imx/imxi2c.c Fri Mar 27 05:31:23 2015
@@ -1,7 +1,7 @@
-/* $NetBSD: imxi2c.c,v 1.1 2014/07/25 07:07:47 hkenken Exp $ */
+/* $NetBSD: imxi2c.c,v 1.2 2015/03/27 05:31:23 hkenken Exp $ */
/*
- * Copyright (c) 2012 Genetec Corporation. All rights reserved.
+ * Copyright (c) 2012, 2015 Genetec Corporation. All rights reserved.
* Written by Hashimoto Kenichi for Genetec Corporation.
*
* Redistribution and use in source and binary forms, with or without
@@ -27,44 +27,24 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: imxi2c.c,v 1.1 2014/07/25 07:07:47 hkenken Exp $");
+__KERNEL_RCSID(0, "$NetBSD: imxi2c.c,v 1.2 2015/03/27 05:31:23 hkenken Exp $");
#include "opt_imx.h"
#include <sys/param.h>
#include <sys/bus.h>
#include <sys/device.h>
-#include <sys/kernel.h>
-#include <sys/systm.h>
-#include <sys/mutex.h>
-#include <dev/i2c/i2cvar.h>
-#include <arm/imx/imxi2creg.h>
+#include <dev/i2c/motoi2cvar.h>
+#include <dev/i2c/motoi2creg.h>
#include <arm/imx/imxi2cvar.h>
-#include <arm/imx/imx51_ccmvar.h>
-
-#define I2C_READ(sc, reg) \
- bus_space_read_2((sc)->sc_iot, (sc)->sc_ioh, reg)
-#define I2C_WRITE(sc, reg, val) \
- bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, reg, val)
-
-#define I2C_TIMEOUT 1000 /* protocol timeout, in uSecs */
-
-static int imxi2c_i2c_acquire_bus(void *, int);
-static void imxi2c_i2c_release_bus(void *, int);
-static int imxi2c_i2c_exec(void *, u_int, u_int16_t, const void *, size_t, void *,
- size_t, int);
-
-static int imxi2c_wait(struct imxi2c_softc *, int);
-static int imxi2c_wait_bus(struct imxi2c_softc *, int);
-
struct clk_div {
uint8_t ic_val;
int div;
};
-static const struct clk_div i2c_clk_div[] = {
+static const struct clk_div imxi2c_clk_div[] = {
{0x20, 22}, {0x21, 24}, {0x22, 26}, {0x23, 28},
{0x00, 30}, {0x01, 32}, {0x24, 32}, {0x02, 36},
{0x25, 36}, {0x26, 40}, {0x03, 42}, {0x27, 44},
@@ -86,41 +66,48 @@ static const struct clk_div i2c_clk_div[
CFATTACH_DECL_NEW(imxi2c, sizeof(struct imxi2c_softc),
imxi2c_match, imxi2c_attach, NULL, NULL);
+static uint8_t
+imxi2c_iord1(struct motoi2c_softc *sc, bus_size_t off)
+{
+ if (off < I2CDFSRR)
+ return bus_space_read_2(sc->sc_iot, sc->sc_ioh, off) & 0xff;
+ else
+ return 0;
+}
+
+static void
+imxi2c_iowr1(struct motoi2c_softc *sc, bus_size_t off, uint8_t data)
+{
+ if (off < I2CDFSRR)
+ bus_space_write_2(sc->sc_iot, sc->sc_ioh, off, data);
+}
+
int
imxi2c_attach_common(device_t parent, device_t self,
bus_space_tag_t iot, paddr_t iobase, size_t size, int intr, int flags)
{
struct imxi2c_softc *sc = device_private(self);
- struct i2cbus_attach_args iba;
+ struct motoi2c_softc *msc = &sc->sc_motoi2c;
int error;
- aprint_normal(": i.MX IIC bus controller\n");
+ aprint_naive("\n");
+ aprint_normal("\n");
sc->sc_dev = self;
- sc->sc_iot = iot;
- if (size <= 0)
- size = I2C_SIZE;
- error = bus_space_map(sc->sc_iot, iobase, size, 0, &sc->sc_ioh);
+ msc->sc_iot = iot;
+ error = bus_space_map(msc->sc_iot, iobase, size, 0, &msc->sc_ioh);
if (error) {
aprint_error_dev(sc->sc_dev,
"failed to map registers (errno=%d)\n", error);
return 1;
}
- mutex_init(&sc->sc_buslock, MUTEX_DEFAULT, IPL_NONE);
-
- sc->sc_i2c.ic_cookie = sc;
- sc->sc_i2c.ic_acquire_bus = imxi2c_i2c_acquire_bus;
- sc->sc_i2c.ic_release_bus = imxi2c_i2c_release_bus;
- sc->sc_i2c.ic_send_start = NULL;
- sc->sc_i2c.ic_send_stop = NULL;
- sc->sc_i2c.ic_initiate_xfer = NULL;
- sc->sc_i2c.ic_read_byte = NULL;
- sc->sc_i2c.ic_write_byte = NULL;
- sc->sc_i2c.ic_exec = imxi2c_i2c_exec;
+ sc->sc_motoi2c_settings.i2c_adr = MOTOI2C_ADR_DEFAULT;
+ sc->sc_motoi2c_settings.i2c_dfsrr = MOTOI2C_DFSRR_DEFAULT;
+ msc->sc_iord = imxi2c_iord1;
+ msc->sc_iowr = imxi2c_iowr1;
- memset(&iba, 0, sizeof(iba));
- iba.iba_tag = &sc->sc_i2c;
+ motoi2c_attach_common(self, msc, &sc->sc_motoi2c_settings);
return 0;
}
@@ -132,181 +119,17 @@ imxi2c_set_freq(device_t self, long freq
bool found = false;
int index;
- for (index = 0; index < __arraycount(i2c_clk_div); index++) {
- if (freq / i2c_clk_div[index].div < speed) {
+ for (index = 0; index < __arraycount(imxi2c_clk_div); index++) {
+ if (freq / imxi2c_clk_div[index].div < speed) {
found = true;
break;
}
}
if (found == false)
- I2C_WRITE(sc, I2C_IFDR, 0x1f);
+ sc->sc_motoi2c_settings.i2c_fdr = 0x1f;
else
- I2C_WRITE(sc, I2C_IFDR, i2c_clk_div[index].ic_val);
+ sc->sc_motoi2c_settings.i2c_fdr = imxi2c_clk_div[index].ic_val;
return 0;
}
-
-
-static int
-imxi2c_wait(struct imxi2c_softc *sc, int flags)
-{
- for (int i = I2C_TIMEOUT; i >= 0; --i) {
- uint16_t sr = I2C_READ(sc, I2C_I2SR);
- if (sr & I2SR_IIF) {
- I2C_WRITE(sc, I2C_I2SR, 0);
- if (sr & I2SR_IAL)
- return EIO;
- if ((sr & I2SR_ICF) == 0)
- return EIO;
- if ((flags & I2C_F_READ) == 0 && (sr & I2SR_RXAK))
- return EIO;
- return 0;
- }
- delay(1);
- }
-
- return ETIMEDOUT;
-}
-
-static int
-imxi2c_wait_bus(struct imxi2c_softc *sc, int status)
-{
- for (int i = I2C_TIMEOUT; i >= 0; --i) {
- uint16_t sr = I2C_READ(sc, I2C_I2SR);
- if ((sr & I2SR_IBB) == status)
- return 0;
- delay(1);
- }
-
- return ETIMEDOUT;
-}
-
-static int
-imxi2c_i2c_acquire_bus(void *cookie, int flags)
-{
- struct imxi2c_softc *sc = cookie;
-
- mutex_enter(&sc->sc_buslock);
- return 0;
-}
-
-static void
-imxi2c_i2c_release_bus(void *cookie, int flags)
-{
- struct imxi2c_softc *sc = cookie;
-
- mutex_exit(&sc->sc_buslock);
- return;
-}
-
-static int
-imxi2c_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *vcmd,
- size_t cmdlen, void *vbuf, size_t buflen, int flags)
-{
- struct imxi2c_softc *sc = cookie;
- const uint8_t *cmdbuf = vcmd;
- uint8_t *buf = vbuf;
- int err = 0;
- size_t len;
- uint16_t val;
-
- /* Clear the bus. */
- I2C_WRITE(sc, I2C_I2SR, 0);
- I2C_WRITE(sc, I2C_I2CR, I2CR_IEN);
- err = imxi2c_wait_bus(sc, 0);
- if (err)
- return err;
-
- if (cmdlen > 0) {
- I2C_WRITE(sc, I2C_I2CR, I2CR_IEN | I2CR_MSTA | I2CR_MTX);
- err = imxi2c_wait_bus(sc, I2SR_IBB);
- if (err)
- goto out;
- I2C_WRITE(sc, I2C_I2DR, addr<<1);
- err = imxi2c_wait(sc, I2C_F_WRITE);
- if (err)
- goto out;
- len = cmdlen;
- while (len--) {
- I2C_WRITE(sc, I2C_I2DR, *cmdbuf++);
- err = imxi2c_wait(sc, I2C_F_WRITE);
- if (err)
- goto out;
- }
- }
-
- if (I2C_OP_READ_P(op) && buflen > 0) {
- /* RESTART if we did write a command above. */
- val = I2CR_IEN | I2CR_MSTA | I2CR_MTX;
- if (cmdlen > 0)
- val |= I2CR_RSTA;
- I2C_WRITE(sc, I2C_I2CR, val);
- err = imxi2c_wait_bus(sc, I2SR_IBB);
- if (err)
- goto out;
- I2C_WRITE(sc, I2C_I2DR, addr<<1 | 0x1);
- err = imxi2c_wait(sc, I2C_F_WRITE);
- if (err)
- goto out;
-
- /* NACK if we're only sending one byte. */
- val = I2CR_IEN | I2CR_MSTA;
- if (buflen == 1)
- val |= I2CR_TXAK;
- I2C_WRITE(sc, I2C_I2CR, val);
-
- /* Dummy read. */
- I2C_READ(sc, I2C_I2DR);
-
- len = buflen;
- while (len--) {
- err = imxi2c_wait(sc, I2C_F_READ);
- if (err)
- goto out;
-
- if (len == 1) {
- /* NACK on last byte. */
- val = I2CR_IEN | I2CR_MSTA | I2CR_TXAK;
- I2C_WRITE(sc, I2C_I2CR, val);
- } else if (len == 0) {
- /* STOP after last byte. */
- val = I2CR_IEN | I2CR_TXAK;
- I2C_WRITE(sc, I2C_I2CR, val);
- }
- *buf++ = I2C_READ(sc, I2C_I2DR);
- }
- }
-
- if (I2C_OP_WRITE_P(op) && cmdlen == 0 && buflen > 0) {
- /* START if we didn't write a command. */
- I2C_WRITE(sc, I2C_I2CR, I2CR_IEN | I2CR_MSTA | I2CR_MTX);
- err = imxi2c_wait_bus(sc, I2SR_IBB);
- if (err)
- goto out;
- I2C_WRITE(sc, I2C_I2DR, addr<<1);
- err = imxi2c_wait(sc, I2C_F_WRITE);
- if (err)
- goto out;
- }
-
- if (I2C_OP_WRITE_P(op) && buflen > 0) {
- len = buflen;
- while (len--) {
- I2C_WRITE(sc, I2C_I2DR, *buf++);
- err = imxi2c_wait(sc, I2C_F_WRITE);
- if (err)
- goto out;
- }
- }
-
-out:
- if (err)
- printf("%s: i2c bus error\n", __func__);
-
- /* STOP if we're still holding the bus. */
- I2C_WRITE(sc, I2C_I2CR, I2CR_IEN);
- imxi2c_wait_bus(sc, 0);
-
- return err;
-}
Index: src/sys/arch/arm/imx/imxi2cvar.h
diff -u src/sys/arch/arm/imx/imxi2cvar.h:1.1 src/sys/arch/arm/imx/imxi2cvar.h:1.2
--- src/sys/arch/arm/imx/imxi2cvar.h:1.1 Fri Jul 25 07:07:47 2014
+++ src/sys/arch/arm/imx/imxi2cvar.h Fri Mar 27 05:31:23 2015
@@ -1,7 +1,7 @@
-/* $NetBSD: imxi2cvar.h,v 1.1 2014/07/25 07:07:47 hkenken Exp $ */
+/* $NetBSD: imxi2cvar.h,v 1.2 2015/03/27 05:31:23 hkenken Exp $ */
/*
-* Copyright (c) 2012 Genetec Corporation. All rights reserved.
+* Copyright (c) 2012, 2015 Genetec Corporation. All rights reserved.
* Written by Hashimoto Kenichi for Genetec Corporation.
*
* Redistribution and use in source and binary forms, with or without
@@ -30,13 +30,12 @@
#define _IMXI2CVAR_H_
#include <dev/i2c/i2cvar.h>
+#include <dev/i2c/motoi2cvar.h>
struct imxi2c_softc {
device_t sc_dev;
- bus_space_tag_t sc_iot;
- bus_space_handle_t sc_ioh;
- struct i2c_controller sc_i2c;
- kmutex_t sc_buslock;
+ struct motoi2c_softc sc_motoi2c;
+ struct motoi2c_settings sc_motoi2c_settings;
};
int imxi2c_attach_common(device_t, device_t,
Index: src/sys/arch/arm/imx/imx51reg.h
diff -u src/sys/arch/arm/imx/imx51reg.h:1.5 src/sys/arch/arm/imx/imx51reg.h:1.6
--- src/sys/arch/arm/imx/imx51reg.h:1.5 Fri Jul 25 07:49:56 2014
+++ src/sys/arch/arm/imx/imx51reg.h Fri Mar 27 05:31:23 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: imx51reg.h,v 1.5 2014/07/25 07:49:56 hkenken Exp $ */
+/* $NetBSD: imx51reg.h,v 1.6 2015/03/27 05:31:23 hkenken Exp $ */
/*-
* Copyright (c) 2007 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -381,7 +381,7 @@
#define I2C1_BASE (AIPSTZ2_BASE + 0x03fc8000)
#define I2C2_BASE (AIPSTZ2_BASE + 0x03fc4000)
-/* register definitions in imxi2creg.h */
+#define I2C_SIZE 0x4000
#define AUDMUX_BASE (AIPSTZ2_BASE + 0x03fd0000)
#define AUDMUX_SIZE 0x4000
Index: src/sys/arch/arm/imx/imx6_reg.h
diff -u src/sys/arch/arm/imx/imx6_reg.h:1.3 src/sys/arch/arm/imx/imx6_reg.h:1.4
--- src/sys/arch/arm/imx/imx6_reg.h:1.3 Mon Oct 6 10:15:40 2014
+++ src/sys/arch/arm/imx/imx6_reg.h Fri Mar 27 05:31:23 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: imx6_reg.h,v 1.3 2014/10/06 10:15:40 ryo Exp $ */
+/* $NetBSD: imx6_reg.h,v 1.4 2015/03/27 05:31:23 hkenken Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -197,9 +197,12 @@
#define AIPS2_MMDC2_BASE 0x000b4000
#define AIPS2_MMDC1_BASE 0x000b0000
#define AIPS2_ROMCP_BASE 0x000ac000
+
#define AIPS2_I2C3_BASE 0x000a8000
#define AIPS2_I2C2_BASE 0x000a4000
#define AIPS2_I2C1_BASE 0x000a0000
+#define I2C_SIZE 0x4000
+
#define AIPS2_USDHC4_BASE 0x0009c000
#define AIPS2_USDHC3_BASE 0x00098000
#define AIPS2_USDHC2_BASE 0x00094000
