Module Name: src
Committed By: jmcneill
Date: Tue Mar 31 21:01:02 UTC 2015
Modified Files:
src/sys/dev/mii: rgephy.c rgephyreg.h
Log Message:
when resetting RTL8211F, make sure to disable manual MDI mode
To generate a diff of this commit:
cvs rdiff -u -r1.38 -r1.39 src/sys/dev/mii/rgephy.c
cvs rdiff -u -r1.7 -r1.8 src/sys/dev/mii/rgephyreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/mii/rgephy.c
diff -u src/sys/dev/mii/rgephy.c:1.38 src/sys/dev/mii/rgephy.c:1.39
--- src/sys/dev/mii/rgephy.c:1.38 Wed Mar 4 18:21:00 2015
+++ src/sys/dev/mii/rgephy.c Tue Mar 31 21:01:02 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: rgephy.c,v 1.38 2015/03/04 18:21:00 jmcneill Exp $ */
+/* $NetBSD: rgephy.c,v 1.39 2015/03/31 21:01:02 jmcneill Exp $ */
/*
* Copyright (c) 2003
@@ -33,7 +33,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: rgephy.c,v 1.38 2015/03/04 18:21:00 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rgephy.c,v 1.39 2015/03/31 21:01:02 jmcneill Exp $");
/*
@@ -619,7 +619,7 @@ rgephy_load_dspcode(struct mii_softc *sc
static void
rgephy_reset(struct mii_softc *sc)
{
- uint16_t ssr;
+ uint16_t ssr, phycr1;
mii_phy_reset(sc);
DELAY(1000);
@@ -634,6 +634,13 @@ rgephy_reset(struct mii_softc *sc)
ssr &= ~RGEPHY_SSR_ALDPS;
PHY_WRITE(sc, RGEPHY_MII_SSR, ssr);
}
+ } else if (sc->mii_mpd_rev == 6) {
+ /* RTL8211F */
+ phycr1 = PHY_READ(sc, RGEPHY_MII_PHYCR1);
+ if ((phycr1 & RGEPHY_PHYCR1_MDI_MMCE) != 0) {
+ phycr1 &= ~RGEPHY_PHYCR1_MDI_MMCE;
+ PHY_WRITE(sc, RGEPHY_MII_PHYCR1, phycr1);
+ }
} else {
PHY_WRITE(sc, 0x1F, 0x0000);
PHY_WRITE(sc, 0x0e, 0x0000);
Index: src/sys/dev/mii/rgephyreg.h
diff -u src/sys/dev/mii/rgephyreg.h:1.7 src/sys/dev/mii/rgephyreg.h:1.8
--- src/sys/dev/mii/rgephyreg.h:1.7 Wed Mar 4 18:21:00 2015
+++ src/sys/dev/mii/rgephyreg.h Tue Mar 31 21:01:02 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: rgephyreg.h,v 1.7 2015/03/04 18:21:00 jmcneill Exp $ */
+/* $NetBSD: rgephyreg.h,v 1.8 2015/03/31 21:01:02 jmcneill Exp $ */
/*
* Copyright (c) 2003
@@ -56,6 +56,9 @@
#define RGEPHY_SSR_JABBER 0x0001 /* Jabber */
/* RTL8211F */
+#define RGEPHY_MII_PHYCR1 0x18 /* PHY Specific control register 1 */
+#define RGEPHY_PHYCR1_MDI_MMCE __BIT(9)
+
#define RGEPHY_MII_PHYSR 0x1a /* PHY Specific status register */
#define RGEPHY_PHYSR_ALDPS __BIT(14)
#define RGEPHY_PHYSR_MDI_PLUG __BIT(13)
