Module Name: src
Committed By: macallan
Date: Sat Apr 4 13:06:01 UTC 2015
Modified Files:
src/sys/arch/evbmips/ingenic: intr.c machdep.c mainbus.c
Log Message:
add IPI support
compile-tested only since we don't actually spin up the 2nd core yet
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/evbmips/ingenic/intr.c
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/evbmips/ingenic/machdep.c
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/evbmips/ingenic/mainbus.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/evbmips/ingenic/intr.c
diff -u src/sys/arch/evbmips/ingenic/intr.c:1.8 src/sys/arch/evbmips/ingenic/intr.c:1.9
--- src/sys/arch/evbmips/ingenic/intr.c:1.8 Sat Mar 28 16:57:23 2015
+++ src/sys/arch/evbmips/ingenic/intr.c Sat Apr 4 13:06:01 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: intr.c,v 1.8 2015/03/28 16:57:23 macallan Exp $ */
+/* $NetBSD: intr.c,v 1.9 2015/04/04 13:06:01 macallan Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.8 2015/03/28 16:57:23 macallan Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.9 2015/04/04 13:06:01 macallan Exp $");
#define __INTR_PRIVATE
@@ -121,7 +121,7 @@ evbmips_intr_init(void)
/* allow peripheral interrupts to core 0 only */
reg = MFC0(12, 4); /* reset entry and interrupts */
reg &= 0xffff0000;
- reg |= REIM_IRQ0_M | REIM_MIRQ0_M | REIM_MIRQ1_M;
+ reg |= REIM_IRQ0_M | REIM_MIRQ0_M;
MTC0(reg, 12, 4);
}
@@ -149,7 +149,6 @@ evbmips_iointr(int ipl, vaddr_t pc, uint
if (ipending & MIPS_INT_MASK_1) {
/*
* this is a mailbox interrupt / IPI
- * for now just print the message and clear it
*/
uint32_t reg;
@@ -157,26 +156,34 @@ evbmips_iointr(int ipl, vaddr_t pc, uint
reg = MFC0(12, 3);
if (id == 0) {
if (reg & CS_MIRQ0_P) {
+#ifdef MULTIPROCESSOR
+ uint32_t tag;
+ tag = MFC0(CP0_CORE_MBOX, 0);
+ ipi_process(curcpu(), tag);
#ifdef INGENIC_INTR_DEBUG
snprintf(buffer, 256,
- "IPI for core 0, msg %08x\n",
- MFC0(CP0_CORE_MBOX, 0));
+ "IPI for core 0, msg %08x\n", tag);
ingenic_puts(buffer);
#endif
+#endif
reg &= (~CS_MIRQ0_P);
/* clear it */
MTC0(reg, 12, 3);
}
} else if (id == 1) {
if (reg & CS_MIRQ1_P) {
+#ifdef MULTIPROCESSOR
+ uint32_t tag;
+ tag = MFC0(CP0_CORE_MBOX, 1);
+ ipi_process(curcpu(), tag);
#ifdef INGENIC_INTR_DEBUG
snprintf(buffer, 256,
- "IPI for core 1, msg %08x\n",
- MFC0(CP0_CORE_MBOX, 1));
+ "IPI for core 1, msg %08x\n", tag);
ingenic_puts(buffer);
#endif
- reg &= ( 7 - CS_MIRQ1_P);
+#endif
+ reg &= (~CS_MIRQ1_P);
/* clear it */
MTC0(reg, 12, 3);
}
Index: src/sys/arch/evbmips/ingenic/machdep.c
diff -u src/sys/arch/evbmips/ingenic/machdep.c:1.5 src/sys/arch/evbmips/ingenic/machdep.c:1.6
--- src/sys/arch/evbmips/ingenic/machdep.c:1.5 Tue Mar 10 22:39:38 2015
+++ src/sys/arch/evbmips/ingenic/machdep.c Sat Apr 4 13:06:01 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: machdep.c,v 1.5 2015/03/10 22:39:38 macallan Exp $ */
+/* $NetBSD: machdep.c,v 1.6 2015/04/04 13:06:01 macallan Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.5 2015/03/10 22:39:38 macallan Exp $");
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.6 2015/04/04 13:06:01 macallan Exp $");
#include "opt_ddb.h"
#include "opt_kgdb.h"
@@ -115,6 +115,40 @@ cal_timer(void)
do {} while (junk == readreg(JZ_OST_CNT_LO));
}
+#ifdef MULTIPROCESSOR
+static void
+ingenic_cpu_init(struct cpu_info *ci)
+{
+ uint32_t reg;
+
+ /* enable IPIs for this core */
+ reg = MFC0(12, 4); /* reset entry and interrupts */
+ reg &= 0xffff0000;
+ if (cpu_index(ci) == 1) {
+ reg |= REIM_MIRQ1_M;
+ } else
+ reg |= REIM_MIRQ0_M;
+ MTC0(reg, 12, 4);
+}
+
+static int
+ingenic_send_ipi(struct cpu_info *ci, int tag)
+{
+ uint32_t msg;
+
+ msg = 1 << tag;
+
+ if (cpus_running & (1 << cpu_index(ci))) {
+ if (cpu_index(ci) == 0) {
+ MTC0(msg, CP0_CORE_MBOX, 0);
+ } else {
+ MTC0(msg, CP0_CORE_MBOX, 1);
+ }
+ }
+ return 0;
+}
+#endif
+
void
mach_init(void)
{
@@ -154,7 +188,11 @@ mach_init(void)
printf("Memory size: 0x%08x\n", memsize);
physmem = btoc(memsize);
- /* XXX this is CI20 specific */
+ /*
+ * memory is at 0x20000000 with first 256MB mirrored to 0x00000000 so
+ * we can see them through KSEG*
+ * assume 1GB for now, the SoC can theoretically support up to 3GB
+ */
mem_clusters[0].start = PAGE_SIZE;
mem_clusters[0].size = 0x10000000 - PAGE_SIZE;
mem_clusters[1].start = 0x30000000;
@@ -182,6 +220,11 @@ mach_init(void)
*/
mips_init_lwp0_uarea();
+#ifdef MULTIPROCESSOR
+ mips_locoresw.lsw_send_ipi = ingenic_send_ipi;
+ mips_locoresw.lsw_cpu_init = ingenic_cpu_init;
+#endif
+
apbus_init();
/*
* Initialize debuggers, and break into them, if appropriate.
Index: src/sys/arch/evbmips/ingenic/mainbus.c
diff -u src/sys/arch/evbmips/ingenic/mainbus.c:1.3 src/sys/arch/evbmips/ingenic/mainbus.c:1.4
--- src/sys/arch/evbmips/ingenic/mainbus.c:1.3 Tue Dec 23 15:09:13 2014
+++ src/sys/arch/evbmips/ingenic/mainbus.c Sat Apr 4 13:06:01 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: mainbus.c,v 1.3 2014/12/23 15:09:13 macallan Exp $ */
+/* $NetBSD: mainbus.c,v 1.4 2015/04/04 13:06:01 macallan Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.3 2014/12/23 15:09:13 macallan Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.4 2015/04/04 13:06:01 macallan Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -93,6 +93,10 @@ mainbus_attach(device_t parent, device_t
/* send ourselves an IPI */
MTC0(0x12345678, CP0_CORE_MBOX, 0);
delay(1000);
+
+ /* send the other core an IPI */
+ MTC0(0x12345678, CP0_CORE_MBOX, 1);
+ delay(1000);
#endif
}
