Module Name: src
Committed By: palle
Date: Sun Apr 5 20:26:47 UTC 2015
Modified Files:
src/sys/arch/sparc64/sparc64: pmap.c
Log Message:
sun4v: Ensure that the W (Write) bit is not present in the TTEs unless for the
data mapping. This way the permanent mappings for the primary cpu done by
ofwboot are the same as the permanent mappings for the secondary cpus done by
the kernel. This should fix an issue when booting the kernel on a T2 based
system (T5120).
To generate a diff of this commit:
cvs rdiff -u -r1.292 -r1.293 src/sys/arch/sparc64/sparc64/pmap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/sparc64/sparc64/pmap.c
diff -u src/sys/arch/sparc64/sparc64/pmap.c:1.292 src/sys/arch/sparc64/sparc64/pmap.c:1.293
--- src/sys/arch/sparc64/sparc64/pmap.c:1.292 Tue Nov 4 18:11:42 2014
+++ src/sys/arch/sparc64/sparc64/pmap.c Sun Apr 5 20:26:47 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.c,v 1.292 2014/11/04 18:11:42 palle Exp $ */
+/* $NetBSD: pmap.c,v 1.293 2015/04/05 20:26:47 palle Exp $ */
/*
*
* Copyright (C) 1996-1999 Eduardo Horvath.
@@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.292 2014/11/04 18:11:42 palle Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.293 2015/04/05 20:26:47 palle Exp $");
#undef NO_VCACHE /* Don't forget the locked TLB in dostart */
#define HWREF
@@ -535,14 +535,25 @@ pmap_mp_init(void)
PGSZ_4M, /* sz */
kernel_tlbs[i].te_pa, /* pa */
1, /* priv */
- 1, /* write */
+ 0, /* write */
1, /* cache */
1, /* aliased */
1, /* valid */
0 /* ie */);
tp[i].data |= TLB_L | TLB_CV;
- if (CPU_ISSUN4V)
- tp[i].data |= SUN4V_TLB_X;
+
+ /*
+ * Assuming that the last tlb slot entry is the only data slot.
+ *
+ * If more than one data slot is required on day, perhaps
+ * the bootinfo structure shared between ofwboot and the kernel
+ * should be expanded to include the number of data slots.
+ */
+ if (i == kernel_tlb_slots-1)
+ tp[i].data |= TLB_W;
+ else
+ if (CPU_ISSUN4V)
+ tp[i].data |= SUN4V_TLB_X;
DPRINTF(PDB_BOOT1, ("xtlb[%d]: Tag: %" PRIx64 " Data: %"
PRIx64 "\n", i, tp[i].tag, tp[i].data));
