Module Name: src
Committed By: hsuenaga
Date: Wed Apr 15 10:52:19 UTC 2015
Modified Files:
src/sys/arch/arm/arm: cpufunc.c cpufunc_asm_pj4b.S
src/sys/arch/arm/include: cpufunc_proto.h
Log Message:
clean up cpufuncs of CPU_PJ4B.
PJ4B is a ARMv7 compatible CPU, so most of cpufuncs are just redundant.
we need funcs for:
- Marvell specific registers
- workaround of errata
- and Marvell specific L2 cache maintainance
if I/O coherency fabric is enabled(option AURORA_IO_CACHE_COHERENCY),
probaly we don't need to maintain L2 cache by software.
To generate a diff of this commit:
cvs rdiff -u -r1.151 -r1.152 src/sys/arch/arm/arm/cpufunc.c
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/arm/arm/cpufunc_asm_pj4b.S
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/include/cpufunc_proto.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/cpufunc.c
diff -u src/sys/arch/arm/arm/cpufunc.c:1.151 src/sys/arch/arm/arm/cpufunc.c:1.152
--- src/sys/arch/arm/arm/cpufunc.c:1.151 Wed Feb 25 13:52:42 2015
+++ src/sys/arch/arm/arm/cpufunc.c Wed Apr 15 10:52:18 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.c,v 1.151 2015/02/25 13:52:42 joerg Exp $ */
+/* $NetBSD: cpufunc.c,v 1.152 2015/04/15 10:52:18 hsuenaga Exp $ */
/*
* arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -49,7 +49,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.151 2015/02/25 13:52:42 joerg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.152 2015/04/15 10:52:18 hsuenaga Exp $");
#include "opt_compat_netbsd.h"
#include "opt_cpuoptions.h"
@@ -88,6 +88,16 @@ __KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v
#include <arm/xscale/xscalereg.h>
#endif
+#if defined(CPU_PJ4B)
+#include "opt_cputypes.h"
+#include "opt_mvsoc.h"
+#include <machine/bus_defs.h>
+#if defined(ARMADAXP)
+#include <arm/marvell/armadaxpreg.h>
+#include <arm/marvell/armadaxpvar.h>
+#endif
+#endif
+
#if defined(PERFCTRS)
struct arm_pmc_funcs *arm_pmc;
#endif
@@ -1342,57 +1352,63 @@ struct cpu_functions pj4bv7_cpufuncs = {
/* CPU functions */
.cf_id = cpufunc_id,
- .cf_cpwait = pj4b_drain_writebuf,
+ .cf_cpwait = armv7_drain_writebuf,
/* MMU functions */
.cf_control = cpufunc_control,
.cf_domains = cpufunc_domains,
- .cf_setttb = pj4b_setttb,
+ .cf_setttb = armv7_setttb,
.cf_faultstatus = cpufunc_faultstatus,
.cf_faultaddress = cpufunc_faultaddress,
/* TLB functions */
- .cf_tlb_flushID = pj4b_tlb_flushID,
- .cf_tlb_flushID_SE = pj4b_tlb_flushID_SE,
- .cf_tlb_flushI = pj4b_tlb_flushID,
- .cf_tlb_flushI_SE = pj4b_tlb_flushID_SE,
- .cf_tlb_flushD = pj4b_tlb_flushID,
- .cf_tlb_flushD_SE = pj4b_tlb_flushID_SE,
+ .cf_tlb_flushID = armv7_tlb_flushID,
+ .cf_tlb_flushID_SE = armv7_tlb_flushID_SE,
+ .cf_tlb_flushI = armv7_tlb_flushID,
+ .cf_tlb_flushI_SE = armv7_tlb_flushID_SE,
+ .cf_tlb_flushD = armv7_tlb_flushID,
+ .cf_tlb_flushD_SE = armv7_tlb_flushID_SE,
/* Cache operations */
.cf_icache_sync_all = armv7_idcache_wbinv_all,
- .cf_icache_sync_range = pj4b_icache_sync_range,
+ .cf_icache_sync_range = armv7_icache_sync_range,
.cf_dcache_wbinv_all = armv7_dcache_wbinv_all,
- .cf_dcache_wbinv_range = pj4b_dcache_wbinv_range,
- .cf_dcache_inv_range = pj4b_dcache_inv_range,
- .cf_dcache_wb_range = pj4b_dcache_wb_range,
+ .cf_dcache_wbinv_range = armv7_dcache_wbinv_range,
+ .cf_dcache_inv_range = armv7_dcache_inv_range,
+ .cf_dcache_wb_range = armv7_dcache_wb_range,
+#if !defined(AURORA_IO_CACHE_COHERENCY) && defined(ARMADAXP)
+ .cf_sdcache_wbinv_range = armadaxp_sdcache_wbinv_range,
+ .cf_sdcache_inv_range = armadaxp_sdcache_inv_range,
+ .cf_sdcache_wb_range = armadaxp_sdcache_wb_range,
+#else
.cf_sdcache_wbinv_range = (void *)cpufunc_nullop,
.cf_sdcache_inv_range = (void *)cpufunc_nullop,
.cf_sdcache_wb_range = (void *)cpufunc_nullop,
+#endif
.cf_idcache_wbinv_all = armv7_idcache_wbinv_all,
- .cf_idcache_wbinv_range = pj4b_idcache_wbinv_range,
+ .cf_idcache_wbinv_range = armv7_idcache_wbinv_range,
/* Other functions */
- .cf_flush_prefetchbuf = pj4b_drain_readbuf,
- .cf_drain_writebuf = pj4b_drain_writebuf,
- .cf_flush_brnchtgt_C = pj4b_flush_brnchtgt_all,
- .cf_flush_brnchtgt_E = pj4b_flush_brnchtgt_va,
+ .cf_flush_prefetchbuf = cpufunc_nullop,
+ .cf_drain_writebuf = armv7_drain_writebuf,
+ .cf_flush_brnchtgt_C = cpufunc_nullop,
+ .cf_flush_brnchtgt_E = (void *)cpufunc_nullop,
- .cf_sleep = (void *)cpufunc_nullop,
+ .cf_sleep = pj4b_cpu_sleep,
/* Soft functions */
.cf_dataabt_fixup = cpufunc_null_fixup,
.cf_prefetchabt_fixup = cpufunc_null_fixup,
- .cf_context_switch = pj4b_context_switch,
+ .cf_context_switch = armv7_context_switch,
.cf_setup = pj4bv7_setup
};
Index: src/sys/arch/arm/arm/cpufunc_asm_pj4b.S
diff -u src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.6 src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.7
--- src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.6 Thu Mar 26 08:50:42 2015
+++ src/sys/arch/arm/arm/cpufunc_asm_pj4b.S Wed Apr 15 10:52:18 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_pj4b.S,v 1.6 2015/03/26 08:50:42 hsuenaga Exp $ */
+/* $NetBSD: cpufunc_asm_pj4b.S,v 1.7 2015/04/15 10:52:18 hsuenaga Exp $ */
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
@@ -41,189 +41,49 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBI
#include <arm/asm.h>
#include <arm/locore.h>
-#define TTB_RGN_OC_WB (3 << 3)
-#define TTB_IRGN_WB ((1 << 0) | (1 << 6))
-
-/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
-#define TTB_FLAGS_UP (TTB_IRGN_WB | TTB_RGN_OC_WB)
-
.Lpj4b_cache_line_size:
.word _C_LABEL(arm_dcache_align)
-ENTRY(pj4b_setttb)
- /* Cache synchronization is not required as this core has PIPT caches */
- dsb
-#if defined(L2CACHE_ENABLE) && defined(AURORA_L2_PT_WALK)
- orr r2, r0, #TTB_FLAGS_UP
-#else
- bic r2, r0, #0x18
-#endif
- mcr p15, 0, r2, c2, c0, 0 /* load TTBR0 */
-#ifdef ARM_MMU_EXTENDED
- cmp r1, #0
- mcreq p15, 0, r2, c2, c0, 1 /* load TTBR1 */
-#else
- mov r0, #0
- mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
-#endif
- isb
- dsb
- RET
-END(pj4b_setttb)
-
-ENTRY(pj4b_tlb_flushID)
- mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
- dsb
- RET
-END(pj4b_tlb_flushID)
-
-ENTRY(pj4b_tlb_flushID_SE)
- bfc r0, #0, #12 @ always KERNEL_PID (i.e. 0)
- mcr p15, 0, r0, c8, c7, 1 @flush I+D tlb single entry
-#if PAGE_SIZE == 2 * L2_S_SIZE
- add r0, r0, L2_S_SIZE
- mcr p15, 0, r0, c8, c7, 1 @flush I+D tlb single entry
-#endif
- dsb
- RET
-END(pj4b_tlb_flushID_SE)
-
-ENTRY(pj4b_icache_sync_range)
- ldr ip, .Lpj4b_cache_line_size
- ldr ip, [ip]
- sub r1, r1, #1 /* Don't overrun */
- sub r3, ip, #1
- and r2, r0, r3
- add r1, r1, r2
- bic r0, r0, r3
-1:
- mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
- mcr p15, 0, r0, c7, c14, 1 /* Clean and invalidate D cache SE with VA */
- add r0, r0, ip
- subs r1, r1, ip
- bpl 1b
- isb /* instruction synchronization barrier */
- dsb
- RET
-END(pj4b_icache_sync_range)
-
-ENTRY(pj4b_dcache_inv_range)
- ldr ip, .Lpj4b_cache_line_size
- ldr ip, [ip]
- sub r1, r1, #1 /* Don't overrun */
- sub r3, ip, #1
- and r2, r0, r3
- add r1, r1, r2
- bic r0, r0, r3
-1:
- mcr p15, 0, r0, c7, c6, 1
- add r0, r0, ip
- subs r1, r1, ip
- bpl 1b
+ENTRY(pj4b_cpu_sleep)
dsb
- RET
-END(pj4b_dcache_inv_range)
-
-ENTRY(pj4b_idcache_wbinv_range)
- ldr ip, .Lpj4b_cache_line_size
- ldr ip, [ip]
- sub r1, r1, #1 /* Don't overrun */
- sub r3, ip, #1
- and r2, r0, r3
- add r1, r1, r2
- bic r0, r0, r3
-1:
- mcr p15, 0, r0, c7, c5, 1
- mcr p15, 0, r0, c7, c14, 1 /* L2C clean and invalidate entry */
- add r0, r0, ip
- subs r1, r1, ip
- bpl 1b
- dsb
- RET
-END(pj4b_idcache_wbinv_range)
-
-ENTRY(pj4b_dcache_wbinv_range)
- ldr ip, .Lpj4b_cache_line_size
- ldr ip, [ip]
- sub r1, r1, #1 /* Don't overrun */
- sub r3, ip, #1
- and r2, r0, r3
- add r1, r1, r2
- bic r0, r0, r3
-1:
- mcr p15, 0, r0, c7, c14, 1
- add r0, r0, ip
- subs r1, r1, ip
- bpl 1b
- dsb
- RET
-END(pj4b_dcache_wbinv_range)
-
-ENTRY(pj4b_dcache_wb_range)
- ldr ip, .Lpj4b_cache_line_size
- ldr ip, [ip]
- sub r1, r1, #1 /* Don't overrun */
- sub r3, ip, #1
- and r2, r0, r3
- add r1, r1, r2
- bic r0, r0, r3
-1:
- mcr p15, 0, r0, c7, c14, 1 /* Clean and invalidate D cache SE with VA */
- add r0, r0, ip
- subs r1, r1, ip
- bpl 1b
- dsb
- RET
-END(pj4b_dcache_wb_range)
-
-ENTRY(pj4b_drain_readbuf)
- isb
- RET
-END(pj4b_drain_readbuf)
-
-ENTRY(pj4b_drain_writebuf)
- dsb
- RET
-END(pj4b_drain_writebuf)
-
-ENTRY(pj4b_flush_brnchtgt_all)
- mcr p15, 0, r0, c7, c5, 6 /* flush entrie branch target cache */
- RET
-END(pj4b_flush_brnchtgt_all)
-
-ENTRY(pj4b_flush_brnchtgt_va)
- mcr p15, 0, r0, c7, c5, 7 /* flush branch target cache by VA */
- RET
-END(pj4b_flush_brnchtgt_va)
-
-ENTRY(pj4b_context_switch)
- dsb
-#if defined(L2CACHE_ENABLE) && defined(AURORA_L2_PT_WALK)
- orr r2, r0, #TTB_FLAGS_UP
-#else
- bic r2, r0, #0x18
-#endif
- mcr p15, 0, r2, c2, c0, 0 @set the new TTBR0
-#ifdef ARM_MMU_EXTENDED
- cmp r1, #0
- mcreq p15, 0, r2, c2, c0, 1 @set the new TTBR1
-#else
- mov r0, #0
- mcr p15, 0, r0, c8, c7, 0 @flush the I+D
-#endif
- dsb
- isb
- RET
-END(pj4b_context_switch)
+ wfi @ wait for an interrupt
+ dsb @ Erratum#ARM-CPU-4742
+ b irq_idle_entry @ assume we got an interrupt
+END(pj4b_cpu_sleep)
ENTRY(pj4b_config)
+ /* Set Auxiliary Debug Modes Control 0 register */
+ mrc p15, 1, r0, c15, c1, 0
+ bic r0, r0, #(1 << 12) @ Erratum#ARM-CPU-6136
+ @ LDSTM 1st issue is single word
+ orr r0, r0, #(1 << 22) @ DVM_WAKEUP enable
+ mcr p15, 1, r0, c15, c1, 0
+
+ /* Set Auxiliary Debug Modes Control 1 register */
+ mrc p15, 1, r0, c15, c1, 1
+ bic r0, r0, #(1 << 2) @ Erratum#ARM-CPU-6409
+ @ Disable static branch prediction
+ orr r0, r0, #(1 << 5) @ STREX backoff disable
+ mcr p15, 1, r0, c15, c1, 1
+
/* Set Auxiliary Debug Modes Control 2 register */
mrc p15, 1, r0, c15, c1, 2
- bic r0, r0, #(1 << 23)
- orr r0, r0, #(1 << 25)
- orr r0, r0, #(1 << 27)
- orr r0, r0, #(1 << 29)
- orr r0, r0, #(1 << 30)
+ bic r0, r0, #(1 << 23) @ Enable fast LDR
+ orr r0, r0, #(1 << 25) @ Intervention Interleave disable
+ orr r0, r0, #(1 << 27) @ Critical word 1st sequencing dis.
+ orr r0, r0, #(1 << 29) @ Disable MO device R/W
+ orr r0, r0, #(1 << 30) @ L1 cache strict round-robin
+ orr r0, r0, #(1 << 31) @ Enable write evict
mcr p15, 1, r0, c15, c1, 2
+
+ /* Set Auxiliary FUnction Modes Control 0 register */
+ mrc p15, 1, r0, c15, c2, 0
+#ifdef MULTIPROCESSOR
+ orr r0, r0, #(1 << 1) @ SMP/nAMP enable
+#endif
+ orr r0, r0, #(1 << 2) @ L2 parity enable
+ orr r0, r0, #(1 << 8) @ Cache & TLB maintenance broadcast
+ mcr p15, 1, r0, c15, c2, 0
+
RET
END(pj4b_config)
Index: src/sys/arch/arm/include/cpufunc_proto.h
diff -u src/sys/arch/arm/include/cpufunc_proto.h:1.3 src/sys/arch/arm/include/cpufunc_proto.h:1.4
--- src/sys/arch/arm/include/cpufunc_proto.h:1.3 Sat Sep 13 17:41:03 2014
+++ src/sys/arch/arm/include/cpufunc_proto.h Wed Apr 15 10:52:18 2015
@@ -323,31 +323,9 @@ void armv7_setup(char *string);
#endif /* CPU_ARMV7 */
#if defined(CPU_PJ4B)
-#if defined(ARM_MMU_EXTENDED)
-void pj4b_setttb(u_int, tlb_asid_t);
-void pj4b_context_switch(u_int, tlb_asid_t);
-#else
-void pj4b_setttb(u_int, bool);
-void pj4b_context_switch(u_int);
-#endif
-void pj4b_tlb_flushID(void);
-void pj4b_tlb_flushID_SE(vaddr_t);
-
-void pj4b_icache_sync_range(vaddr_t, vsize_t);
-void pj4b_idcache_wbinv_range(vaddr_t, vsize_t);
-void pj4b_dcache_wbinv_range(vaddr_t, vsize_t);
-void pj4b_dcache_inv_range(vaddr_t, vsize_t);
-void pj4b_dcache_wb_range(vaddr_t, vsize_t);
-
-void pj4b_drain_writebuf(void);
-void pj4b_drain_readbuf(void);
-void pj4b_flush_brnchtgt_all(void);
-void pj4b_flush_brnchtgt_va(u_int);
-void pj4b_sleep(int);
-
+void pj4b_cpu_sleep(int);
void pj4bv7_setup(char *string);
void pj4b_config(void);
-
#endif /* CPU_PJ4B */
#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
