Module Name: src
Committed By: jmcneill
Date: Sun Apr 19 18:54:52 UTC 2015
Modified Files:
src/sys/arch/arm/amlogic: amlogic_board.c amlogic_crureg.h amlogic_io.c
amlogic_var.h files.amlogic
Added Files:
src/sys/arch/arm/amlogic: amlogic_sdio.c amlogic_sdioreg.h
Log Message:
Add a driver for Amlogic "SDIO" MMC controller.
To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/arm/amlogic/amlogic_board.c
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/arm/amlogic/amlogic_crureg.h
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/amlogic/amlogic_io.c \
src/sys/arch/arm/amlogic/amlogic_var.h
cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/amlogic/amlogic_sdio.c \
src/sys/arch/arm/amlogic/amlogic_sdioreg.h
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/arm/amlogic/files.amlogic
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/amlogic/amlogic_board.c
diff -u src/sys/arch/arm/amlogic/amlogic_board.c:1.11 src/sys/arch/arm/amlogic/amlogic_board.c:1.12
--- src/sys/arch/arm/amlogic/amlogic_board.c:1.11 Fri Apr 3 14:02:06 2015
+++ src/sys/arch/arm/amlogic/amlogic_board.c Sun Apr 19 18:54:52 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: amlogic_board.c,v 1.11 2015/04/03 14:02:06 jmcneill Exp $ */
+/* $NetBSD: amlogic_board.c,v 1.12 2015/04/19 18:54:52 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <[email protected]>
@@ -29,7 +29,7 @@
#include "opt_amlogic.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amlogic_board.c,v 1.11 2015/04/03 14:02:06 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amlogic_board.c,v 1.12 2015/04/19 18:54:52 jmcneill Exp $");
#define _ARM32_BUS_DMA_PRIVATE
#include <sys/param.h>
@@ -109,6 +109,31 @@ amlogic_get_rate_sys(void)
}
uint32_t
+amlogic_get_rate_clk81(void)
+{
+ uint32_t cc, rate;
+
+ rate = amlogic_get_rate_fixed();
+ cc = CBUS_READ(HHI_MPEG_CLK_CNTL_REG);
+
+ switch (__SHIFTOUT(cc, HHI_MPEG_CLK_CNTL_DIV_SRC)) {
+ case 7:
+ rate /= 5;
+ break;
+ case 6:
+ rate /= 3;
+ break;
+ case 5:
+ rate /= 4;
+ break;
+ default:
+ panic("CLK81: unknown rate, HHI_MPEG_CLK_CNTL_REG = %#x", cc);
+ }
+
+ return rate / (__SHIFTOUT(cc, HHI_MPEG_CLK_CNTL_DIV_N) + 1);
+}
+
+uint32_t
amlogic_get_rate_fixed(void)
{
uint32_t cntl;
@@ -216,6 +241,11 @@ amlogic_sdhc_select_port(int port)
CBUS_SET_CLEAR(PERIPHS_PIN_MUX_2_REG, 0, 0x0000fc00);
CBUS_SET_CLEAR(PERIPHS_PIN_MUX_8_REG, 0, 0x00000600);
CBUS_SET_CLEAR(PERIPHS_PIN_MUX_2_REG, 0x000000f0, 0);
+
+ /* XXX ODROID-C1 */
+ CBUS_SET_CLEAR(PREG_PAD_GPIO5_EN_N_REG, 0x20000000, 0);
+ CBUS_SET_CLEAR(PREG_PAD_GPIO5_OUT_REG, 0, 0x80000000);
+ CBUS_SET_CLEAR(PREG_PAD_GPIO5_EN_N_REG, 0, 0x80000000);
break;
case AMLOGIC_SDHC_PORT_C:
/* BOOT -> SDHC pin mux settings */
@@ -224,6 +254,93 @@ amlogic_sdhc_select_port(int port)
CBUS_SET_CLEAR(PERIPHS_PIN_MUX_6_REG, 0, 0xff000000);
CBUS_SET_CLEAR(PERIPHS_PIN_MUX_4_REG, 0x70000000, 0);
CBUS_SET_CLEAR(PERIPHS_PIN_MUX_7_REG, 0x000c0000, 0);
+
+ /* XXX ODROID-C1 */
+ CBUS_SET_CLEAR(PAD_PULL_UP_3_REG, 0, 0x000000ff);
+ break;
+ default:
+ return EINVAL;
+ }
+
+ return 0;
+}
+
+void
+amlogic_sdhc_reset_port(int port)
+{
+ switch (port) {
+ case AMLOGIC_SDHC_PORT_C:
+ CBUS_SET_CLEAR(PERIPHS_PIN_MUX_2_REG, 0, 0x01000000);
+ CBUS_SET_CLEAR(PREG_PAD_GPIO3_EN_N_REG, 0, 0x00000200);
+ CBUS_SET_CLEAR(PREG_PAD_GPIO3_OUT_REG, 0x00000200, 0);
+ delay(1000);
+ CBUS_SET_CLEAR(PREG_PAD_GPIO3_OUT_REG, 0, 0x00000200);
+ delay(2000);
+ CBUS_SET_CLEAR(PREG_PAD_GPIO3_OUT_REG, 0x00000200, 0);
+ delay(1000);
+ break;
+ }
+}
+
+bool
+amlogic_sdhc_is_removable(int port)
+{
+ switch (port) {
+ case AMLOGIC_SDHC_PORT_B:
+ return true;
+ default:
+ return false;
+ }
+}
+
+bool
+amlogic_sdhc_is_card_present(int port)
+{
+ switch (port) {
+ case AMLOGIC_SDHC_PORT_B:
+ /* GPIO CARD_6 */
+ return !(CBUS_READ(PREG_PAD_GPIO0_IN_REG) & __BIT(28));
+ default:
+ return true;
+ }
+}
+
+void
+amlogic_sdio_init(void)
+{
+ /* enable SDIO clk */
+ CBUS_WRITE(EE_CLK_GATING0_REG,
+ CBUS_READ(EE_CLK_GATING0_REG) | EE_CLK_GATING0_SDIO);
+
+ /* reset */
+ CBUS_SET_CLEAR(RESET6_REG, RESET6_SDIO, 0);
+}
+
+int
+amlogic_sdio_select_port(int port)
+{
+ switch (port) {
+ case AMLOGIC_SDIO_PORT_B:
+ /* CARD -> SDIO pin mux settings */
+ CBUS_SET_CLEAR(PERIPHS_PIN_MUX_6_REG, 0, 0x3f000000);
+ CBUS_SET_CLEAR(PERIPHS_PIN_MUX_8_REG, 0, 0x0000063f);
+ CBUS_SET_CLEAR(PERIPHS_PIN_MUX_2_REG, 0, 0x000000f0);
+ CBUS_SET_CLEAR(PERIPHS_PIN_MUX_2_REG, 0x0000fc00, 0);
+
+ /* XXX ODROID-C1 */
+ CBUS_SET_CLEAR(PREG_PAD_GPIO5_EN_N_REG, 0x20000000, 0);
+ CBUS_SET_CLEAR(PREG_PAD_GPIO5_OUT_REG, 0, 0x80000000);
+ CBUS_SET_CLEAR(PREG_PAD_GPIO5_EN_N_REG, 0, 0x80000000);
+ break;
+ case AMLOGIC_SDIO_PORT_C:
+ /* BOOT -> SDIO pin mux settings */
+ CBUS_SET_CLEAR(PERIPHS_PIN_MUX_2_REG, 0, 0x06c2fc00);
+ CBUS_SET_CLEAR(PERIPHS_PIN_MUX_8_REG, 0, 0x0000003f);
+ CBUS_SET_CLEAR(PERIPHS_PIN_MUX_4_REG, 0, 0x6c000000);
+ CBUS_SET_CLEAR(PERIPHS_PIN_MUX_6_REG, 0xfc000000, 0);
+
+ /* XXX ODROID-C1 */
+ CBUS_SET_CLEAR(PAD_PULL_UP_3_REG, 0, 0x000000ff);
break;
default:
return EINVAL;
@@ -292,7 +409,7 @@ amlogic_usbphy_init(int port)
}
if (port == 0) {
- CBUS_WRITE(RESET1_REG, RESET1_USB);
+ CBUS_SET_CLEAR(RESET1_REG, RESET1_USB, 0);
}
amlogic_usbphy_clkgate_enable(port);
Index: src/sys/arch/arm/amlogic/amlogic_crureg.h
diff -u src/sys/arch/arm/amlogic/amlogic_crureg.h:1.8 src/sys/arch/arm/amlogic/amlogic_crureg.h:1.9
--- src/sys/arch/arm/amlogic/amlogic_crureg.h:1.8 Fri Apr 3 14:02:06 2015
+++ src/sys/arch/arm/amlogic/amlogic_crureg.h Sun Apr 19 18:54:52 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: amlogic_crureg.h,v 1.8 2015/04/03 14:02:06 jmcneill Exp $ */
+/* $NetBSD: amlogic_crureg.h,v 1.9 2015/04/19 18:54:52 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <[email protected]>
@@ -54,6 +54,10 @@
#define HHI_SYS_CPU_CLK_CNTL1_SDIV __BITS(29,20)
#define HHI_SYS_CPU_CLK_CNTL1_PERIPH_CLK_MUX __BITS(8,6)
+#define HHI_MPEG_CLK_CNTL_REG CBUS_REG(0x105d)
+#define HHI_MPEG_CLK_CNTL_DIV_SRC __BITS(14,12)
+#define HHI_MPEG_CLK_CNTL_DIV_N __BITS(5,0)
+
#define HHI_SYS_CPU_CLK_CNTL0_REG CBUS_REG(0x1067)
#define HHI_SYS_CPU_CLK_CNTL0_CLKSEL __BIT(7)
#define HHI_SYS_CPU_CLK_CNTL0_SOUTSEL __BITS(3,2)
@@ -72,10 +76,25 @@
#define RESET1_REG CBUS_REG(0x1102)
#define RESET1_USB __BIT(2)
+#define RESET6_REG CBUS_REG(0x1107)
+#define RESET6_SDIO __BIT(8)
+
#define PREG_CTLREG0_ADDR_REG CBUS_REG(0x2000)
#define PREG_CTLREG0_ADDR_CLKRATE __BITS(9,4)
#define PREG_PAD_GPIO0_EN_N_REG CBUS_REG(0x200c)
+#define PREG_PAD_GPIO0_OUT_REG CBUS_REG(0x200d)
+#define PREG_PAD_GPIO0_IN_REG CBUS_REG(0x200e)
+
+#define PREG_PAD_GPIO3_EN_N_REG CBUS_REG(0x2015)
+#define PREG_PAD_GPIO3_OUT_REG CBUS_REG(0x2016)
+#define PREG_PAD_GPIO3_IN_REG CBUS_REG(0x2017)
+#define PREG_PAD_GPIO3_PUPD_EN_REG CBUS_REG(0x204a)
+#define PREG_PAD_GPIO3_PUPD_REG CBUS_REG(0x203c)
+
+#define PREG_PAD_GPIO5_EN_N_REG CBUS_REG(0x201b)
+#define PREG_PAD_GPIO5_OUT_REG CBUS_REG(0x201c)
+#define PREG_PAD_GPIO5_IN_REG CBUS_REG(0x201d)
#define PERIPHS_PIN_MUX_0_REG CBUS_REG(0x202c)
#define PERIPHS_PIN_MUX_1_REG CBUS_REG(0x202d)
Index: src/sys/arch/arm/amlogic/amlogic_io.c
diff -u src/sys/arch/arm/amlogic/amlogic_io.c:1.9 src/sys/arch/arm/amlogic/amlogic_io.c:1.10
--- src/sys/arch/arm/amlogic/amlogic_io.c:1.9 Sun Mar 29 22:49:44 2015
+++ src/sys/arch/arm/amlogic/amlogic_io.c Sun Apr 19 18:54:52 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: amlogic_io.c,v 1.9 2015/03/29 22:49:44 jmcneill Exp $ */
+/* $NetBSD: amlogic_io.c,v 1.10 2015/04/19 18:54:52 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <[email protected]>
@@ -29,7 +29,7 @@
#include "opt_amlogic.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amlogic_io.c,v 1.9 2015/03/29 22:49:44 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amlogic_io.c,v 1.10 2015/04/19 18:54:52 jmcneill Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -73,6 +73,10 @@ static const struct amlogic_locators aml
AMLOGIC_USB1_OFFSET, AMLOGIC_USB_SIZE, 1, AMLOGIC_INTR_USB1 },
{ "awge",
AMLOGIC_GMAC_OFFSET, AMLOGIC_GMAC_SIZE, NOPORT, AMLOGIC_INTR_GMAC },
+ { "amlogicsdio",
+ AMLOGIC_SDIO_OFFSET, AMLOGIC_SDIO_SIZE, 1, AMLOGIC_INTR_SDIO },
+ { "amlogicsdio",
+ AMLOGIC_SDIO_OFFSET, AMLOGIC_SDIO_SIZE, 2, AMLOGIC_INTR_SDIO },
{ "amlogicsdhc",
AMLOGIC_SDHC_OFFSET, AMLOGIC_SDHC_SIZE, 1, AMLOGIC_INTR_SDHC },
{ "amlogicsdhc",
Index: src/sys/arch/arm/amlogic/amlogic_var.h
diff -u src/sys/arch/arm/amlogic/amlogic_var.h:1.9 src/sys/arch/arm/amlogic/amlogic_var.h:1.10
--- src/sys/arch/arm/amlogic/amlogic_var.h:1.9 Sun Mar 29 22:49:44 2015
+++ src/sys/arch/arm/amlogic/amlogic_var.h Sun Apr 19 18:54:52 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: amlogic_var.h,v 1.9 2015/03/29 22:49:44 jmcneill Exp $ */
+/* $NetBSD: amlogic_var.h,v 1.10 2015/04/19 18:54:52 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <[email protected]>
@@ -63,16 +63,27 @@ void amlogic_usbphy_init(int);
void amlogic_eth_init(void);
void amlogic_rng_init(void);
void amlogic_sdhc_init(void);
+void amlogic_sdio_init(void);
int amlogic_sdhc_select_port(int);
+void amlogic_sdhc_reset_port(int);
+bool amlogic_sdhc_is_removable(int);
+bool amlogic_sdhc_is_card_present(int);
+#define AMLOGIC_SDHC_PORT_A 0
#define AMLOGIC_SDHC_PORT_B 1
#define AMLOGIC_SDHC_PORT_C 2
+int amlogic_sdio_select_port(int);
+#define AMLOGIC_SDIO_PORT_A 0
+#define AMLOGIC_SDIO_PORT_B 1
+#define AMLOGIC_SDIO_PORT_C 2
+
uint32_t amlogic_get_rate_xtal(void);
uint32_t amlogic_get_rate_sys(void);
uint32_t amlogic_get_rate_fixed(void);
uint32_t amlogic_get_rate_a9(void);
uint32_t amlogic_get_rate_a9periph(void);
+uint32_t amlogic_get_rate_clk81(void);
void amlogic_genfb_ddb_trap_callback(int);
void amlogic_genfb_set_console_dev(device_t);
Index: src/sys/arch/arm/amlogic/files.amlogic
diff -u src/sys/arch/arm/amlogic/files.amlogic:1.10 src/sys/arch/arm/amlogic/files.amlogic:1.11
--- src/sys/arch/arm/amlogic/files.amlogic:1.10 Sun Mar 29 22:49:44 2015
+++ src/sys/arch/arm/amlogic/files.amlogic Sun Apr 19 18:54:52 2015
@@ -1,4 +1,4 @@
-# $NetBSD: files.amlogic,v 1.10 2015/03/29 22:49:44 jmcneill Exp $
+# $NetBSD: files.amlogic,v 1.11 2015/04/19 18:54:52 jmcneill Exp $
#
# Configuration info for Amlogic ARM Peripherals
#
@@ -30,6 +30,11 @@ file arch/arm/amlogic/amlogic_com.c aml
attach genfb at amlogicio with amlogic_genfb
file arch/arm/amlogic/amlogic_genfb.c amlogic_genfb needs-flag
+# SDIO
+device amlogicsdio: sdmmcbus
+attach amlogicsdio at amlogicio with amlogic_sdio
+file arch/arm/amlogic/amlogic_sdio.c amlogic_sdio
+
# SDHC
device amlogicsdhc: sdmmcbus
attach amlogicsdhc at amlogicio with amlogic_sdhc
Added files:
Index: src/sys/arch/arm/amlogic/amlogic_sdio.c
diff -u /dev/null src/sys/arch/arm/amlogic/amlogic_sdio.c:1.1
--- /dev/null Sun Apr 19 18:54:52 2015
+++ src/sys/arch/arm/amlogic/amlogic_sdio.c Sun Apr 19 18:54:52 2015
@@ -0,0 +1,499 @@
+/* $NetBSD: amlogic_sdio.c,v 1.1 2015/04/19 18:54:52 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2015 Jared D. McNeill <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "locators.h"
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: amlogic_sdio.c,v 1.1 2015/04/19 18:54:52 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/intr.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+
+#include <dev/sdmmc/sdmmcvar.h>
+#include <dev/sdmmc/sdmmcchip.h>
+#include <dev/sdmmc/sdmmc_ioreg.h>
+
+#include <arm/amlogic/amlogic_reg.h>
+#include <arm/amlogic/amlogic_sdioreg.h>
+#include <arm/amlogic/amlogic_var.h>
+
+static int amlogic_sdio_match(device_t, cfdata_t, void *);
+static void amlogic_sdio_attach(device_t, device_t, void *);
+static void amlogic_sdio_attach_i(device_t);
+
+static int amlogic_sdio_intr(void *);
+
+struct amlogic_sdio_softc {
+ device_t sc_dev;
+ bus_space_tag_t sc_bst;
+ bus_space_handle_t sc_bsh;
+ bus_dma_tag_t sc_dmat;
+ void *sc_ih;
+
+ uint32_t sc_bus_freq;
+ u_int sc_cur_width;
+ u_int sc_cur_port;
+
+ device_t sc_sdmmc_dev;
+ kmutex_t sc_intr_lock;
+ kcondvar_t sc_intr_cv;
+
+ uint32_t sc_intr_irqs;
+};
+
+CFATTACH_DECL_NEW(amlogic_sdio, sizeof(struct amlogic_sdio_softc),
+ amlogic_sdio_match, amlogic_sdio_attach, NULL, NULL);
+
+static int amlogic_sdio_host_reset(sdmmc_chipset_handle_t);
+static uint32_t amlogic_sdio_host_ocr(sdmmc_chipset_handle_t);
+static int amlogic_sdio_host_maxblklen(sdmmc_chipset_handle_t);
+static int amlogic_sdio_card_detect(sdmmc_chipset_handle_t);
+static int amlogic_sdio_write_protect(sdmmc_chipset_handle_t);
+static int amlogic_sdio_bus_power(sdmmc_chipset_handle_t, uint32_t);
+static int amlogic_sdio_bus_clock(sdmmc_chipset_handle_t, int);
+static int amlogic_sdio_bus_width(sdmmc_chipset_handle_t, int);
+static int amlogic_sdio_bus_rod(sdmmc_chipset_handle_t, int);
+static void amlogic_sdio_exec_command(sdmmc_chipset_handle_t,
+ struct sdmmc_command *);
+static void amlogic_sdio_card_enable_intr(sdmmc_chipset_handle_t, int);
+static void amlogic_sdio_card_intr_ack(sdmmc_chipset_handle_t);
+
+static int amlogic_sdio_set_clock(struct amlogic_sdio_softc *, u_int);
+static int amlogic_sdio_wait_irqs(struct amlogic_sdio_softc *, uint32_t, int);
+
+static struct sdmmc_chip_functions amlogic_sdio_chip_functions = {
+ .host_reset = amlogic_sdio_host_reset,
+ .host_ocr = amlogic_sdio_host_ocr,
+ .host_maxblklen = amlogic_sdio_host_maxblklen,
+ .card_detect = amlogic_sdio_card_detect,
+ .write_protect = amlogic_sdio_write_protect,
+ .bus_power = amlogic_sdio_bus_power,
+ .bus_clock = amlogic_sdio_bus_clock,
+ .bus_width = amlogic_sdio_bus_width,
+ .bus_rod = amlogic_sdio_bus_rod,
+ .exec_command = amlogic_sdio_exec_command,
+ .card_enable_intr = amlogic_sdio_card_enable_intr,
+ .card_intr_ack = amlogic_sdio_card_intr_ack,
+};
+
+#define SDIO_WRITE(sc, reg, val) \
+ bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
+#define SDIO_READ(sc, reg) \
+ bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
+
+static int
+amlogic_sdio_match(device_t parent, cfdata_t cf, void *aux)
+{
+ struct amlogicio_attach_args * const aio = aux;
+ const struct amlogic_locators * const loc = &aio->aio_loc;
+
+ if (loc->loc_port == AMLOGICIOCF_PORT_DEFAULT)
+ return 0;
+
+ return 1;
+}
+
+static void
+amlogic_sdio_attach(device_t parent, device_t self, void *aux)
+{
+ struct amlogic_sdio_softc * const sc = device_private(self);
+ struct amlogicio_attach_args * const aio = aux;
+ const struct amlogic_locators * const loc = &aio->aio_loc;
+
+ sc->sc_dev = self;
+ sc->sc_bst = aio->aio_core_bst;
+ sc->sc_dmat = aio->aio_dmat;
+ sc->sc_cur_port = loc->loc_port;
+ bus_space_subregion(aio->aio_core_bst, aio->aio_bsh,
+ loc->loc_offset, loc->loc_size, &sc->sc_bsh);
+ mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_BIO);
+ cv_init(&sc->sc_intr_cv, "sdiointr");
+
+ amlogic_sdio_init();
+ if (amlogic_sdio_select_port(loc->loc_port) != 0) {
+ aprint_error(": couldn't select port %d\n", loc->loc_port);
+ return;
+ }
+
+ aprint_naive("\n");
+ aprint_normal(": SDIO controller\n");
+
+ sc->sc_ih = intr_establish(loc->loc_intr, IPL_BIO, IST_EDGE,
+ amlogic_sdio_intr, sc);
+ if (sc->sc_ih == NULL) {
+ aprint_error_dev(self, "couldn't establish interrupt %d\n",
+ loc->loc_intr);
+ return;
+ }
+ aprint_normal_dev(self, "interrupting on irq %d\n", loc->loc_intr);
+
+ sc->sc_bus_freq = amlogic_get_rate_clk81();
+ aprint_debug_dev(self, "CLK81 rate: %u Hz\n", sc->sc_bus_freq);
+
+ config_interrupts(self, amlogic_sdio_attach_i);
+}
+
+static void
+amlogic_sdio_attach_i(device_t self)
+{
+ struct amlogic_sdio_softc *sc = device_private(self);
+ struct sdmmcbus_attach_args saa;
+
+ amlogic_sdio_host_reset(sc);
+ amlogic_sdio_bus_clock(sc, 400);
+ amlogic_sdio_bus_width(sc, 1);
+
+ memset(&saa, 0, sizeof(saa));
+ saa.saa_busname = "sdmmc";
+ saa.saa_sct = &amlogic_sdio_chip_functions;
+ saa.saa_dmat = sc->sc_dmat;
+ saa.saa_sch = sc;
+ saa.saa_clkmin = 400;
+ saa.saa_clkmax = 50000;
+ saa.saa_caps = SMC_CAPS_4BIT_MODE|
+ SMC_CAPS_SD_HIGHSPEED|
+ SMC_CAPS_MMC_HIGHSPEED|
+ SMC_CAPS_DMA;
+
+ sc->sc_sdmmc_dev = config_found(self, &saa, NULL);
+}
+
+static int
+amlogic_sdio_intr(void *priv)
+{
+ struct amlogic_sdio_softc *sc = priv;
+
+ mutex_enter(&sc->sc_intr_lock);
+ sc->sc_intr_irqs |= SDIO_READ(sc, SDIO_IRQS_REG);
+ cv_broadcast(&sc->sc_intr_cv);
+ mutex_exit(&sc->sc_intr_lock);
+
+ return 1;
+}
+
+static int
+amlogic_sdio_set_clock(struct amlogic_sdio_softc *sc, u_int freq)
+{
+ const u_int pll_freq = sc->sc_bus_freq / 2000;
+ uint32_t conf;
+ int clk_div;
+
+ if (freq == 0)
+ return 0;
+
+ clk_div = howmany(pll_freq, freq);
+
+ conf = SDIO_READ(sc, SDIO_CONF_REG);
+ conf &= ~SDIO_CONF_COMMAND_CLK_DIV;
+ conf |= __SHIFTIN(clk_div - 1, SDIO_CONF_COMMAND_CLK_DIV);
+ SDIO_WRITE(sc, SDIO_CONF_REG, conf);
+
+ return 0;
+}
+
+static int
+amlogic_sdio_wait_irqs(struct amlogic_sdio_softc *sc, uint32_t mask, int timeout)
+{
+ int retry, error;
+
+ KASSERT(mutex_owned(&sc->sc_intr_lock));
+
+ if (sc->sc_intr_irqs & mask)
+ return 0;
+
+ retry = timeout / hz;
+
+ while (retry > 0) {
+ error = cv_timedwait(&sc->sc_intr_cv, &sc->sc_intr_lock, hz);
+ if (error && error != EWOULDBLOCK)
+ return error;
+ if (sc->sc_intr_irqs & mask)
+ return 0;
+ --retry;
+ }
+
+ return ETIMEDOUT;
+}
+
+static int
+amlogic_sdio_host_reset(sdmmc_chipset_handle_t sch)
+{
+ struct amlogic_sdio_softc *sc = sch;
+
+ SDIO_WRITE(sc, SDIO_IRQC_REG, SDIO_IRQC_SOFT_RESET);
+
+ delay(2);
+
+ SDIO_WRITE(sc, SDIO_IRQS_REG, SDIO_IRQS_CLEAR);
+ SDIO_WRITE(sc, SDIO_CONF_REG,
+ __SHIFTIN(2, SDIO_CONF_WRITE_CRC_OK_STATUS) |
+ __SHIFTIN(2, SDIO_CONF_WRITE_NWR) |
+ __SHIFTIN(3, SDIO_CONF_M_ENDIAN) |
+ __SHIFTIN(39, SDIO_CONF_COMMAND_ARG_BITS) |
+ __SHIFTIN(0x1f4, SDIO_CONF_COMMAND_CLK_DIV));
+
+ SDIO_WRITE(sc, SDIO_MULT_REG,
+ __SHIFTIN(sc->sc_cur_port, SDIO_MULT_PORT_SEL));
+
+ return 0;
+}
+
+static uint32_t
+amlogic_sdio_host_ocr(sdmmc_chipset_handle_t sch)
+{
+ return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V;
+}
+
+static int
+amlogic_sdio_host_maxblklen(sdmmc_chipset_handle_t sch)
+{
+ return 512;
+}
+
+static int
+amlogic_sdio_card_detect(sdmmc_chipset_handle_t sch)
+{
+ return 1;
+}
+
+static int
+amlogic_sdio_write_protect(sdmmc_chipset_handle_t sch)
+{
+ return 0;
+}
+
+static int
+amlogic_sdio_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr)
+{
+ return 0;
+}
+
+static int
+amlogic_sdio_bus_clock(sdmmc_chipset_handle_t sch, int freq)
+{
+ struct amlogic_sdio_softc *sc = sch;
+
+ return amlogic_sdio_set_clock(sc, freq);
+}
+
+static int
+amlogic_sdio_bus_width(sdmmc_chipset_handle_t sch, int width)
+{
+ struct amlogic_sdio_softc *sc = sch;
+ uint32_t conf;
+
+ conf = SDIO_READ(sc, SDIO_CONF_REG);
+ if (width == 1) {
+ conf &= ~SDIO_CONF_BUS_WIDTH;
+ } else if (width == 4) {
+ conf |= SDIO_CONF_BUS_WIDTH;
+ } else {
+ return EINVAL;
+ }
+ SDIO_WRITE(sc, SDIO_CONF_REG, conf);
+
+ sc->sc_cur_width = width;
+
+ return 0;
+}
+
+static int
+amlogic_sdio_bus_rod(sdmmc_chipset_handle_t sch, int on)
+{
+ return ENOTSUP;
+}
+
+static void
+amlogic_sdio_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd)
+{
+ struct amlogic_sdio_softc *sc = sch;
+ uint32_t send, ext, mult, addr;
+ int i;
+
+ KASSERT(cmd->c_blklen <= 512);
+
+ send = ext = mult = addr = 0;
+
+ mutex_enter(&sc->sc_intr_lock);
+
+ if (cmd->c_opcode == SD_IO_SEND_OP_COND ||
+ cmd->c_opcode == SD_IO_RW_DIRECT ||
+ cmd->c_opcode == SD_IO_RW_EXTENDED) {
+ cmd->c_error = EINVAL;
+ goto done;
+ }
+
+ sc->sc_intr_irqs = 0;
+
+ if (cmd->c_flags & SCF_RSP_PRESENT) {
+ if (cmd->c_flags & SCF_RSP_136) {
+ send |= __SHIFTIN(133, SDIO_SEND_RESPONSE_BITS);
+ send |= SDIO_SEND_RESPONSE_CRC7_FROM_8;
+ } else {
+ send |= __SHIFTIN(45, SDIO_SEND_RESPONSE_BITS);
+ }
+ }
+ if ((cmd->c_flags & SCF_RSP_CRC) == 0) {
+ send |= SDIO_SEND_RESPONSE_NO_CRC;
+ }
+ if (cmd->c_flags & SCF_RSP_BSY) {
+ send |= SDIO_SEND_CHECK_BUSY_DAT0;
+ }
+
+ if (cmd->c_datalen > 0) {
+ unsigned int nblks, packlen;
+
+ nblks = cmd->c_datalen / cmd->c_blklen;
+ if (nblks == 0 || (cmd->c_datalen % cmd->c_blklen) != 0)
+ ++nblks;
+ packlen = (cmd->c_blklen * 8) + (0xf * sc->sc_cur_width);
+
+ send |= __SHIFTIN(nblks - 1, SDIO_SEND_REPEAT_PACKAGE);
+ ext |= __SHIFTIN(packlen, SDIO_EXT_DATA_RW_NUMBER);
+
+ if (ISSET(cmd->c_flags, SCF_CMD_READ)) {
+ send |= SDIO_SEND_RESPONSE_DATA;
+ } else {
+ send |= SDIO_SEND_COMMAND_HAS_DATA;
+ }
+
+ KASSERT(cmd->c_dmamap->dm_nsegs == 1);
+ KASSERT(cmd->c_dmamap->dm_segs[0].ds_len >= cmd->c_datalen);
+
+ addr = cmd->c_dmamap->dm_segs[0].ds_addr;
+ }
+ send |= __SHIFTIN(cmd->c_opcode | 0x40, SDIO_SEND_COMMAND_INDEX);
+
+ mult |= __SHIFTIN(sc->sc_cur_port, SDIO_MULT_PORT_SEL);
+
+ SDIO_WRITE(sc, SDIO_IRQC_REG, SDIO_IRQC_SOFT_RESET);
+ delay(2);
+
+ SDIO_WRITE(sc, SDIO_IRQC_REG, SDIO_IRQC_ARC_CMD_INTEN);
+ SDIO_WRITE(sc, SDIO_IRQS_REG, SDIO_IRQS_CLEAR);
+
+ SDIO_WRITE(sc, SDIO_ARGU_REG, cmd->c_arg);
+ SDIO_WRITE(sc, SDIO_MULT_REG, mult);
+ SDIO_WRITE(sc, SDIO_EXT_REG, ext);
+ SDIO_WRITE(sc, SDIO_ADDR_REG, addr);
+ SDIO_WRITE(sc, SDIO_SEND_REG, send);
+
+ cmd->c_error = amlogic_sdio_wait_irqs(sc, SDIO_IRQS_CMD_INT, hz * 3);
+ if (cmd->c_error) {
+ goto done;
+ }
+ SDIO_WRITE(sc, SDIO_IRQS_REG, SDIO_IRQS_CLEAR);
+
+ if (SDIO_READ(sc, SDIO_IRQS_REG) & SDIO_IRQS_CMD_BUSY) {
+ int retry;
+ for (retry = 20000; retry > 0; retry--) {
+ const uint32_t irqs = SDIO_READ(sc, SDIO_IRQS_REG);
+ if ((irqs & SDIO_IRQS_CMD_BUSY) == 0)
+ break;
+ delay(100);
+ }
+ if (retry == 0) {
+ device_printf(sc->sc_dev,
+ "busy timeout, opcode %d flags %#x datalen %d\n",
+ cmd->c_opcode, cmd->c_flags, cmd->c_datalen);
+ cmd->c_error = ETIMEDOUT;
+ goto done;
+ }
+ }
+
+ const uint32_t irqs = SDIO_READ(sc, SDIO_IRQS_REG);
+ if (cmd->c_flags & SCF_RSP_CRC) {
+ if ((irqs & SDIO_IRQS_RESPONSE_CRC7_OK) == 0) {
+ device_printf(sc->sc_dev, "response crc error\n");
+ cmd->c_error = EIO;
+ goto done;
+ }
+ }
+ if (cmd->c_datalen > 0) {
+ uint32_t crcmask = SDIO_IRQS_DATA_READ_CRC16_OK|
+ SDIO_IRQS_DATA_WRITE_CRC16_OK;
+ if ((irqs & crcmask) == 0) {
+ device_printf(sc->sc_dev, "data crc error\n");
+ cmd->c_error = EIO;
+ goto done;
+ }
+ }
+
+ if (cmd->c_flags & SCF_RSP_PRESENT) {
+ mult |= SDIO_MULT_WRITE_READ_OUT_INDEX;
+ mult &= ~SDIO_MULT_RESPONSE_READ_INDEX;
+ SDIO_WRITE(sc, SDIO_MULT_REG, mult);
+
+ if (cmd->c_flags & SCF_RSP_136) {
+ for (i = 0; i < 4; i++) {
+ cmd->c_resp[i] = SDIO_READ(sc, SDIO_ARGU_REG);
+ }
+ } else {
+ cmd->c_resp[0] = SDIO_READ(sc, SDIO_ARGU_REG);
+ }
+ }
+
+done:
+ cmd->c_flags |= SCF_ITSDONE;
+
+ SDIO_WRITE(sc, SDIO_IRQC_REG, 0);
+ SDIO_WRITE(sc, SDIO_IRQS_REG, SDIO_IRQS_CLEAR);
+
+ mutex_exit(&sc->sc_intr_lock);
+}
+
+static void
+amlogic_sdio_card_enable_intr(sdmmc_chipset_handle_t sch, int enable)
+{
+ struct amlogic_sdio_softc *sc = sch;
+ uint32_t irqc;
+
+ mutex_enter(&sc->sc_intr_lock);
+ irqc = SDIO_READ(sc, SDIO_IRQC_REG);
+ if (enable) {
+ irqc |= SDIO_IRQC_ARC_IF_INTEN;
+ } else {
+ irqc &= ~SDIO_IRQC_ARC_IF_INTEN;
+ }
+ SDIO_WRITE(sc, SDIO_IRQC_REG, irqc);
+ mutex_exit(&sc->sc_intr_lock);
+}
+
+static void
+amlogic_sdio_card_intr_ack(sdmmc_chipset_handle_t sch)
+{
+ struct amlogic_sdio_softc *sc = sch;
+
+ mutex_enter(&sc->sc_intr_lock);
+ SDIO_WRITE(sc, SDIO_IRQS_REG, SDIO_IRQS_IF_INT);
+ mutex_exit(&sc->sc_intr_lock);
+}
Index: src/sys/arch/arm/amlogic/amlogic_sdioreg.h
diff -u /dev/null src/sys/arch/arm/amlogic/amlogic_sdioreg.h:1.1
--- /dev/null Sun Apr 19 18:54:52 2015
+++ src/sys/arch/arm/amlogic/amlogic_sdioreg.h Sun Apr 19 18:54:52 2015
@@ -0,0 +1,116 @@
+/* $NetBSD: amlogic_sdioreg.h,v 1.1 2015/04/19 18:54:52 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2015 Jared D. McNeill <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _ARM_AMLOGIC_SDIOREG_H
+#define _ARM_AMLOGIC_SDIOREG_H
+
+#define SDIO_ARGU_REG 0x00
+#define SDIO_SEND_REG 0x04
+#define SDIO_CONF_REG 0x08
+#define SDIO_IRQS_REG 0x0c
+#define SDIO_IRQC_REG 0x10
+#define SDIO_MULT_REG 0x14
+#define SDIO_ADDR_REG 0x18
+#define SDIO_EXT_REG 0x1c
+#define SDIO_CCTL_REG 0x40
+#define SDIO_CDAT_REG 0x44
+
+#define SDIO_SEND_COMMAND_INDEX __BITS(7,0)
+#define SDIO_SEND_RESPONSE_BITS __BITS(15,8)
+#define SDIO_SEND_RESPONSE_NO_CRC __BIT(16)
+#define SDIO_SEND_RESPONSE_DATA __BIT(17)
+#define SDIO_SEND_RESPONSE_CRC7_FROM_8 __BIT(18)
+#define SDIO_SEND_CHECK_BUSY_DAT0 __BIT(19)
+#define SDIO_SEND_COMMAND_HAS_DATA __BIT(20)
+#define SDIO_SEND_USE_INT_WINDOW __BIT(21)
+#define SDIO_SEND_REPEAT_PACKAGE __BITS(31,24)
+
+#define SDIO_CONF_COMMAND_CLK_DIV __BITS(9,0)
+#define SDIO_CONF_COMMAND_DISABLE_CRC __BIT(10)
+#define SDIO_CONF_COMMAND_OUT_AT_POSEDGE __BIT(11)
+#define SDIO_CONF_COMMAND_ARG_BITS __BITS(17,12)
+#define SDIO_CONF_NO_DELAY_DATA __BIT(18)
+#define SDIO_CONF_DATA_LATCH_AT_NEGEDGE __BIT(19)
+#define SDIO_CONF_BUS_WIDTH __BIT(20)
+#define SDIO_CONF_M_ENDIAN __BITS(22,21)
+#define SDIO_CONF_WRITE_NWR __BITS(28,23)
+#define SDIO_CONF_WRITE_CRC_OK_STATUS __BITS(31,29)
+
+#define SDIO_IRQS_STATUS __BITS(3,0)
+#define SDIO_IRQS_CMD_BUSY __BIT(4)
+#define SDIO_IRQS_RESPONSE_CRC7_OK __BIT(5)
+#define SDIO_IRQS_DATA_READ_CRC16_OK __BIT(6)
+#define SDIO_IRQS_DATA_WRITE_CRC16_OK __BIT(7)
+#define SDIO_IRQS_IF_INT __BIT(8)
+#define SDIO_IRQS_CMD_INT __BIT(9)
+#define SDIO_IRQS_SOFT_INT __BIT(10)
+#define SDIO_IRQS_SET_SOFT_INT __BIT(11)
+#define SDIO_IRQS_STATUS_INFO __BIT(15,12)
+#define SDIO_IRQS_TIMING_OUT_INT __BIT(16)
+#define SDIO_IRQS_AMRISC_TIMING_OUT_INTEN __BIT(17)
+#define SDIO_IRQS_ARC_TIMING_OUT_INTEN __BIT(18)
+#define SDIO_IRQS_TIMING_OUT_COUNT __BITS(31,19)
+#define SDIO_IRQS_CLEAR \
+ (SDIO_IRQS_IF_INT|SDIO_IRQS_SOFT_INT|SDIO_IRQS_SET_SOFT_INT|\
+ SDIO_IRQS_TIMING_OUT_INT)
+
+#define SDIO_IRQC_AMRISC_IF_INTEN __BIT(0)
+#define SDIO_IRQC_AMRISC_CMD_INTEN __BIT(1)
+#define SDIO_IRQC_AMRISC_SOFT_INTEN __BIT(2)
+#define SDIO_IRQC_ARC_IF_INTEN __BIT(3)
+#define SDIO_IRQC_ARC_CMD_INTEN __BIT(4)
+#define SDIO_IRQC_ARC_SOFT_INTEN __BIT(5)
+#define SDIO_IRQC_IF_INT_CONFIG __BITS(7,6)
+#define SDIO_IRQC_FORCE_DATA __BITS(13,8)
+#define SDIO_IRQC_FORCE_ENABLE __BIT(14)
+#define SDIO_IRQC_SOFT_RESET __BIT(15)
+#define SDIO_IRQC_FORCE_OUTEN __BITS(21,16)
+#define SDIO_IRQC_DISABLE_MEM_HALT __BITS(23,22)
+#define SDIO_IRQC_FORCE_DATA_READ __BITS(29,24)
+#define SDIO_IRQC_FORCE_HALT __BIT(30)
+#define SDIO_IRQC_HALT_HOLE __BIT(31)
+
+#define SDIO_MULT_PORT_SEL __BITS(1,0)
+#define SDIO_MULT_MS_ENABLE __BIT(2)
+#define SDIO_MULT_MS_SCLK_ALWAYS __BIT(3)
+#define SDIO_MULT_STREAM_ENABLE __BIT(4)
+#define SDIO_MULT_STREAM_8BIT_MODE __BIT(5)
+#define SDIO_MULT_DATA_CATCH_LEVEL __BITS(7,6)
+#define SDIO_MULT_WRITE_READ_OUT_INDEX __BIT(8)
+#define SDIO_MULT_DATA_CATCH_READOUT_EN __BIT(9)
+#define SDIO_MULT_DAT0_DATA_ON_DAT1 __BIT(10)
+#define SDIO_MULT_DAT1_DATA_SWAPPED __BIT(11)
+#define SDIO_MULT_RESPONSE_READ_INDEX __BITS(15,12)
+#define SDIO_MULT_DATA_CATCH_FINISH_PT __BITS(27,16)
+
+#define SDIO_EXT_CMD_ARG_EXT __BITS(15,0)
+#define SDIO_EXT_DATA_RW_NUMBER __BITS(29,16)
+#define SDIO_EXT_DATA_RW_NO_CRC16 __BIT(30)
+#define SDIO_EXT_CRC_STATUS_4LINE __BIT(31)
+
+#endif /* _ARM_AMLOGIC_SDIOREG_H */
