Module Name: src
Committed By: macallan
Date: Tue Apr 21 19:56:02 UTC 2015
Modified Files:
src/sys/arch/mips/ingenic: ingenic_regs.h
Log Message:
#define some bits in the clock gating registers
To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/mips/ingenic/ingenic_regs.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/ingenic/ingenic_regs.h
diff -u src/sys/arch/mips/ingenic/ingenic_regs.h:1.13 src/sys/arch/mips/ingenic/ingenic_regs.h:1.14
--- src/sys/arch/mips/ingenic/ingenic_regs.h:1.13 Tue Apr 21 19:19:31 2015
+++ src/sys/arch/mips/ingenic/ingenic_regs.h Tue Apr 21 19:56:01 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: ingenic_regs.h,v 1.13 2015/04/21 19:19:31 macallan Exp $ */
+/* $NetBSD: ingenic_regs.h,v 1.14 2015/04/21 19:56:01 macallan Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -181,6 +181,12 @@ MFC0(uint32_t r, uint32_t s)
#define JZ_PLLBP 0x00000002 /* PLL bypass */
#define JZ_PLLEN 0x00000001 /* PLL enable */
#define JZ_CLKGR0 0x10000020 /* CLocK Gating Registers */
+ #define CLK_OTG0 (1 << 2)
+ #define CLK_SMB0 (1 << 5)
+ #define CLK_SMB1 (1 << 6)
+ #define CLK_UHC (1 << 24)
+ #define CLK_SMB2 (1 << 25)
+ #define CLK_LCD (1 << 28)
#define JZ_OPCR 0x10000024 /* Oscillator Power Control Reg. */
#define OPCR_IDLE_DIS 0x80000000 /* don't stop CPU clk on idle */
#define OPCR_GPU_CLK_ST 0x40000000 /* stop GPU clock */
@@ -197,6 +203,12 @@ MFC0(uint32_t r, uint32_t s)
#define OPCR_CPU_MODE 0x00000002 /* 1 access 'accelerated' */
#define OPCR_OSE 0x00000001 /* disable EXTCLK */
#define JZ_CLKGR1 0x10000028 /* CLocK Gating Registers */
+ #define CLK_SMB3 (1 << 0)
+ #define CLK_OTG1 (1 << 8)
+ #define CLK_HDMI (1 << 9)
+ #define CLK_AHB_MON (1 << 11)
+ #define CLK_SMB4 (1 << 12)
+
#define JZ_USBPCR 0x1000003c
#define PCR_USB_MODE 0x80000000 /* 1 - otg */
#define PCR_AVLD_REG 0x40000000
