Module Name: src
Committed By: jmcneill
Date: Sun Apr 26 16:22:57 UTC 2015
Modified Files:
src/sys/arch/arm/cortex: a9_mpsubr.S
Log Message:
isb between TTBCR write and TLBIALL
To generate a diff of this commit:
cvs rdiff -u -r1.32 -r1.33 src/sys/arch/arm/cortex/a9_mpsubr.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/a9_mpsubr.S
diff -u src/sys/arch/arm/cortex/a9_mpsubr.S:1.32 src/sys/arch/arm/cortex/a9_mpsubr.S:1.33
--- src/sys/arch/arm/cortex/a9_mpsubr.S:1.32 Mon Apr 20 23:12:56 2015
+++ src/sys/arch/arm/cortex/a9_mpsubr.S Sun Apr 26 16:22:57 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: a9_mpsubr.S,v 1.32 2015/04/20 23:12:56 jmcneill Exp $ */
+/* $NetBSD: a9_mpsubr.S,v 1.33 2015/04/26 16:22:57 jmcneill Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -207,6 +207,8 @@ arm_cpuinit:
#endif
mcr p15, 0, r1, c2, c0, 2 // TTBCR write
+ isb
+
#if !defined(CPU_CORTEXA5)
XPUTC(#'I')
mov r1, #0
