Module Name: src
Committed By: jmcneill
Date: Sat May 9 11:17:59 UTC 2015
Modified Files:
src/sys/arch/arm/nvidia: tegra_car.c tegra_carreg.h tegra_var.h
Log Message:
add tegra_car_pllu_rate
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/nvidia/tegra_car.c
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/nvidia/tegra_carreg.h
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/nvidia/tegra_var.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/nvidia/tegra_car.c
diff -u src/sys/arch/arm/nvidia/tegra_car.c:1.4 src/sys/arch/arm/nvidia/tegra_car.c:1.5
--- src/sys/arch/arm/nvidia/tegra_car.c:1.4 Sun May 3 16:40:12 2015
+++ src/sys/arch/arm/nvidia/tegra_car.c Sat May 9 11:17:59 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_car.c,v 1.4 2015/05/03 16:40:12 jmcneill Exp $ */
+/* $NetBSD: tegra_car.c,v 1.5 2015/05/09 11:17:59 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcne...@invisible.ca>
@@ -29,7 +29,7 @@
#include "locators.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_car.c,v 1.4 2015/05/03 16:40:12 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_car.c,v 1.5 2015/05/09 11:17:59 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -81,6 +81,8 @@ tegra_car_attach(device_t parent, device
aprint_normal(": CAR\n");
aprint_verbose_dev(self, "PLLX = %u Hz\n", tegra_car_pllx_rate());
+ aprint_verbose_dev(self, "PLLC = %u Hz\n", tegra_car_pllc_rate());
+ aprint_verbose_dev(self, "PLLU = %u Hz\n", tegra_car_pllu_rate());
aprint_verbose_dev(self, "PLLP0 = %u Hz\n", tegra_car_pllp0_rate());
}
@@ -139,6 +141,26 @@ tegra_car_pllc_rate(void)
}
u_int
+tegra_car_pllu_rate(void)
+{
+ bus_space_tag_t bst;
+ bus_space_handle_t bsh;
+ uint64_t rate;
+
+ tegra_car_get_bs(&bst, &bsh);
+
+ rate = tegra_car_osc_rate();
+ const uint32_t base = bus_space_read_4(bst, bsh, CAR_PLLU_BASE_REG);
+ const u_int divm = __SHIFTOUT(base, CAR_PLLU_BASE_DIVM);
+ const u_int divn = __SHIFTOUT(base, CAR_PLLU_BASE_DIVN);
+ const u_int divp = __SHIFTOUT(base, CAR_PLLU_BASE_VCO_FREQ) ? 0 : 1;
+
+ rate = (uint64_t)tegra_car_osc_rate() * divn;
+
+ return rate / (divm << divp);
+}
+
+u_int
tegra_car_pllp0_rate(void)
{
return tegra_car_pll_rate(CAR_PLLP_BASE_REG, CAR_PLLP_BASE_DIVM,
Index: src/sys/arch/arm/nvidia/tegra_carreg.h
diff -u src/sys/arch/arm/nvidia/tegra_carreg.h:1.5 src/sys/arch/arm/nvidia/tegra_carreg.h:1.6
--- src/sys/arch/arm/nvidia/tegra_carreg.h:1.5 Wed May 6 21:27:05 2015
+++ src/sys/arch/arm/nvidia/tegra_carreg.h Sat May 9 11:17:59 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_carreg.h,v 1.5 2015/05/06 21:27:05 skrll Exp $ */
+/* $NetBSD: tegra_carreg.h,v 1.6 2015/05/09 11:17:59 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcne...@invisible.ca>
@@ -64,6 +64,20 @@
#define CAR_PLLC_BASE_DIVN __BITS(15,8)
#define CAR_PLLC_BASE_DIVM __BITS(7,0)
+#define CAR_PLLU_BASE_REG 0xc0
+#define CAR_PLLU_BASE_BYPASS __BIT(31)
+#define CAR_PLLU_BASE_ENABLE __BIT(30)
+#define CAR_PLLU_BASE_REF_DIS __BIT(29)
+#define CAR_PLLU_BASE_LOCK __BIT(27)
+#define CAR_PLLU_BASE_CLKENABLE_48M __BIT(25)
+#define CAR_PLLU_BASE_OVERRIDE __BIT(24)
+#define CAR_PLLU_BASE_CLKENABLE_ICUSB __BIT(23)
+#define CAR_PLLU_BASE_CLKENABLE_HSIC __BIT(22)
+#define CAR_PLLU_BASE_CLKENABLE_USB __BIT(21)
+#define CAR_PLLU_BASE_VCO_FREQ __BIT(20)
+#define CAR_PLLU_BASE_DIVN __BITS(17,8)
+#define CAR_PLLU_BASE_DIVM __BITS(4,0)
+
#define CAR_PLLX_BASE_REG 0xe0
#define CAR_PLLX_BASE_BYPASS __BIT(31)
#define CAR_PLLX_BASE_ENABLE __BIT(30)
Index: src/sys/arch/arm/nvidia/tegra_var.h
diff -u src/sys/arch/arm/nvidia/tegra_var.h:1.9 src/sys/arch/arm/nvidia/tegra_var.h:1.10
--- src/sys/arch/arm/nvidia/tegra_var.h:1.9 Thu May 7 23:55:11 2015
+++ src/sys/arch/arm/nvidia/tegra_var.h Sat May 9 11:17:59 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_var.h,v 1.9 2015/05/07 23:55:11 jmcneill Exp $ */
+/* $NetBSD: tegra_var.h,v 1.10 2015/05/09 11:17:59 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcne...@invisible.ca>
@@ -76,6 +76,7 @@ void tegra_dma_bootstrap(psize_t);
u_int tegra_car_osc_rate(void);
u_int tegra_car_pllc_rate(void);
u_int tegra_car_pllx_rate(void);
+u_int tegra_car_pllu_rate(void);
u_int tegra_car_pllp0_rate(void);
u_int tegra_car_uart_rate(u_int);
u_int tegra_car_periph_sdmmc_rate(u_int);
