Module Name: src
Committed By: hsuenaga
Date: Thu May 14 05:39:32 UTC 2015
Modified Files:
src/sys/arch/arm/arm: cpufunc.c cpufunc_asm_pj4b.S
src/sys/arch/arm/include: cpufunc_proto.h
src/sys/arch/arm/marvell: armadaxp.c armadaxpreg.h mvsocreg.h
src/sys/arch/evbarm/marvell: marvell_machdep.c
Log Message:
add synchronization barrier for AURORA_IO_CACHE_COHERENCY.
cleanup MARVELL L2 cache code.
To generate a diff of this commit:
cvs rdiff -u -r1.153 -r1.154 src/sys/arch/arm/arm/cpufunc.c
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/arm/cpufunc_asm_pj4b.S
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/include/cpufunc_proto.h
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/arm/marvell/armadaxp.c
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/marvell/armadaxpreg.h
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/marvell/mvsocreg.h
cvs rdiff -u -r1.30 -r1.31 src/sys/arch/evbarm/marvell/marvell_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/cpufunc.c
diff -u src/sys/arch/arm/arm/cpufunc.c:1.153 src/sys/arch/arm/arm/cpufunc.c:1.154
--- src/sys/arch/arm/arm/cpufunc.c:1.153 Fri Apr 17 13:39:01 2015
+++ src/sys/arch/arm/arm/cpufunc.c Thu May 14 05:39:32 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.c,v 1.153 2015/04/17 13:39:01 hsuenaga Exp $ */
+/* $NetBSD: cpufunc.c,v 1.154 2015/05/14 05:39:32 hsuenaga Exp $ */
/*
* arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -49,7 +49,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.153 2015/04/17 13:39:01 hsuenaga Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.154 2015/05/14 05:39:32 hsuenaga Exp $");
#include "opt_compat_netbsd.h"
#include "opt_cpuoptions.h"
@@ -1371,8 +1371,7 @@ struct cpu_functions pj4bv7_cpufuncs = {
.cf_tlb_flushD = armv7_tlb_flushID,
.cf_tlb_flushD_SE = armv7_tlb_flushID_SE,
- /* Cache operations */
-
+ /* Cache operations (see also pj4bv7_setup) */
.cf_icache_sync_all = armv7_idcache_wbinv_all,
.cf_icache_sync_range = armv7_icache_sync_range,
@@ -1381,18 +1380,6 @@ struct cpu_functions pj4bv7_cpufuncs = {
.cf_dcache_inv_range = armv7_dcache_inv_range,
.cf_dcache_wb_range = armv7_dcache_wb_range,
-#if defined(L2CACHE_ENABLE) && \
- !defined(AURORA_IO_CACHE_COHERENCY) && \
- defined(ARMADAXP)
- .cf_sdcache_wbinv_range = armadaxp_sdcache_wbinv_range,
- .cf_sdcache_inv_range = armadaxp_sdcache_inv_range,
- .cf_sdcache_wb_range = armadaxp_sdcache_wb_range,
-#else
- .cf_sdcache_wbinv_range = (void *)cpufunc_nullop,
- .cf_sdcache_inv_range = (void *)cpufunc_nullop,
- .cf_sdcache_wb_range = (void *)cpufunc_nullop,
-#endif
-
.cf_idcache_wbinv_all = armv7_idcache_wbinv_all,
.cf_idcache_wbinv_range = armv7_idcache_wbinv_range,
@@ -3096,6 +3083,36 @@ pj4bv7_setup(char *args)
cpuctrl |= CPU_CONTROL_VECRELOC;
#endif
+#ifdef L2CACHE_ENABLE
+ /* Setup L2 cache */
+ arm_scache.cache_type = CPU_CT_CTYPE_WT;
+ arm_scache.cache_unified = 1;
+ arm_scache.dcache_type = arm_scache.icache_type = CACHE_TYPE_PIPT;
+ arm_scache.dcache_size = arm_scache.icache_size = ARMADAXP_L2_SIZE;
+ arm_scache.dcache_ways = arm_scache.icache_ways = ARMADAXP_L2_WAYS;
+ arm_scache.dcache_way_size = arm_scache.icache_way_size =
+ ARMADAXP_L2_WAY_SIZE;
+ arm_scache.dcache_line_size = arm_scache.icache_line_size =
+ ARMADAXP_L2_LINE_SIZE;
+ arm_scache.dcache_sets = arm_scache.icache_sets =
+ ARMADAXP_L2_SETS;
+
+ cpufuncs.cf_sdcache_wbinv_range = armadaxp_sdcache_wbinv_range;
+ cpufuncs.cf_sdcache_inv_range = armadaxp_sdcache_inv_range;
+ cpufuncs.cf_sdcache_wb_range = armadaxp_sdcache_wb_range;
+#endif
+
+#ifdef AURORA_IO_CACHE_COHERENCY
+ /* use AMBA and I/O Coherency Fabric to maintain cache */
+ cpufuncs.cf_dcache_wbinv_range = pj4b_dcache_cfu_wbinv_range;
+ cpufuncs.cf_dcache_inv_range = pj4b_dcache_cfu_inv_range;
+ cpufuncs.cf_dcache_wb_range = pj4b_dcache_cfu_wb_range;
+
+ cpufuncs.cf_sdcache_wbinv_range = (void *)cpufunc_nullop;
+ cpufuncs.cf_sdcache_inv_range = (void *)cpufunc_nullop;
+ cpufuncs.cf_sdcache_wb_range = (void *)cpufunc_nullop;
+#endif
+
/* Clear out the cache */
cpu_idcache_wbinv_all();
@@ -3104,6 +3121,9 @@ pj4bv7_setup(char *args)
/* And again. */
cpu_idcache_wbinv_all();
+#ifdef L2CACHE_ENABLE
+ armadaxp_sdcache_wbinv_all();
+#endif
curcpu()->ci_ctrl = cpuctrl;
}
Index: src/sys/arch/arm/arm/cpufunc_asm_pj4b.S
diff -u src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.7 src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.8
--- src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.7 Wed Apr 15 10:52:18 2015
+++ src/sys/arch/arm/arm/cpufunc_asm_pj4b.S Thu May 14 05:39:32 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_pj4b.S,v 1.7 2015/04/15 10:52:18 hsuenaga Exp $ */
+/* $NetBSD: cpufunc_asm_pj4b.S,v 1.8 2015/05/14 05:39:32 hsuenaga Exp $ */
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
@@ -41,9 +41,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBI
#include <arm/asm.h>
#include <arm/locore.h>
-.Lpj4b_cache_line_size:
- .word _C_LABEL(arm_dcache_align)
+.Lpj4b_l2_barrier_reg:
+ .word _C_LABEL(armadaxp_l2_barrier_reg)
+/* LINTSTUB: void pj4b_cpu_sleep(int); */
ENTRY(pj4b_cpu_sleep)
dsb
wfi @ wait for an interrupt
@@ -51,6 +52,7 @@ ENTRY(pj4b_cpu_sleep)
b irq_idle_entry @ assume we got an interrupt
END(pj4b_cpu_sleep)
+/* LINTSTUB: void pj4b_config(void); */
ENTRY(pj4b_config)
/* Set Auxiliary Debug Modes Control 0 register */
mrc p15, 1, r0, c15, c1, 0
@@ -87,3 +89,21 @@ ENTRY(pj4b_config)
RET
END(pj4b_config)
+
+/* LINTSTUB: void pj4b_io_coherency_barrier(vaddr_t, paddr_t, vsize_t); */
+ENTRY_NP(pj4b_io_coherency_barrier)
+ ldr r0, .Lpj4b_l2_barrier_reg
+ ldr r0, [r0] @ MVSOC_MLMB_CIB_BARRIER
+ mov r1, #1 @ MVSOC_MLMB_CIB_BARRIER_TRIGGER
+ str r1, [r0]
+1:
+ ldr r1, [r0]
+ tst r1, #1
+ beq 1b
+ dsb
+ RET
+END(pj4b_io_coherency_barrier)
+
+STRONG_ALIAS(pj4b_dcache_cfu_wbinv_range, pj4b_io_coherency_barrier)
+STRONG_ALIAS(pj4b_dcache_cfu_inv_range, pj4b_io_coherency_barrier)
+STRONG_ALIAS(pj4b_dcache_cfu_wb_range, pj4b_io_coherency_barrier)
Index: src/sys/arch/arm/include/cpufunc_proto.h
diff -u src/sys/arch/arm/include/cpufunc_proto.h:1.4 src/sys/arch/arm/include/cpufunc_proto.h:1.5
--- src/sys/arch/arm/include/cpufunc_proto.h:1.4 Wed Apr 15 10:52:18 2015
+++ src/sys/arch/arm/include/cpufunc_proto.h Thu May 14 05:39:32 2015
@@ -326,6 +326,10 @@ void armv7_setup(char *string);
void pj4b_cpu_sleep(int);
void pj4bv7_setup(char *string);
void pj4b_config(void);
+void pj4b_io_coherency_barrier(vaddr_t, paddr_t, vsize_t);
+void pj4b_dcache_cfu_inv_range(vaddr_t, vsize_t);
+void pj4b_dcache_cfu_wb_range(vaddr_t, vsize_t);
+void pj4b_dcache_cfu_wbinv_range(vaddr_t, vsize_t);
#endif /* CPU_PJ4B */
#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
Index: src/sys/arch/arm/marvell/armadaxp.c
diff -u src/sys/arch/arm/marvell/armadaxp.c:1.12 src/sys/arch/arm/marvell/armadaxp.c:1.13
--- src/sys/arch/arm/marvell/armadaxp.c:1.12 Sun May 3 06:29:31 2015
+++ src/sys/arch/arm/marvell/armadaxp.c Thu May 14 05:39:32 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: armadaxp.c,v 1.12 2015/05/03 06:29:31 hsuenaga Exp $ */
+/* $NetBSD: armadaxp.c,v 1.13 2015/05/14 05:39:32 hsuenaga Exp $ */
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
@@ -37,7 +37,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBI
*******************************************************************************/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: armadaxp.c,v 1.12 2015/05/03 06:29:31 hsuenaga Exp $");
+__KERNEL_RCSID(0, "$NetBSD: armadaxp.c,v 1.13 2015/05/14 05:39:32 hsuenaga Exp $");
#define _INTR_PRIVATE
@@ -89,6 +89,7 @@ int l2cache_state = 0;
int iocc_state = 0;
#define read_miscreg(r) (*(volatile uint32_t *)(misc_base + (r)))
vaddr_t misc_base;
+vaddr_t armadaxp_l2_barrier_reg;
extern void (*mvsoc_intr_init)(void);
static void armadaxp_intr_init(void);
@@ -432,11 +433,18 @@ armadaxp_l2_init(bus_addr_t pbase)
return (-1);
}
+ /* Variables for cpufunc_asm_pj4b.S */
+ armadaxp_l2_barrier_reg = mlmb_base + MVSOC_MLMB_CIB_BARRIER_TRIGGER;
+
/* Set L2 policy */
reg = L2_READ(ARMADAXP_L2_AUX_CTRL);
- reg &= ~(L2_WBWT_MODE_MASK);
- reg &= ~(L2_REP_STRAT_MASK);
- reg |= L2_REP_STRAT_SEMIPLRU;
+ reg &= ~(L2_AUX_WBWT_MODE_MASK);
+ reg &= ~(L2_AUX_REP_STRAT_MASK);
+ reg |= L2_AUX_WBWT_MODE_WB;
+ reg |= L2_AUX_ECC_ENABLE;
+ reg |= L2_AUX_PARITY_ENABLE;
+ reg |= L2_AUX_FORCE_WA;
+ reg |= L2_AUX_REP_STRAT_SEMIPLRU;
L2_WRITE(ARMADAXP_L2_AUX_CTRL, reg);
/* Invalidate L2 cache */
@@ -460,7 +468,7 @@ armadaxp_l2_init(bus_addr_t pbase)
/* Enable L2 cache */
reg = L2_READ(ARMADAXP_L2_CTRL);
- L2_WRITE(ARMADAXP_L2_CTRL, reg | L2_ENABLE);
+ L2_WRITE(ARMADAXP_L2_CTRL, reg | L2_CTRL_ENABLE);
/* Mark as enabled */
l2cache_state = 1;
@@ -497,39 +505,88 @@ armadaxp_sdcache_wbinv_all(void)
__asm__ __volatile__("dsb");
}
+static paddr_t
+armadaxp_sdcache_wbalign_base(vaddr_t va, paddr_t pa, psize_t sz)
+{
+ paddr_t line_start = pa & ~ARMADAXP_L2_ALIGN;
+ vaddr_t save_start;
+ uint8_t save_buf[ARMADAXP_L2_LINE_SIZE];
+ size_t unalign;
+
+ unalign = va & ARMADAXP_L2_ALIGN;
+ if (unalign == 0)
+ return line_start; /* request is aligned to cache line size */
+
+ /* save data that is not intended to invalidate */
+ save_start = va & ~ARMADAXP_L2_ALIGN;
+ memcpy(save_buf, (void *)save_start, unalign);
+
+ /* invalidate include saved data */
+ L2_WRITE(ARMADAXP_L2_INV_PHYS, line_start);
+
+ /* write back saved data */
+ memcpy((void *)save_start, save_buf, unalign);
+ L2_WRITE(ARMADAXP_L2_WB_PHYS, line_start);
+ L2_WRITE(ARMADAXP_L2_SYNC, 0);
+ __asm__ __volatile__("dsb");
+
+ return line_start;
+}
+
+static paddr_t
+armadaxp_sdcache_wbalign_end(vaddr_t va, paddr_t pa, psize_t sz)
+{
+ paddr_t line_start = (pa + sz - 1) & ~ARMADAXP_L2_ALIGN;
+ vaddr_t save_start = va + sz;
+ uint8_t save_buf[ARMADAXP_L2_LINE_SIZE];
+ size_t save_len;
+ size_t unalign;
+
+ unalign = save_start & ARMADAXP_L2_ALIGN;
+ if (unalign == 0)
+ return line_start; /* request is aligned to cache line size */
+
+ /* save data that is not intended to invalidate */
+ save_len = ARMADAXP_L2_LINE_SIZE - unalign;
+ memcpy(save_buf, (void *)save_start, save_len);
+
+ /* invalidate include saved data */
+ L2_WRITE(ARMADAXP_L2_INV_PHYS, line_start);
+
+ /* write back saved data */
+ memcpy((void *)save_start, save_buf, save_len);
+ L2_WRITE(ARMADAXP_L2_WB_PHYS, line_start);
+ __asm__ __volatile__("dsb");
+
+ return line_start;
+}
+
void
armadaxp_sdcache_inv_range(vaddr_t va, paddr_t pa, psize_t sz)
{
- paddr_t pa_base = pa;
- paddr_t pa_end = pa + sz - 1;
+ paddr_t pa_base;
+ paddr_t pa_end;
- /* need write back if boundary is not aligned */
- if (pa_base & 0x1f)
- L2_WRITE(ARMADAXP_L2_WB_PHYS, (pa_base & ~0x1f));
- if (pa_end & 0x1f)
- L2_WRITE(ARMADAXP_L2_WB_PHYS, (pa_end & ~0x1f));
- L2_WRITE(ARMADAXP_L2_SYNC, 0);
- __asm__ __volatile__("dsb");
+ /* align and write-back the boundary */
+ pa_base = armadaxp_sdcache_wbalign_base(va, pa, sz);
+ pa_end = armadaxp_sdcache_wbalign_end(va, pa, sz);
/* invalidate other cache */
- pa_base &= ~0x1f;
- pa_end &= ~0x1f;
- if (pa_base == pa_end)
+ if (pa_base == pa_end) {
L2_WRITE(ARMADAXP_L2_INV_PHYS, pa_base);
- else {
- L2_WRITE(ARMADAXP_L2_RANGE_BASE, pa_base);
- L2_WRITE(ARMADAXP_L2_INV_RANGE, pa_end);
+ return;
}
+
+ L2_WRITE(ARMADAXP_L2_RANGE_BASE, pa_base);
+ L2_WRITE(ARMADAXP_L2_INV_RANGE, pa_end);
}
void
armadaxp_sdcache_wb_range(vaddr_t va, paddr_t pa, psize_t sz)
{
- paddr_t pa_base = pa;
- paddr_t pa_end = pa + sz - 1;
+ paddr_t pa_base = pa & ~ARMADAXP_L2_ALIGN;
+ paddr_t pa_end = (pa + sz - 1) & ~ARMADAXP_L2_ALIGN;
- pa_base &= ~0x1f;
- pa_end &= ~0x1f;
if (pa_base == pa_end)
L2_WRITE(ARMADAXP_L2_WB_PHYS, pa_base);
else {
@@ -543,11 +600,9 @@ armadaxp_sdcache_wb_range(vaddr_t va, pa
void
armadaxp_sdcache_wbinv_range(vaddr_t va, paddr_t pa, psize_t sz)
{
- paddr_t pa_base = pa;
- paddr_t pa_end = pa + sz - 1;
+ paddr_t pa_base = pa & ~ARMADAXP_L2_ALIGN;;
+ paddr_t pa_end = (pa + sz - 1) & ~ARMADAXP_L2_ALIGN;
- pa_base &= ~0x1f;
- pa_end &= ~0x1f;
if (pa_base == pa_end)
L2_WRITE(ARMADAXP_L2_WBINV_PHYS, pa_base);
else {
@@ -565,19 +620,22 @@ armadaxp_io_coherency_init(void)
/* set CIB read snoop command to ReadUnique */
reg = read_mlmbreg(MVSOC_MLMB_CIB_CTRL_CFG);
- reg &= ~(7 << 16);
- reg |= (7 << 16);
+ reg |= MVSOC_MLMB_CIB_CTRL_CFG_WB_EN;
write_mlmbreg(MVSOC_MLMB_CIB_CTRL_CFG, reg);
+
/* enable CPUs in SMP group on Fabric coherency */
- reg = read_mlmbreg(MVSOC_MLMB_COHERENCY_FABRIC_CTRL);
- reg &= ~(0x3 << 24);
- reg |= (1 << 24);
- write_mlmbreg(MVSOC_MLMB_COHERENCY_FABRIC_CTRL, reg);
-
- reg = read_mlmbreg(MVSOC_MLMB_COHERENCY_FABRIC_CFG);
- reg &= ~(0x3 << 24);
- reg |= (1 << 24);
- write_mlmbreg(MVSOC_MLMB_COHERENCY_FABRIC_CFG, reg);
+ reg = read_mlmbreg(MVSOC_MLMB_CFU_CTRL);
+ reg |= MVSOC_MLMB_CFU_CTRL_SNOOP_CPU0;
+ write_mlmbreg(MVSOC_MLMB_CFU_CTRL, reg);
+
+ /* send all snoop request to L2 cache */
+ reg = read_mlmbreg(MVSOC_MLMB_CFU_CFG);
+#ifdef L2CACHE_ENABLE
+ reg |= MVSOC_MLMB_CFU_CFG_L2_NOTIFY;
+#else
+ reg &= ~MVSOC_MLMB_CFU_CFG_L2_NOTIFY;
+#endif
+ write_mlmbreg(MVSOC_MLMB_CFU_CFG, reg);
/* Mark as enabled */
iocc_state = 1;
Index: src/sys/arch/arm/marvell/armadaxpreg.h
diff -u src/sys/arch/arm/marvell/armadaxpreg.h:1.3 src/sys/arch/arm/marvell/armadaxpreg.h:1.4
--- src/sys/arch/arm/marvell/armadaxpreg.h:1.3 Wed Apr 15 10:40:36 2015
+++ src/sys/arch/arm/marvell/armadaxpreg.h Thu May 14 05:39:32 2015
@@ -75,7 +75,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBI
#define ARMADAXP_ATTR_PEX3_MEM 0xf8
#define ARMADAXP_ATTR_PEX3_IO 0xf0
-
#define ARMADAXP_IRQ_GBE0_TH_RXTX 8 /* GBE0_TH_RXTX_Int */
#define ARMADAXP_IRQ_GBE1_TH_RXTX 10 /* GBE1_TH_RXTX_Int */
#define ARMADAXP_IRQ_GBE2_TH_RXTX 12 /* GBE2_TH_RXTX_Int */
@@ -239,10 +238,45 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBI
#define ARMADAXP_L2_WBINV_RANGE 0x7f4
#define ARMADAXP_L2_WBINV_IDXWAY 0x7f8
#define ARMADAXP_L2_WBINV_WAY 0x7fc
-#define L2_ENABLE (1 << 0)
-#define L2_WBWT_MODE_MASK (3 << 0)
-#define L2_REP_STRAT_MASK (3 << 27)
-#define L2_REP_STRAT_SEMIPLRU (3 << 27)
+
+/* Cache line size */
+#define ARMADAXP_L2_SIZE (256 * 1024) /* bytes */
+#define ARMADAXP_L2_LINE_SIZE 32
+#define ARMADAXP_L2_ALIGN (ARMADAXP_L2_LINE_SIZE - 1)
+#define ARMADAXP_L2_WAYS 4
+#define ARMADAXP_L2_WAY_SIZE (ARMADAXP_L2_SIZE / ARMADAXP_L2_WAYS)
+#define ARMADAXP_L2_SETS \
+ (ARMADAXP_L2_WAY_SIZE / ARMADAXP_L2_LINE_SIZE)
+
+/* ARMADAXP_L2_CTRL */
+#define L2_CTRL_ENABLE (1 << 0)
+
+/* ARMADAXP_L2_AUX_CTRL */
+#define L2_AUX_WBWT_MODE_MASK (3 << 0)
+#define L2_AUX_WBWT_MODE_BY_ATTR (0 << 0)
+#define L2_AUX_WBWT_MODE_WB (1 << 0)
+#define L2_AUX_WBWT_MODE_WT (2 << 0)
+#define L2_AUX_FLUSH_ON_POWERDOWN (1 << 3)
+#define L2_AUX_ECC_ENABLE (1 << 20)
+#define L2_AUX_PARITY_ENABLE (1 << 21)
+#define L2_AUX_INVAL_UCE (1 << 22)
+#define L2_AUX_FORCE_WA (1 << 23)
+#define L2_AUX_REP_STRAT_MASK (3 << 27)
+#define L2_AUX_REP_STRAT_LFSR (1 << 27)
+#define L2_AUX_REP_STRAT_PLRU (2 << 27)
+#define L2_AUX_REP_STRAT_SEMIPLRU (3 << 27)
+#define L2_AUX_L2_SIZE_MASK (0x03 << 10)
+#define L2_AUX_L2_SIZE_256K (0x00 << 10)
+#define L2_AUX_L2_ASSOC_MASK (0x0f << 13)
+#define L2_AUX_L2_ASSOC_4WAY (0x03 << 13)
+#define L2_AUX_L2_WAY_MASK (0x07 << 17)
+#define L2_AUX_L2_WAY_16K (0x02 << 17)
+#define L2_AUX_L2_WAY_32K (0x03 << 17)
+#define L2_AUX_L2_WAY_64K (0x04 << 17)
+#define L2_AUX_L2_WAY_128K (0x05 << 17)
+#define L2_AUX_L2_WAY_256K (0x06 << 17)
+#define L2_AUX_L2_WAY_512K (0x07 << 17)
+
#define L2_ALL_WAYS 0xffffffff
/*
Index: src/sys/arch/arm/marvell/mvsocreg.h
diff -u src/sys/arch/arm/marvell/mvsocreg.h:1.9 src/sys/arch/arm/marvell/mvsocreg.h:1.10
--- src/sys/arch/arm/marvell/mvsocreg.h:1.9 Mon Feb 17 05:05:46 2014
+++ src/sys/arch/arm/marvell/mvsocreg.h Thu May 14 05:39:32 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: mvsocreg.h,v 1.9 2014/02/17 05:05:46 kiyohara Exp $ */
+/* $NetBSD: mvsocreg.h,v 1.10 2015/05/14 05:39:32 hsuenaga Exp $ */
/*
* Copyright (c) 2007, 2008 KIYOHARA Takashi
* All rights reserved.
@@ -129,11 +129,23 @@
#define MVSOC_MLMB_WINCR_SIZE_MASK 0xff000000
/* Coherent Fabric Control and Status */
-#define MVSOC_MLMB_COHERENCY_FABRIC_CTRL 0x200
-#define MVSOC_MLMB_COHERENCY_FABRIC_CFG 0x204
+#define MVSOC_MLMB_CFU_CTRL 0x200
+#define MVSOC_MLMB_CFU_CTRL_PROP_ERR (0x1 << 8)
+#define MVSOC_MLMB_CFU_CTRL_SNOOP_CPU0 (0x1 << 24)
+
+#define MVSOC_MLMB_CFU_CFG 0x228
+#define MVSOC_MLMB_CFU_CFG_L2_NOTIFY (0x1 << 16)
/* CIB registers offsets */
-#define MVSOC_MLMB_CIB_CTRL_CFG 0x280
+#define MVSOC_MLMB_CIB_CTRL_CFG 0x280
+#define MVSOC_MLMB_CIB_CTRL_CFG_WB_EN (0x1 << 0)
+#define MVSOC_MLMB_CIB_CTRL_CFG_STOP (0x1 << 9)
+#define MVSOC_MLMB_CIB_CTRL_CFG_IGN_SHARE (0x2 << 10)
+#define MVSOC_MLMB_CIB_CTRL_CFG_EMPTY (0x1 << 13)
+
+/* CIB barrier register */
+#define MVSOC_MLMB_CIB_BARRIER 0x1810
+#define MVSOC_MLMB_CIB_BARRIER_TRIGGER (0x1 << 0)
#define MVSOC_TMR_BASE (MVSOC_MLMB_BASE + 0x0300)
Index: src/sys/arch/evbarm/marvell/marvell_machdep.c
diff -u src/sys/arch/evbarm/marvell/marvell_machdep.c:1.30 src/sys/arch/evbarm/marvell/marvell_machdep.c:1.31
--- src/sys/arch/evbarm/marvell/marvell_machdep.c:1.30 Sat Aug 30 13:19:52 2014
+++ src/sys/arch/evbarm/marvell/marvell_machdep.c Thu May 14 05:39:32 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: marvell_machdep.c,v 1.30 2014/08/30 13:19:52 kiyohara Exp $ */
+/* $NetBSD: marvell_machdep.c,v 1.31 2015/05/14 05:39:32 hsuenaga Exp $ */
/*
* Copyright (c) 2007, 2008, 2010 KIYOHARA Takashi
* All rights reserved.
@@ -25,7 +25,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: marvell_machdep.c,v 1.30 2014/08/30 13:19:52 kiyohara Exp $");
+__KERNEL_RCSID(0, "$NetBSD: marvell_machdep.c,v 1.31 2015/05/14 05:39:32 hsuenaga Exp $");
#include "opt_evbarm_boardtype.h"
#include "opt_ddb.h"
@@ -67,6 +67,7 @@ __KERNEL_RCSID(0, "$NetBSD: marvell_mach
#include <arm/marvell/kirkwoodreg.h>
#include <arm/marvell/mv78xx0reg.h>
#include <arm/marvell/armadaxpreg.h>
+#include <arm/marvell/armadaxpvar.h>
#include <arm/marvell/mvsocgppvar.h>
#include <evbarm/marvell/marvellreg.h>
@@ -345,11 +346,7 @@ initarm(void *arg)
#ifdef L2CACHE_ENABLE
/* Initialize L2 Cache */
- {
- extern int armadaxp_l2_init(bus_addr_t);
-
- (void)armadaxp_l2_init(MARVELL_INTERREGS_PBASE);
- }
+ armadaxp_l2_init(MARVELL_INTERREGS_PBASE);
#endif
#ifdef AURORA_IO_CACHE_COHERENCY
