Module Name: src
Committed By: skrll
Date: Sat May 30 20:39:56 UTC 2015
Modified Files:
src/sys/arch/arm/include: armreg.h
Log Message:
Add Revision ID register
To generate a diff of this commit:
cvs rdiff -u -r1.105 -r1.106 src/sys/arch/arm/include/armreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/include/armreg.h
diff -u src/sys/arch/arm/include/armreg.h:1.105 src/sys/arch/arm/include/armreg.h:1.106
--- src/sys/arch/arm/include/armreg.h:1.105 Wed May 20 02:59:57 2015
+++ src/sys/arch/arm/include/armreg.h Sat May 30 20:39:56 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.105 2015/05/20 02:59:57 hsuenaga Exp $ */
+/* $NetBSD: armreg.h,v 1.106 2015/05/30 20:39:56 skrll Exp $ */
/*
* Copyright (c) 1998, 2001 Ben Harris
@@ -900,6 +900,7 @@ ARMREG_READ_INLINE(midr, "p15,0,%0,c0,c0
ARMREG_READ_INLINE(ctr, "p15,0,%0,c0,c0,1") /* Cache Type Register */
ARMREG_READ_INLINE(tlbtr, "p15,0,%0,c0,c0,3") /* TLB Type Register */
ARMREG_READ_INLINE(mpidr, "p15,0,%0,c0,c0,5") /* Multiprocess Affinity Register */
+ARMREG_READ_INLINE(revidr, "p15,0,%0,c0,c0,6") /* Revision ID Register */
ARMREG_READ_INLINE(pfr0, "p15,0,%0,c0,c1,0") /* Processor Feature Register 0 */
ARMREG_READ_INLINE(pfr1, "p15,0,%0,c0,c1,1") /* Processor Feature Register 1 */
ARMREG_READ_INLINE(mmfr0, "p15,0,%0,c0,c1,4") /* Memory Model Feature Register 0 */
