Module Name: src Committed By: matt Date: Thu Jun 11 05:15:49 UTC 2015
Modified Files: src/sys/arch/mips/include: cpuregs.h Log Message: Add a few MIPS32 R3 bits To generate a diff of this commit: cvs rdiff -u -r1.93 -r1.94 src/sys/arch/mips/include/cpuregs.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/arch/mips/include/cpuregs.h diff -u src/sys/arch/mips/include/cpuregs.h:1.93 src/sys/arch/mips/include/cpuregs.h:1.94 --- src/sys/arch/mips/include/cpuregs.h:1.93 Wed Jun 10 05:03:41 2015 +++ src/sys/arch/mips/include/cpuregs.h Thu Jun 11 05:15:49 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: cpuregs.h,v 1.93 2015/06/10 05:03:41 matt Exp $ */ +/* $NetBSD: cpuregs.h,v 1.94 2015/06/11 05:15:49 matt Exp $ */ /* * Copyright (c) 2009 Miodrag Vallat. @@ -748,6 +748,7 @@ #define MIPS1_TLB_PID_SHIFT 6 #define MIPS3_TLB_VPN2 0xffffe000 +#define MIPS3_TLB_EHINV 0x00000400 /* mipsNN R3 */ #define MIPS3_TLB_ASID 0x000000ff #define MIPS1_TLB_VIRT_PAGE_NUM MIPS1_TLB_VPN @@ -940,6 +941,7 @@ #define MIPS_74K 0x97 /* MIPS 74Kc/74Kf ISA 32 Rel 2 */ #define MIPS_1004K 0x99 /* MIPS 1004Kc/1004Kf ISA 32 Rel 2 */ #define MIPS_1074K 0x9a /* MIPS 1074Kc/1074Kf ISA 32 Rel 2 */ +#define MIPS_interAptiv 0xa1 /* MIPS interAptiv ISA 32 R3 MT */ /* * CPU processor revision IDs for company ID == 2 (Broadcom)