Module Name: src
Committed By: skrll
Date: Thu Jul 23 15:07:31 UTC 2015
Modified Files:
src/sys/arch/arm/nvidia: tegra_carreg.h
Log Message:
CAR_PLLD_BASE_REG defines
To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/arm/nvidia/tegra_carreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/nvidia/tegra_carreg.h
diff -u src/sys/arch/arm/nvidia/tegra_carreg.h:1.18 src/sys/arch/arm/nvidia/tegra_carreg.h:1.19
--- src/sys/arch/arm/nvidia/tegra_carreg.h:1.18 Sat May 30 13:25:55 2015
+++ src/sys/arch/arm/nvidia/tegra_carreg.h Thu Jul 23 15:07:31 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_carreg.h,v 1.18 2015/05/30 13:25:55 jmcneill Exp $ */
+/* $NetBSD: tegra_carreg.h,v 1.19 2015/07/23 15:07:31 skrll Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <[email protected]>
@@ -88,6 +88,20 @@
#define CAR_PLLU_BASE_DIVN __BITS(17,8)
#define CAR_PLLU_BASE_DIVM __BITS(4,0)
+#define CAR_PLLD_BASE_REG 0xd0
+#define CAR_PLLD_BASE_BYPASS __BIT(31)
+#define CAR_PLLD_BASE_ENABLE __BIT(30)
+#define CAR_PLLD_BASE_REF_DIS __BIT(29)
+#define CAR_PLLD_BASE_LOCK __BIT(27)
+#define CAR_PLLD_BASE_CLKENABLE_CSI __BIT(26)
+#define CAR_PLLD_BASE_DSIA_CLK_SRC __BIT(25)
+#define CAR_PLLD_BASE_CSI_CLK_SRC __BIT(23)
+#define CAR_PLLD_BASE_DIVP __BITS(22,20)
+#define CAR_PLLD_BASE_DIVN __BITS(18,8)
+#define CAR_PLLD_BASE_DIVM __BITS(4,0)
+
+#define CAR_PLLD_MISC_REG 0xdc
+
#define CAR_PLLX_BASE_REG 0xe0
#define CAR_PLLX_BASE_BYPASS __BIT(31)
#define CAR_PLLX_BASE_ENABLE __BIT(30)
