Module Name: src
Committed By: msaitoh
Date: Mon Oct 19 02:45:26 UTC 2015
Modified Files:
src/sys/arch/x86/include: cacheinfo.h
Log Message:
Add some TLB entries from the latest Intel SDM. This change might incorrect
because the document itself is very strange.
To generate a diff of this commit:
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/x86/include/cacheinfo.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/cacheinfo.h
diff -u src/sys/arch/x86/include/cacheinfo.h:1.19 src/sys/arch/x86/include/cacheinfo.h:1.20
--- src/sys/arch/x86/include/cacheinfo.h:1.19 Tue Sep 9 15:11:33 2014
+++ src/sys/arch/x86/include/cacheinfo.h Mon Oct 19 02:45:26 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: cacheinfo.h,v 1.19 2014/09/09 15:11:33 msaitoh Exp $ */
+/* $NetBSD: cacheinfo.h,v 1.20 2015/10/19 02:45:26 msaitoh Exp $ */
#ifndef _X86_CACHEINFO_H_
#define _X86_CACHEINFO_H_
@@ -234,6 +234,10 @@ __CI_TBL(CAI_DTLB, 0x5c, 0xff, 64,
__CI_TBL(CAI_DTLB, 0x5d, 0xff, 64, 4 * 1024, "4K/4M: 256 entries"),\
__CI_TBL(CAI_ITLB, 0x61, 0xff, 48, 4 * 1024, NULL), \
__CI_TBL(CAI_L1_1GBDTLB,0x63, 4, 4,1024*1024 * 1024, NULL), \
+__CI_TBL(CAI_ITLB, 0x6a, 8, 64, 4 * 1024, NULL), \
+__CI_TBL(CAI_DTLB, 0x6b, 8,256, 4 * 1024, NULL), \
+__CI_TBL(CAI_L2_DTLB2, 0x6c, 8,126, 0, "2M/4M: 126 entries"),\
+__CI_TBL(CAI_L1_1GBDTLB,0x6d,0xff, 16,1024*1024 * 1024, NULL), \
__CI_TBL(CAI_ITLB2, 0x76, 0xff, 8, 4 * 1024 * 1024, "2M/4M: 8 entries"), \
__CI_TBL(CAI_DTLB, 0xa0, 0xff, 32, 4 * 1024, NULL), \
__CI_TBL(CAI_ITLB, 0xb0, 4,128, 4 * 1024, NULL), \
