Module Name: src
Committed By: msaitoh
Date: Wed Oct 21 12:55:00 UTC 2015
Modified Files:
src/sys/dev/pci: pci_subr.c pcireg.h
Log Message:
Decode SATA Capability and Multicast Extendeded Capability.
To generate a diff of this commit:
cvs rdiff -u -r1.137 -r1.138 src/sys/dev/pci/pci_subr.c
cvs rdiff -u -r1.104 -r1.105 src/sys/dev/pci/pcireg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/pci/pci_subr.c
diff -u src/sys/dev/pci/pci_subr.c:1.137 src/sys/dev/pci/pci_subr.c:1.138
--- src/sys/dev/pci/pci_subr.c:1.137 Sat Oct 3 15:22:14 2015
+++ src/sys/dev/pci/pci_subr.c Wed Oct 21 12:54:59 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: pci_subr.c,v 1.137 2015/10/03 15:22:14 joerg Exp $ */
+/* $NetBSD: pci_subr.c,v 1.138 2015/10/21 12:54:59 msaitoh Exp $ */
/*
* Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
@@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.137 2015/10/03 15:22:14 joerg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.138 2015/10/21 12:54:59 msaitoh Exp $");
#ifdef _KERNEL_OPT
#include "opt_pci.h"
@@ -1791,7 +1791,26 @@ pci_conf_print_msix_cap(const pcireg_t *
printf(" BIR: 0x%x\n", reg & PCI_MSIX_PBABIR_MASK);
}
-/* XXX pci_conf_print_sata_cap */
+static void
+pci_conf_print_sata_cap(const pcireg_t *regs, int capoff)
+{
+ pcireg_t reg;
+
+ printf("\n Serial ATA Capability Register\n");
+
+ reg = regs[o2i(capoff + PCI_MSIX_CTL)];
+ printf(" Revision register: 0x%04x\n", (reg >> 16) & 0xff);
+ printf(" Revision: %lu.%lu\n",
+ __SHIFTOUT(reg, PCI_SATA_REV_MAJOR),
+ __SHIFTOUT(reg, PCI_SATA_REV_MINOR));
+
+ reg = regs[o2i(capoff + PCI_SATA_BAR)];
+
+ printf(" BAR Register: 0x%08x\n", reg);
+ printf(" BAR number: %lu\n", reg & PCI_SATA_BAR_NUM);
+ printf(" BAR offset: 0x%08lx\n", reg & PCI_SATA_BAR_OFFSET);
+}
+
static void
pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff)
{
@@ -1838,7 +1857,7 @@ static struct {
{ PCI_CAP_SECURE, "Secure Device", NULL },
{ PCI_CAP_PCIEXPRESS, "PCI Express", pci_conf_print_pcie_cap },
{ PCI_CAP_MSIX, "MSI-X", pci_conf_print_msix_cap },
- { PCI_CAP_SATA, "SATA", NULL },
+ { PCI_CAP_SATA, "SATA", pci_conf_print_sata_cap },
{ PCI_CAP_PCIAF, "Advanced Features", pci_conf_print_pciaf_cap }
};
@@ -2640,7 +2659,72 @@ pci_conf_print_sriov_cap(const pcireg_t
}
/* XXX pci_conf_print_mriov_cap */
-/* XXX pci_conf_print_multicast_cap */
+
+static void
+pci_conf_print_multicast_cap(const pcireg_t *regs, int capoff, int extcapoff)
+{
+ pcireg_t reg, cap, ctl;
+ pcireg_t regl, regh;
+ uint64_t addr;
+ int n;
+
+ printf("\n Multicast\n");
+
+ reg = regs[o2i(extcapoff + PCI_MCAST_CTL)];
+ cap = reg & 0xffff;
+ ctl = reg >> 16;
+ printf(" Capability Register: 0x%04x\n", cap);
+ printf(" Max Group: %lu\n", (reg & PCI_MCAST_CAP_MAXGRP) + 1);
+
+ /* Endpoint Only */
+ n = __SHIFTOUT(reg, PCI_MCAST_CAP_WINSIZEREQ);
+ if (n > 0)
+ printf(" Windw Size Requested: %d\n", 1 << (n - 1));
+
+ onoff("ECRC Regeneration Supported", reg, PCI_MCAST_CAP_ECRCREGEN);
+
+ printf(" Control Register: 0x%04x\n", ctl);
+ printf(" Num Group: %lu\n",
+ __SHIFTOUT(reg, PCI_MCAST_CTL_NUMGRP) + 1);
+ onoff("Enable", reg, PCI_MCAST_CTL_ENA);
+
+ regl = regs[o2i(extcapoff + PCI_MCAST_BARL)];
+ regh = regs[o2i(extcapoff + PCI_MCAST_BARH)];
+ printf(" Base Address Register 0: 0x%08x\n", regl);
+ printf(" Base Address Register 1: 0x%08x\n", regh);
+ printf(" Index Position: %lu\n", regl & PCI_MCAST_BARL_INDPOS);
+ addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_BARL_ADDR);
+ printf(" Base Address: 0x%016" PRIx64 "\n", addr);
+
+ regl = regs[o2i(extcapoff + PCI_MCAST_RECVL)];
+ regh = regs[o2i(extcapoff + PCI_MCAST_RECVH)];
+ printf(" Receive Register 0: 0x%08x\n", regl);
+ printf(" Receive Register 1: 0x%08x\n", regh);
+
+ regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLL)];
+ regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLH)];
+ printf(" Block All Register 0: 0x%08x\n", regl);
+ printf(" Block All Register 1: 0x%08x\n", regh);
+
+ regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSL)];
+ regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSH)];
+ printf(" Block Untranslated Register 0: 0x%08x\n", regl);
+ printf(" Block Untranslated Register 1: 0x%08x\n", regh);
+
+ regl = regs[o2i(extcapoff + PCI_MCAST_OVERLAYL)];
+ regh = regs[o2i(extcapoff + PCI_MCAST_OVERLAYH)];
+ printf(" Overlay BAR 0: 0x%08x\n", regl);
+ printf(" Overlay BAR 1: 0x%08x\n", regh);
+
+ n = regl & PCI_MCAST_OVERLAYL_SIZE;
+ printf(" Overlay Size: ");
+ if (n >= 6)
+ printf("%d\n", n);
+ else
+ printf("off\n");
+ addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_OVERLAYL_ADDR);
+ printf(" Overlay BAR: 0x%016" PRIx64 "\n", addr);
+}
static void
pci_conf_print_page_req_cap(const pcireg_t *regs, int capoff, int extcapoff)
@@ -2957,8 +3041,8 @@ static struct {
pci_conf_print_sriov_cap },
{ PCI_EXTCAP_MRIOV, "Multiple Root IO Virtualization",
NULL },
- { PCI_EXTCAP_MULTICAST, "Multicast",
- NULL },
+ { PCI_EXTCAP_MCAST, "Multicast",
+ pci_conf_print_multicast_cap },
{ PCI_EXTCAP_PAGE_REQ, "Page Request",
pci_conf_print_page_req_cap },
{ PCI_EXTCAP_AMD, "Reserved for AMD",
Index: src/sys/dev/pci/pcireg.h
diff -u src/sys/dev/pci/pcireg.h:1.104 src/sys/dev/pci/pcireg.h:1.105
--- src/sys/dev/pci/pcireg.h:1.104 Fri Oct 2 05:22:53 2015
+++ src/sys/dev/pci/pcireg.h Wed Oct 21 12:54:59 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: pcireg.h,v 1.104 2015/10/02 05:22:53 msaitoh Exp $ */
+/* $NetBSD: pcireg.h,v 1.105 2015/10/21 12:54:59 msaitoh Exp $ */
/*
* Copyright (c) 1995, 1996, 1999, 2000
@@ -1080,6 +1080,12 @@ struct pci_msix_table_entry {
* Capability ID: 0x12
* SATA
*/
+#define PCI_SATA_REV 0x00 /* Revision Register */
+#define PCI_SATA_REV_MINOR __BITS(19, 16) /* Minor Revision */
+#define PCI_SATA_REV_MAJOR __BITS(23, 20) /* Major Revision */
+#define PCI_SATA_BAR 0x04 /* BAR Register */
+#define PCI_SATA_BAR_NUM __BITS(3, 0) /* BAR Specifier */
+#define PCI_SATA_BAR_OFFSET __BITS(23, 4) /* BAR Offset */
/*
* Capability ID: 0x13
@@ -1347,7 +1353,7 @@ struct pci_rom {
#define PCI_EXTCAP_ATS 0x000f /* Address Translation Services */
#define PCI_EXTCAP_SRIOV 0x0010 /* Single Root IO Virtualization */
#define PCI_EXTCAP_MRIOV 0x0011 /* Multiple Root IO Virtualization */
-#define PCI_EXTCAP_MULTICAST 0x0012 /* Multicast */
+#define PCI_EXTCAP_MCAST 0x0012 /* Multicast */
#define PCI_EXTCAP_PAGE_REQ 0x0013 /* Page Request */
#define PCI_EXTCAP_AMD 0x0014 /* Reserved for AMD */
#define PCI_EXTCAP_RESIZE_BAR 0x0015 /* Resizable BAR */
@@ -1690,6 +1696,27 @@ struct pci_rom {
* Extended capability ID: 0x0012
* Multicast
*/
+#define PCI_MCAST_CAP 0x04 /* Capability Register */
+#define PCI_MCAST_CAP_MAXGRP __BITS(5, 0) /* Max Group */
+#define PCI_MCAST_CAP_WINSIZEREQ __BITS(13, 8) /* Window Size Requested */
+#define PCI_MCAST_CAP_ECRCREGEN __BIT(15) /* ECRC Regen. Supported */
+#define PCI_MCAST_CTL 0x04 /* Control Register */
+#define PCI_MCAST_CTL_NUMGRP __BITS(5+16, 16) /* Num Group */
+#define PCI_MCAST_CTL_ENA __BIT(15+16) /* Enable */
+#define PCI_MCAST_BARL 0x08 /* Base Address Register (low) */
+#define PCI_MCAST_BARL_INDPOS __BITS(5, 0) /* Index Position */
+#define PCI_MCAST_BARL_ADDR __BITS(31, 12) /* Base Address Register(low)*/
+#define PCI_MCAST_BARH 0x0c /* Base Address Register (high) */
+#define PCI_MCAST_RECVL 0x10 /* Receive Register (low) */
+#define PCI_MCAST_RECVH 0x14 /* Receive Register (high) */
+#define PCI_MCAST_BLOCKALLL 0x18 /* Block All Register (low) */
+#define PCI_MCAST_BLOCKALLH 0x1c /* Block All Register (high) */
+#define PCI_MCAST_BLOCKUNTRNSL 0x20 /* Block Untranslated Register (low) */
+#define PCI_MCAST_BLOCKUNTRNSH 0x24 /* Block Untranslated Register (high) */
+#define PCI_MCAST_OVERLAYL 0x28 /* Overlay BAR (low) */
+#define PCI_MCAST_OVERLAYL_SIZE __BITS(5, 0) /* Overlay Size */
+#define PCI_MCAST_OVERLAYL_ADDR __BITS(31, 6) /* Overlay BAR (low) */
+#define PCI_MCAST_OVERLAYH 0x2c /* Overlay BAR (high) */
/*
* Extended capability ID: 0x0013
