Module Name: src
Committed By: msaitoh
Date: Mon Oct 26 02:31:31 UTC 2015
Modified Files:
src/sys/dev/mii: igphyreg.h
Log Message:
No binary change:
- s/IGPPHY/IGPHY/
- Fix the definition of PLHR_VALID_CHANNEL_*
- Fix the definition of MSE_CHANNEL_*
- Add MII_IGPHY_POWER_MGMT
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/dev/mii/igphyreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/mii/igphyreg.h
diff -u src/sys/dev/mii/igphyreg.h:1.7 src/sys/dev/mii/igphyreg.h:1.8
--- src/sys/dev/mii/igphyreg.h:1.7 Fri Oct 23 08:40:34 2015
+++ src/sys/dev/mii/igphyreg.h Mon Oct 26 02:31:31 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: igphyreg.h,v 1.7 2015/10/23 08:40:34 msaitoh Exp $ */
+/* $NetBSD: igphyreg.h,v 1.8 2015/10/26 02:31:31 msaitoh Exp $ */
/*******************************************************************************
@@ -43,7 +43,7 @@
*/
/* IGP01E1000 Specific Port Config Register - R/W */
-#define MII_IGPPHY_PORT_CONFIG 0x10 /* PHY specific config register */
+#define MII_IGPHY_PORT_CONFIG 0x10 /* PHY specific config register */
#define PSCFR_AUTO_MDIX_PAR_DETECT 0x0010
#define PSCFR_PRE_EN 0x0020
#define PSCFR_SMART_SPEED 0x0080
@@ -77,18 +77,18 @@
/* IGP01E1000 Specific Port Link Health Register */
#define MII_IGPHY_LINK_HEALTH 0x13
-#define PLHR_SS_DOWNGRADE 0x8000
-#define PLHR_GIG_SCRAMBLER_ERROR 0x4000
-#define PLHR_GIG_REM_RCVR_NOK 0x0800 /* LH */
-#define PLHR_IDLE_ERROR_CNT_OFLOW 0x0400 /* LH */
-#define PLHR_DATA_ERR_1 0x0200 /* LH */
+#define PLHR_VALID_CHANNEL_A 0x0001
+#define PLHR_VALID_CHANNEL_B 0x0002
+#define PLHR_VALID_CHANNEL_C 0x0004
+#define PLHR_VALID_CHANNEL_D 0x0008
+#define PLHR_AUTONEG_ACTIVE 0x0010
+#define PLHR_AUTONEG_FAULT 0x0040
#define PLHR_DATA_ERR_0 0x0100
-#define PLHR_AUTONEG_FAULT 0x0010
-#define PLHR_AUTONEG_ACTIVE 0x0008
-#define PLHR_VALID_CHANNEL_D 0x0004
-#define PLHR_VALID_CHANNEL_C 0x0002
-#define PLHR_VALID_CHANNEL_B 0x0001
-#define PLHR_VALID_CHANNEL_A 0x0000
+#define PLHR_DATA_ERR_1 0x0200 /* LH */
+#define PLHR_IDLE_ERROR_CNT_OFLOW 0x0400 /* LH */
+#define PLHR_GIG_REM_RCVR_NOK 0x0800 /* LH */
+#define PLHR_GIG_SCRAMBLER_ERROR 0x4000
+#define PLHR_SS_DOWNGRADE 0x8000
/* IGP01E1000 GMII FIFO Register */
#define MII_IGGMII_FIFO 0x14
@@ -97,10 +97,17 @@
/* IGP01E1000 Channel Quality Register */
#define MII_IGPHY_CHANNEL_QUALITY 0x15
-#define MSE_CHANNEL_D 0x000F
-#define MSE_CHANNEL_C 0x00F0
-#define MSE_CHANNEL_B 0x0F00
-#define MSE_CHANNEL_A 0xF000
+#define MSE_CHANNEL_A 0x000F
+#define MSE_CHANNEL_B 0x00F0
+#define MSE_CHANNEL_C 0x0F00
+#define MSE_CHANNEL_D 0xF000
+
+/* IGP01E1000 Power Management */
+#define MII_IGPHY_POWER_MGMT 0x19
+#define PMR_SPD_EN 0x0001
+#define PMR_D0_LPLU 0x0002
+#define PMR_D3_LPLU 0x0004
+#define PMR_DIS_1000 0x0040
#define MII_IGPHY_PAGE_SELECT 0x1F
#define IGPHY_MAXREGADDR 0x1F
