Module Name: src
Committed By: msaitoh
Date: Wed Nov 18 04:24:02 UTC 2015
Modified Files:
src/sys/dev/pci: pci_subr.c pcireg.h
Log Message:
- Add the Auto Slot Power Limit Disable bit in Slot Control register and
the Completion Timeout Prefix/Header Log Capable bit in the AER capability
and control register (ECN: Downstream Port Containment (DPC)).
- Add the Poisoned TLP Egress Block bit (ECN: Enhanced DPC).
- Update Link Capabilities 2 register and Link Control 3 register (ECN:
Separate Refclk Independent SSC Architecture (SRIS))
- ECN: Readiness Notifications (RN)
- Add the Retimer Presence Detect Supported bit in the Link Capabilities 2
register and the Retimer Presence Detected bit in the Link Status 2 register
(ECN: Extension Devices)
To generate a diff of this commit:
cvs rdiff -u -r1.145 -r1.146 src/sys/dev/pci/pci_subr.c
cvs rdiff -u -r1.111 -r1.112 src/sys/dev/pci/pcireg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/pci/pci_subr.c
diff -u src/sys/dev/pci/pci_subr.c:1.145 src/sys/dev/pci/pci_subr.c:1.146
--- src/sys/dev/pci/pci_subr.c:1.145 Tue Nov 17 18:26:50 2015
+++ src/sys/dev/pci/pci_subr.c Wed Nov 18 04:24:02 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: pci_subr.c,v 1.145 2015/11/17 18:26:50 msaitoh Exp $ */
+/* $NetBSD: pci_subr.c,v 1.146 2015/11/18 04:24:02 msaitoh Exp $ */
/*
* Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
@@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.145 2015/11/17 18:26:50 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.146 2015/11/18 04:24:02 msaitoh Exp $");
#ifdef _KERNEL_OPT
#include "opt_pci.h"
@@ -729,6 +729,7 @@ pci_conf_print_common(
onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE);
printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff);
+ onoff("Immediate Readness", rval, PCI_STATUS_IMMD_READNESS);
onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active",
"inactive");
onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT);
@@ -1441,6 +1442,34 @@ pci_print_pcie_compl_timeout(uint32_t va
}
}
+static const char * const pcie_linkspeeds[] = {"2.5", "5.0", "8.0"};
+
+static void
+pci_print_pcie_linkspeed(pcireg_t val)
+{
+
+ /* Start from 1 */
+ if (val < 1 || val > __arraycount(pcie_linkspeeds))
+ printf("unknown value (%u)\n", val);
+ else
+ printf("%sGT/s\n", pcie_linkspeeds[val - 1]);
+}
+
+static void
+pci_print_pcie_linkspeedvector(pcireg_t val)
+{
+ unsigned int i;
+
+ /* Start from 0 */
+ for (i = 0; i < 16; i++)
+ if (((val >> i) & 0x01) != 0) {
+ if (i >= __arraycount(pcie_linkspeeds))
+ printf(" unknown vector (%x)", 1 << i);
+ else
+ printf(" %sGT/s", pcie_linkspeeds[i]);
+ }
+}
+
static void
pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff)
{
@@ -1450,8 +1479,6 @@ pci_conf_print_pcie_cap(const pcireg_t *
bool check_slot = false;
bool check_rootport = false;
unsigned int pciever;
- static const char * const linkspeeds[] = {"2.5", "5.0", "8.0"};
- int i;
printf("\n PCI Express Capabilities Register\n");
/* Capability Register */
@@ -1573,12 +1600,7 @@ pci_conf_print_pcie_cap(const pcireg_t *
reg = regs[o2i(capoff + PCIE_LCAP)];
printf(" Link Capabilities Register: 0x%08x\n", reg);
printf(" Maximum Link Speed: ");
- val = reg & PCIE_LCAP_MAX_SPEED;
- if (val < 1 || val > 3) {
- printf("unknown %u value\n", val);
- } else {
- printf("%sGT/s\n", linkspeeds[val - 1]);
- }
+ pci_print_pcie_linkspeed(reg & PCIE_LCAP_MAX_SPEED);
printf(" Maximum Link Width: x%u lanes\n",
(unsigned int)(reg & PCIE_LCAP_MAX_WIDTH) >> 4);
printf(" Active State PM Support: ");
@@ -1643,19 +1665,28 @@ pci_conf_print_pcie_cap(const pcireg_t *
PCIE_LCSR_LBMIE);
onoff("Link Autonomous Bandwidth Interrupt Enable", reg,
PCIE_LCSR_LABIE);
+ printf(" DRS Signaling Control: ");
+ val = __SHIFTOUT(reg, PCIE_LCSR_DRSSGNL);
+ switch (val) {
+ case 0:
+ printf("not reported\n");
+ break;
+ case 1:
+ printf("Interrupt Enabled\n");
+ break;
+ case 2:
+ printf("DRS to FRS Signaling Enabled\n");
+ break;
+ default:
+ printf("reserved\n");
+ break;
+ }
/* Link Status Register */
reg = regs[o2i(capoff + PCIE_LCSR)];
printf(" Link Status Register: 0x%04x\n", reg >> 16);
printf(" Negotiated Link Speed: ");
- if (((reg >> 16) & 0x000f) < 1 ||
- ((reg >> 16) & 0x000f) > 3) {
- printf("unknown %u value\n",
- (unsigned int)(reg & PCIE_LCSR_LINKSPEED) >> 16);
- } else {
- printf("%sGT/s\n",
- linkspeeds[((reg & PCIE_LCSR_LINKSPEED) >> 16)-1]);
- }
+ pci_print_pcie_linkspeed(__SHIFTOUT(reg, PCIE_LCSR_LINKSPEED));
printf(" Negotiated Link Width: x%u lanes\n",
(reg >> 20) & 0x003f);
onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR);
@@ -1734,6 +1765,8 @@ pci_conf_print_pcie_cap(const pcireg_t *
reg, PCIE_SLCSR_EIC);
onoff("Data Link Layer State Changed Enable", reg,
PCIE_SLCSR_DLLSCE);
+ onoff("Auto Slot Power Limit Disable", reg,
+ PCIE_SLCSR_AUTOSPLDIS);
/* Slot Status Register */
printf(" Slot Status Register: %04x\n", reg >> 16);
@@ -1829,6 +1862,7 @@ pci_conf_print_pcie_cap(const pcireg_t *
onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF);
printf(" Max End-End TLP Prefixes: %u\n",
(unsigned int)(reg & PCIE_DCAP2_MAX_EETLP) >> 22);
+ onoff("FRS Supported", reg, PCIE_DCAP2_FRS);
/* Device Control 2 */
reg = regs[o2i(capoff + PCIE_DCSR2)];
@@ -1860,27 +1894,33 @@ pci_conf_print_pcie_cap(const pcireg_t *
onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP);
if (check_link) {
+ bool drs_supported;
+
/* Link Capability 2 */
reg = regs[o2i(capoff + PCIE_LCAP2)];
printf(" Link Capabilities 2: 0x%08x\n", reg);
- val = (reg & PCIE_LCAP2_SUP_LNKSV) >> 1;
printf(" Supported Link Speed Vector:");
- for (i = 0; i <= 2; i++) {
- if (((val >> i) & 0x01) != 0)
- printf(" %sGT/s", linkspeeds[i]);
- }
+ pci_print_pcie_linkspeedvector(
+ __SHIFTOUT(reg, PCIE_LCAP2_SUP_LNKSV));
printf("\n");
onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK);
+ printf(" Lower SKP OS Generation Supported Speed Vector:");
+ pci_print_pcie_linkspeedvector(
+ __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_GENSUPPSV));
+ printf("\n");
+ printf(" Lower SKP OS Reception Supported Speed Vector:");
+ pci_print_pcie_linkspeedvector(
+ __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_RECSUPPSV));
+ printf("\n");
+ onoff("DRS Supported", reg, PCIE_LCAP2_DRS);
+ drs_supported = (reg & PCIE_LCAP2_DRS) ? true : false;
/* Link Control 2 */
reg = regs[o2i(capoff + PCIE_LCSR2)];
printf(" Link Control 2: 0x%04x\n", reg & 0xffff);
printf(" Target Link Speed: ");
- val = reg & PCIE_LCSR2_TGT_LSPEED;
- if (val < 1 || val > 3)
- printf("unknown %u value\n", val);
- else
- printf("%sGT/s\n", linkspeeds[val - 1]);
+ pci_print_pcie_linkspeed(__SHIFTOUT(reg,
+ PCIE_LCSR2_TGT_LSPEED));
onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL);
onoff("HW Autonomous Speed Disabled", reg,
PCIE_LCSR2_HW_AS_DIS);
@@ -1903,6 +1943,33 @@ pci_conf_print_pcie_cap(const pcireg_t *
onoff("Equalization Phase 3 Successful", reg,
PCIE_LCSR2_EQP3_SUC);
onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ);
+ onoff("Retimer Presence Detected", reg, PCIE_LCSR2_RETIMERPD);
+ if (drs_supported) {
+ printf(" Downstream Component Presence: ");
+ switch (__SHIFTOUT(reg, PCIE_LCSR2_DSCOMPN)) {
+ case PCIE_DSCOMPN_DOWN_NOTDETERM:
+ printf("Link Down - Presence Not"
+ " Determined\n");
+ break;
+ case PCIE_DSCOMPN_DOWN_NOTPRES:
+ printf("Link Down - Component Not Present\n");
+ break;
+ case PCIE_DSCOMPN_DOWN_PRES:
+ printf("Link Down - Component Present\n");
+ break;
+ case PCIE_DSCOMPN_UP_PRES:
+ printf("Link Up - Component Present\n");
+ break;
+ case PCIE_DSCOMPN_UP_PRES_DRS:
+ printf("Link Up - Component Present and DRS"
+ " received\n");
+ break;
+ default:
+ printf("reserved\n");
+ break;
+ }
+ onoff("DRS Message Received", reg, PCIE_LCSR2_DRSRCV);
+ }
}
/* Slot Capability 2 */
@@ -2107,7 +2174,7 @@ pci_conf_print_aer_cap_uc(pcireg_t reg)
onoff("Undefined", reg, PCI_AER_UC_UNDEFINED);
onoff("Data Link Protocol Error", reg, PCI_AER_UC_DL_PROTOCOL_ERROR);
onoff("Surprise Down Error", reg, PCI_AER_UC_SURPRISE_DOWN_ERROR);
- onoff("Poisoned TLP", reg, PCI_AER_UC_POISONED_TLP);
+ onoff("Poisoned TLP Received", reg, PCI_AER_UC_POISONED_TLP);
onoff("Flow Control Protocol Error", reg, PCI_AER_UC_FC_PROTOCOL_ERROR);
onoff("Completion Timeout", reg, PCI_AER_UC_COMPLETION_TIMEOUT);
onoff("Completer Abort", reg, PCI_AER_UC_COMPLETER_ABORT);
@@ -2122,7 +2189,9 @@ pci_conf_print_aer_cap_uc(pcireg_t reg)
onoff("MC Blocked TLP", reg, PCI_AER_UC_MC_BLOCKED_TLP);
onoff("AtomicOp Egress BLK", reg, PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED);
onoff("TLP Prefix Blocked Error", reg,
- PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR);
+ PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR);
+ onoff("Poisoned TLP Egress Blocked", reg,
+ PCI_AER_UC_POISONTLP_EGRESS_BLOCKED);
}
static void
@@ -2151,7 +2220,9 @@ pci_conf_print_aer_cap_control(pcireg_t
onoff("ECRC Check Enab", reg, PCI_AER_ECRC_CHECK_ENABLE);
onoff("Multiple Header Recording Capable", reg,
PCI_AER_MULT_HDR_CAPABLE);
- onoff("Multiple Header Recording Enable", reg, PCI_AER_MULT_HDR_ENABLE);
+ onoff("Multiple Header Recording Enable", reg,PCI_AER_MULT_HDR_ENABLE);
+ onoff("Completion Timeout Prefix/Header Log Capable", reg,
+ PCI_AER_COMPTOUTPRFXHDRLOG_CAP);
/* This bit is RsvdP if the End-End TLP Prefix Supported bit is Clear */
if (!tlp_prefix_log)
@@ -3007,6 +3078,10 @@ pci_conf_print_sec_pcie_cap(const pcireg
onoff("Perform Equalization", reg, PCI_SECPCIE_LCTL3_PERFEQ);
onoff("Link Equalization Request Interrupt Enable",
reg, PCI_SECPCIE_LCTL3_LINKEQREQ_IE);
+ printf(" Enable Lower SKP OS Generation Vector:");
+ pci_print_pcie_linkspeedvector(
+ __SHIFTOUT(reg, PCI_SECPCIE_LCTL3_ELSKPOSGENV));
+ printf("\n");
reg = regs[o2i(extcapoff + PCI_SECPCIE_LANEERR_STA)];
printf(" Lane Error Status register: 0x%08x\n", reg);
Index: src/sys/dev/pci/pcireg.h
diff -u src/sys/dev/pci/pcireg.h:1.111 src/sys/dev/pci/pcireg.h:1.112
--- src/sys/dev/pci/pcireg.h:1.111 Tue Nov 17 18:26:50 2015
+++ src/sys/dev/pci/pcireg.h Wed Nov 18 04:24:02 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: pcireg.h,v 1.111 2015/11/17 18:26:50 msaitoh Exp $ */
+/* $NetBSD: pcireg.h,v 1.112 2015/11/18 04:24:02 msaitoh Exp $ */
/*
* Copyright (c) 1995, 1996, 1999, 2000
@@ -92,6 +92,7 @@ typedef u_int16_t pci_product_id_t;
#define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200
#define PCI_COMMAND_INTERRUPT_DISABLE 0x00000400
+#define PCI_STATUS_IMMD_READNESS __BIT(0+16)
#define PCI_STATUS_INT_STATUS 0x00080000
#define PCI_STATUS_CAPLIST_SUPPORT 0x00100000
#define PCI_STATUS_66MHZ_SUPPORT 0x00200000
@@ -943,6 +944,7 @@ typedef u_int8_t pci_revision_t;
#define PCIE_LCSR_HAWD __BIT(9) /* HW Autonomous Width Disable*/
#define PCIE_LCSR_LBMIE __BIT(10) /* Link BW Management Intr En */
#define PCIE_LCSR_LABIE __BIT(11) /* Link Autonomous BW Intr En */
+#define PCIE_LCSR_DRSSGNL __BITS(15, 14) /* DRS Signaling */
#define PCIE_LCSR_LINKSPEED __BITS(19, 16) /* Link Speed */
#define PCIE_LCSR_NLW __BITS(25, 20) /* Negotiated Link Width */
#define PCIE_LCSR_LINKTRAIN_ERR __BIT(10 + 16) /* Link Training Error */
@@ -976,6 +978,7 @@ typedef u_int8_t pci_revision_t;
#define PCIE_SLCSR_PCC __BIT(10) /* Power Controller Control */
#define PCIE_SLCSR_EIC __BIT(11) /* Electromechanical Interlock*/
#define PCIE_SLCSR_DLLSCE __BIT(12) /* DataLinkLayer State Changed*/
+#define PCIE_SLCSR_AUTOSPLDIS __BIT(13) /* Auto Slot Power Limit Dis. */
#define PCIE_SLCSR_ABP __BIT(0 + 16) /* Attention Button Pressed */
#define PCIE_SLCSR_PFD __BIT(1 + 16) /* Power Fault Detected */
#define PCIE_SLCSR_MSC __BIT(2 + 16) /* MRL Sensor Changed */
@@ -1012,6 +1015,7 @@ typedef u_int8_t pci_revision_t;
#define PCIE_DCAP2_EXTFMT_FLD __BIT(20) /* Extended Fmt Field Support */
#define PCIE_DCAP2_EETLP_PREF __BIT(21) /* End-End TLP Prefix Support */
#define PCIE_DCAP2_MAX_EETLP __BITS(23, 22) /* Max End-End TLP Prefix Sup */
+#define PCIE_DCAP2_FRS __BIT(31) /* FRS Supported */
#define PCIE_DCSR2 0x28 /* Device Control & Status 2 Register */
#define PCIE_DCSR2_COMPT_VAL __BITS(3, 0) /* Completion Timeout Value */
#define PCIE_DCSR2_COMPT_DIS __BIT(4) /* Completion Timeout Disable */
@@ -1026,6 +1030,12 @@ typedef u_int8_t pci_revision_t;
#define PCIE_LCAP2 0x2c /* Link Capabilities 2 Register */
#define PCIE_LCAP2_SUP_LNKSV __BITS(7, 1) /* Supported Link Speeds Vect */
#define PCIE_LCAP2_CROSSLNK __BIT(8) /* Crosslink Supported */
+#define PCIE_LCAP2_LOWSKPOS_GENSUPPSV __BITS(15, 9)
+ /* Lower SKP OS Generation Supp. Spd. Vect */
+#define PCIE_LCAP2_LOWSKPOS_RECSUPPSV __BITS(22, 16)
+ /* Lower SKP OS Reception Supp. Spd. Vect */
+#define PCIE_LCAP2_RETIMERPD __BIT(23) /* Retimer Presence Detect */
+#define PCIE_LCAP2_DRS __BIT(31) /* DRS Supported */
#define PCIE_LCSR2 0x30 /* Link Control & Status 2 Register */
#define PCIE_LCSR2_TGT_LSPEED __BITS(3, 0) /* Target Link Speed */
#define PCIE_LCSR2_ENT_COMPL __BIT(4) /* Enter Compliance */
@@ -1041,6 +1051,15 @@ typedef u_int8_t pci_revision_t;
#define PCIE_LCSR2_EQP2_SUC __BIT(3 + 16) /* Equaliz Phase 2 Successful */
#define PCIE_LCSR2_EQP3_SUC __BIT(4 + 16) /* Equaliz Phase 3 Successful */
#define PCIE_LCSR2_LNKEQ_REQ __BIT(5 + 16) /* Link Equalization Request */
+#define PCIE_LCSR2_RETIMERPD __BIT(6 + 16) /* Retimer Presence Detected */
+#define PCIE_LCSR2_DSCOMPN __BITS(30, 28) /* Downstream Component Pres. */
+#define PCIE_DSCOMPN_DOWN_NOTDETERM 0x00 /* LD: Presence Not Determin.*/
+#define PCIE_DSCOMPN_DOWN_NOTPRES 0x01 /* LD: Component Not Present */
+#define PCIE_DSCOMPN_DOWN_PRES 0x02 /* LD: Component Present */
+ /* 0x03 is reserved */
+#define PCIE_DSCOMPN_UP_PRES 0x04 /* LU: Component Present */
+#define PCIE_DSCOMPN_UP_PRES_DRS 0x05 /* LU: Comp Pres and DRS RCV */
+#define PCIE_LCSR2_DRSRCV __BIT(15 + 16) /* DRS Message Received */
#define PCIE_SLCAP2 0x34 /* Slot Capabilities 2 Register */
#define PCIE_SLCSR2 0x38 /* Slot Control & Status 2 Register */
@@ -1409,6 +1428,7 @@ struct pci_rom {
#define PCI_AER_UC_MC_BLOCKED_TLP __BIT(23)
#define PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED __BIT(24)
#define PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR __BIT(25)
+#define PCI_AER_UC_POISONTLP_EGRESS_BLOCKED __BIT(26)
#define PCI_AER_UC_MASK 0x08 /* Uncorrectable Error Mask Register */
/* Shares bits with UC_STATUS */
#define PCI_AER_UC_SEVERITY 0x0c /* Uncorrectable Error Severity Reg. */
@@ -1435,6 +1455,7 @@ struct pci_rom {
#define PCI_AER_MULT_HDR_CAPABLE __BIT(9)
#define PCI_AER_MULT_HDR_ENABLE __BIT(10)
#define PCI_AER_TLP_PREFIX_LOG_PRESENT __BIT(11)
+#define PCI_AER_COMPTOUTPRFXHDRLOG_CAP __BIT(12)
#define PCI_AER_HEADER_LOG 0x1c /* Header Log Register */
#define PCI_AER_ROOTERR_CMD 0x2c /* Root Error Command Register */
/* Only for root complex ports */
@@ -1453,7 +1474,7 @@ struct pci_rom {
#define PCI_AER_ROOTERR_INT_MESSAGE __BITS(31, 27)
#define PCI_AER_ROOTERR_INT_MESSAGE_S 27
#define PCI_AER_ROOTERR_INT_MESSAGE_M 0x1f
-#define PCI_AER_ERRSRC_ID 0x34 /* Error Source Identification Register */
+#define PCI_AER_ERRSRC_ID 0x34 /* Error Source Identification Reg. */
#define PCI_AER_ERRSRC_ID_ERR_COR __BITS(15, 0)
#define PCI_AER_ERRSRC_ID_ERR_COR_S 0
#define PCI_AER_ERRSRC_ID_ERR_COR_M 0xffff
@@ -1799,6 +1820,7 @@ struct pci_rom {
#define PCI_SECPCIE_LCTL3 0x04 /* Link Control 3 */
#define PCI_SECPCIE_LCTL3_PERFEQ __BIT(0) /* Perform Equalization */
#define PCI_SECPCIE_LCTL3_LINKEQREQ_IE __BIT(1) /* Link Eq. Req. Int. Ena. */
+#define PCI_SECPCIE_LCTL3_ELSKPOSGENV __BITS(15, 9) /* En. Lo. SKP OS Gen V*/
#define PCI_SECPCIE_LANEERR_STA 0x08 /* Lane Error Status */
#define PCI_SECPCIE_EQCTLS 0x0c /* Equalization Control [0-maxlane] */
#define PCI_SECPCIE_EQCTL(x) (PCI_SECPCIE_EQCTLS + ((x) * 2))
