Module Name: src
Committed By: joerg
Date: Fri Jan 15 12:09:15 UTC 2016
Modified Files:
src/sys/dev/marvell: gtbrgreg.h gtmpscreg.h gtsdmareg.h
Log Message:
Switch to generic __BIT/__BITS macro, which doesn't depend on
left-shifting negative values.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/dev/marvell/gtbrgreg.h
cvs rdiff -u -r1.4 -r1.5 src/sys/dev/marvell/gtmpscreg.h
cvs rdiff -u -r1.5 -r1.6 src/sys/dev/marvell/gtsdmareg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/marvell/gtbrgreg.h
diff -u src/sys/dev/marvell/gtbrgreg.h:1.2 src/sys/dev/marvell/gtbrgreg.h:1.3
--- src/sys/dev/marvell/gtbrgreg.h:1.2 Wed Apr 28 13:51:56 2010
+++ src/sys/dev/marvell/gtbrgreg.h Fri Jan 15 12:09:15 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: gtbrgreg.h,v 1.2 2010/04/28 13:51:56 kiyohara Exp $ */
+/* $NetBSD: gtbrgreg.h,v 1.3 2016/01/15 12:09:15 joerg Exp $ */
/*
* Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
@@ -46,13 +46,6 @@
#ifndef _GTBRGREG_H
#define _GTBRGREG_H
-#ifndef BIT
-#define BIT(bitno) (1U << (bitno))
-#endif
-#ifndef BITS
-#define BITS(hi, lo) ((~((~0) << ((hi) + 1))) & ((~0) << (lo)))
-#endif
-
#define GTBRG_NCHAN 3 /* Number of MPSC channels */
/*******************************************************************************
@@ -71,10 +64,10 @@
/*
* BRG Configuration Register bits
*/
-#define BRG_BCR_CDV BITS(15,0) /* Count Down Value */
-#define BRG_BCR_EN BIT(16) /* Enable BRG */
-#define BRG_BCR_RST BIT(17) /* Reset BRG */
-#define BRG_BCR_CLKS_MASK BITS(22,18) /* Clock Source */
+#define BRG_BCR_CDV __BITS(15,0) /* Count Down Value */
+#define BRG_BCR_EN __BIT(16) /* Enable BRG */
+#define BRG_BCR_RST __BIT(17) /* Reset BRG */
+#define BRG_BCR_CLKS_MASK __BITS(22,18) /* Clock Source */
#define BRG_BCR_CLKS_BCLKIN (0 << 18) /* from MPP */
#define BRG_BCR_CLKS_SCLK0 (2 << 18) /* from S0 port */
#define BRG_BCR_CLKS_TSCLK0 (3 << 18) /* from S0 port */
@@ -82,18 +75,18 @@
#define BRG_BCR_CLKS_TSCLK1 (7 << 18) /* from S1 port */
#define BRG_BCR_CLKS_TCLK (8 << 18) /* "Tclk" ??? */
/* all other values resvd. */
-#define BRG_BCR_RES BITS(31,23)
+#define BRG_BCR_RES __BITS(31,23)
/*
* BRG Baud Tuning Register bits
*/
-#define BRG_BTR_CUV BITS(15,0) /* Count Up Value */
-#define BRG_BTR_RES BITS(31,16)
+#define BRG_BTR_CUV __BITS(15,0) /* Count Up Value */
+#define BRG_BTR_RES __BITS(31,16)
/*
* BRG Cause and Mask interrupt Register bits
*/
-#define BRG_INTR_BTR0 BIT(0) /* Baud Tuning 0 irpt. */
-#define BRG_INTR_BTR1 BIT(1) /* Baud Tuning 1 irpt. */
-#define BRG_INTR_BTR2 BIT(2) /* Baud Tuning 2 irpt. */
-#define BRG_INTR_RES BITS(31,3)
+#define BRG_INTR_BTR0 __BIT(0) /* Baud Tuning 0 irpt. */
+#define BRG_INTR_BTR1 __BIT(1) /* Baud Tuning 1 irpt. */
+#define BRG_INTR_BTR2 __BIT(2) /* Baud Tuning 2 irpt. */
+#define BRG_INTR_RES __BITS(31,3)
#endif /* _GTBRGREG_H */
Index: src/sys/dev/marvell/gtmpscreg.h
diff -u src/sys/dev/marvell/gtmpscreg.h:1.4 src/sys/dev/marvell/gtmpscreg.h:1.5
--- src/sys/dev/marvell/gtmpscreg.h:1.4 Wed Apr 28 13:51:56 2010
+++ src/sys/dev/marvell/gtmpscreg.h Fri Jan 15 12:09:15 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: gtmpscreg.h,v 1.4 2010/04/28 13:51:56 kiyohara Exp $ */
+/* $NetBSD: gtmpscreg.h,v 1.5 2016/01/15 12:09:15 joerg Exp $ */
/*
* Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
@@ -46,13 +46,6 @@
#ifndef _GTMPSCREG_H
#define _GTMPSCREG_H
-#ifndef BIT
-#define BIT(bitno) (1U << (bitno))
-#endif
-#ifndef BITS
-#define BITS(hi, lo) ((~((~0) << ((hi) + 1))) & ((~0) << (lo)))
-#endif
-
#define GTMPSC_BASE(u) (MPSC0_BASE + ((u) << 12))
#define GTMPSC_SIZE 0x1000
@@ -86,11 +79,11 @@
#define GTMPSC_MRR_PORT0 0 /* serial port #0 */
#define GTMPSC_MRR_NONE 7 /* unconnected */
/* all other "routes" resvd. */
-#define GTMPSC_MRR_MR0_MASK BITS(2,0) /* routing mask for MPSC0 */
-#define GTMPSC_MRR_RESa BITS(5,3)
-#define GTMPSC_MRR_MR1_MASK BITS(8,6) /* routing mask for MPSC1 */
-#define GTMPSC_MRR_RESb BITS(30,9)
-#define GTMPSC_MRRE_DSC BIT(31) /* "Don't Stop Clock" */
+#define GTMPSC_MRR_MR0_MASK __BITS(2,0) /* routing mask for MPSC0 */
+#define GTMPSC_MRR_RESa __BITS(5,3)
+#define GTMPSC_MRR_MR1_MASK __BITS(8,6) /* routing mask for MPSC1 */
+#define GTMPSC_MRR_RESb __BITS(30,9)
+#define GTMPSC_MRRE_DSC __BIT(31) /* "Don't Stop Clock" */
#define GTMPSC_MRR_RES (GTMPSC_MRR_RESa|GTMPSC_MRR_RESb)
/*
* MPSC Clock Routing Register bits
@@ -106,92 +99,92 @@
#define GTMPSC_CRR(u, v) ((v) << GTMPSC_CRR_SHIFT(u))
#define GTMPSC_CRR_SHIFT(u) ((u) * 8)
#define GTMPSC_CRR_MASK 0xf
-#define GTMPSC_CRR_RESa BITS(7,4)
-#define GTMPSC_CRR_RESb BITS(31,12)
+#define GTMPSC_CRR_RESa __BITS(7,4)
+#define GTMPSC_CRR_RESb __BITS(31,12)
#define GTMPSC_CRR_RES (GTMPSC_CRR_RESa|GTMPSC_CRR_RESb)
/*
* MPSC Main Configuration Register LO bits
*/
-#define GTMPSC_MMCR_LO_MODE_MASK BITS(2,0)
+#define GTMPSC_MMCR_LO_MODE_MASK __BITS(2,0)
#define GTMPSC_MMCR_LO_MODE_UART (0x4 << 0) /* UART mode */
-#define GTMPSC_MMCR_LO_TTX BIT(3) /* Transparent TX */
-#define GTMPSC_MMCR_LO_TRX BIT(4) /* Transparent RX */
-#define GTMPSC_MMCR_LO_RESa BIT(5)
-#define GTMPSC_MMCR_LO_ET BIT(6) /* Enable TX */
-#define GTMPSC_MMCR_LO_ER BIT(7) /* Enable RX */
-#define GTMPSC_MMCR_LO_LPBK_MASK BITS(9,8) /* Loop Back */
+#define GTMPSC_MMCR_LO_TTX __BIT(3) /* Transparent TX */
+#define GTMPSC_MMCR_LO_TRX __BIT(4) /* Transparent RX */
+#define GTMPSC_MMCR_LO_RESa __BIT(5)
+#define GTMPSC_MMCR_LO_ET __BIT(6) /* Enable TX */
+#define GTMPSC_MMCR_LO_ER __BIT(7) /* Enable RX */
+#define GTMPSC_MMCR_LO_LPBK_MASK __BITS(9,8) /* Loop Back */
#define GTMPSC_MMCR_LO_LPBK_NONE (0 << 8) /* Normal (non-loop) */
#define GTMPSC_MMCR_LO_LPBK_LOOP (1 << 8) /* Loop Back */
#define GTMPSC_MMCR_LO_LPBK_ECHO (2 << 8) /* Echo */
#define GTMPSC_MMCR_LO_LPBK_LBE (3 << 8) /* Loop Back and Echo */
-#define GTMPSC_MMCR_LO_NLM BIT(10) /* Null Modem */
-#define GTMPSC_MMCR_LO_RESb BIT(11)
-#define GTMPSC_MMCR_LO_TSYN BIT(12) /* Transmitter sync to Rcvr. */
-#define GTMPSC_MMCR_LO_RESc BIT(13)
-#define GTMPSC_MMCR_LO_TSNS_MASK BITS(15,14) /* Transmit Sense */
+#define GTMPSC_MMCR_LO_NLM __BIT(10) /* Null Modem */
+#define GTMPSC_MMCR_LO_RESb __BIT(11)
+#define GTMPSC_MMCR_LO_TSYN __BIT(12) /* Transmitter sync to Rcvr. */
+#define GTMPSC_MMCR_LO_RESc __BIT(13)
+#define GTMPSC_MMCR_LO_TSNS_MASK __BITS(15,14) /* Transmit Sense */
#define GTMPSC_MMCR_LO_TSNS_INF (0 << 14) /* Infinite */
-#define GTMPSC_MMCR_LO_TIDL BIT(16) /* TX Idles */
-#define GTMPSC_MMCR_LO_RTSM BIT(17) /* RTS Mode */
-#define GTMPSC_MMCR_LO_RESd BIT(18)
-#define GTMPSC_MMCR_LO_CTSS BIT(19) /* CTS Sampling mode */
-#define GTMPSC_MMCR_LO_CDS BIT(20) /* CD Sampling mode */
-#define GTMPSC_MMCR_LO_CTSM BIT(21) /* CTS operating Mode */
-#define GTMPSC_MMCR_LO_CDM BIT(22) /* CD operating Mode */
-#define GTMPSC_MMCR_LO_CRCM_MASK BITS(25,23) /* CRC Mode */
+#define GTMPSC_MMCR_LO_TIDL __BIT(16) /* TX Idles */
+#define GTMPSC_MMCR_LO_RTSM __BIT(17) /* RTS Mode */
+#define GTMPSC_MMCR_LO_RESd __BIT(18)
+#define GTMPSC_MMCR_LO_CTSS __BIT(19) /* CTS Sampling mode */
+#define GTMPSC_MMCR_LO_CDS __BIT(20) /* CD Sampling mode */
+#define GTMPSC_MMCR_LO_CTSM __BIT(21) /* CTS operating Mode */
+#define GTMPSC_MMCR_LO_CDM __BIT(22) /* CD operating Mode */
+#define GTMPSC_MMCR_LO_CRCM_MASK __BITS(25,23) /* CRC Mode */
#define GTMPSC_MMCR_LO_CRCM_NONE (0 << 23) /* CRC Mode */
-#define GTMPSC_MMCR_LO_RESe BITS(27,26)
-#define GTMPSC_MMCR_LO_TRVD BIT(28) /* Transmit Reverse Data */
-#define GTMPSC_MMCR_LO_RRVD BIT(29) /* Receive Reverse Data */
-#define GTMPSC_MMCR_LO_RESf BIT(30)
-#define GTMPSC_MMCR_LO_GDE BIT(31) /* Glitch Detect Enable */
+#define GTMPSC_MMCR_LO_RESe __BITS(27,26)
+#define GTMPSC_MMCR_LO_TRVD __BIT(28) /* Transmit Reverse Data */
+#define GTMPSC_MMCR_LO_RRVD __BIT(29) /* Receive Reverse Data */
+#define GTMPSC_MMCR_LO_RESf __BIT(30)
+#define GTMPSC_MMCR_LO_GDE __BIT(31) /* Glitch Detect Enable */
#define GTMPSC_MMCR_LO_RES \
(GTMPSC_MMCR_LO_RESa|GTMPSC_MMCR_LO_RESb|GTMPSC_MMCR_LO_RESc \
|GTMPSC_MMCR_LO_RESd|GTMPSC_MMCR_LO_RESe|GTMPSC_MMCR_LO_RESf)
/*
* MPSC Main Configuration Register HI bits
*/
-#define GTMPSC_MMCR_HI_TCI BIT(0) /* TX Clock Invert */
-#define GTMPSC_MMCR_HI_TINV BIT(1) /* TX Bitstream Inversion */
-#define GTMPSC_MMCR_HI_TPL BITS(4,2) /* TX Preable Length */
+#define GTMPSC_MMCR_HI_TCI __BIT(0) /* TX Clock Invert */
+#define GTMPSC_MMCR_HI_TINV __BIT(1) /* TX Bitstream Inversion */
+#define GTMPSC_MMCR_HI_TPL __BITS(4,2) /* TX Preable Length */
#define GTMPSC_MMCR_HI_TPL_NONE 0 /* no TX Preable (default) */
#define GTMPSC_MMCR_HI_TPL_16 (6 << 2) /* 16 byte preamble */
-#define GTMPSC_MMCR_HI_TPPT_MASK BITS(8,5) /* TX Preable Pattern */
+#define GTMPSC_MMCR_HI_TPPT_MASK __BITS(8,5) /* TX Preable Pattern */
#define GTMPSC_MMCR_HI_TPPT_NONE (0 << 5) /* TX Preable Pattern */
-#define GTMPSC_MMCR_HI_TCDV_MASK BITS(10,9) /* TX Clock Divide */
+#define GTMPSC_MMCR_HI_TCDV_MASK __BITS(10,9) /* TX Clock Divide */
#define GTMPSC_MMCR_HI_TCDV_1X (0 << 9) /* 1x clock mode */
#define GTMPSC_MMCR_HI_TCDV_8X (1 << 9) /* 8x clock mode */
#define GTMPSC_MMCR_HI_TCDV_16X (2 << 9) /* 16x clock mode */
#define GTMPSC_MMCR_HI_TCDV_32X (3 << 9) /* 32x clock mode */
-#define GTMPSC_MMCR_HI_TDEC_MASK BITS(13,11) /* TX Encoder */
+#define GTMPSC_MMCR_HI_TDEC_MASK __BITS(13,11) /* TX Encoder */
#define GTMPSC_MMCR_HI_TDEC_NRZ (0 << 9) /* NRZ (default) */
#define GTMPSC_MMCR_HI_TDEC_NRZI (1 << 9) /* NRZI (mark) */
#define GTMPSC_MMCR_HI_TDEC_FM0 (2 << 9) /* FM0 */
#define GTMPSC_MMCR_HI_TDEC_MAN (4 << 9) /* Manchester */
#define GTMPSC_MMCR_HI_TDEC_DMAN (6 << 9) /* Differential Manchester */
/* all other values rsvd. */
-#define GTMPSC_MMCR_HI_RESa BITS(15,14)
-#define GTMPSC_MMCR_HI_RINV BIT(16) /* RX Bitstream Inversion */
-#define GTMPSC_MMCR_HI_GDW BITS(20,17) /* Clock Glitch Width */
-#define GTMPSC_MMCR_HI_RESb BIT(21)
-#define GTMPSC_MMCR_HI_RDW BIT(22) /* Reveive Data Width */
-#define GTMPSC_MMCR_HI_RSYL_MASK BITS(24,23) /* Reveive Sync Width */
+#define GTMPSC_MMCR_HI_RESa __BITS(15,14)
+#define GTMPSC_MMCR_HI_RINV __BIT(16) /* RX Bitstream Inversion */
+#define GTMPSC_MMCR_HI_GDW __BITS(20,17) /* Clock Glitch Width */
+#define GTMPSC_MMCR_HI_RESb __BIT(21)
+#define GTMPSC_MMCR_HI_RDW __BIT(22) /* Reveive Data Width */
+#define GTMPSC_MMCR_HI_RSYL_MASK __BITS(24,23) /* Reveive Sync Width */
#define GTMPSC_MMCR_HI_RSYL_EXT (0 << 23) /* External sync */
#define GTMPSC_MMCR_HI_RSYL_4BIT (1 << 23) /* 4-bit sync */
#define GTMPSC_MMCR_HI_RSYL_8BIT (2 << 23) /* 8-bit sync */
#define GTMPSC_MMCR_HI_RSYL_16BIT (3 << 23) /* 16-bit sync */
-#define GTMPSC_MMCR_HI_RCDV_MASK BITS(26,25) /* Receive Clock Divider */
+#define GTMPSC_MMCR_HI_RCDV_MASK __BITS(26,25) /* Receive Clock Divider */
#define GTMPSC_MMCR_HI_RCDV_1X (0 << 25) /* 1x clock mode (default) */
#define GTMPSC_MMCR_HI_RCDV_8X (1 << 25) /* 8x clock mode (default) */
#define GTMPSC_MMCR_HI_RCDV_16X (2 << 25) /* 16x clock mode (default) */
#define GTMPSC_MMCR_HI_RCDV_32X (3 << 25) /* 16x clock mode (default) */
-#define GTMPSC_MMCR_HI_RENC_MASK BITS(29,27) /* Receive Encoder */
+#define GTMPSC_MMCR_HI_RENC_MASK __BITS(29,27) /* Receive Encoder */
#define GTMPSC_MMCR_HI_RENC_NRZ (0 << 27) /* NRZ (default) */
#define GTMPSC_MMCR_HI_RENC_NRZI (1 << 27) /* NRZI */
#define GTMPSC_MMCR_HI_RENC_FM0 (2 << 27) /* FM0 */
#define GTMPSC_MMCR_HI_RENC_MAN (4 << 27) /* Manchester */
#define GTMPSC_MMCR_HI_RENC_DMAN (6 << 27) /* Differential Manchester */
/* all other values rsvd. */
-#define GTMPSC_MMCR_HI_SEDG_MASK BITS(31,30) /* Sync Clock Edge */
+#define GTMPSC_MMCR_HI_SEDG_MASK __BITS(31,30) /* Sync Clock Edge */
#define GTMPSC_MMCR_HI_SEDG_BOTH (0 << 30) /* rising and falling (dflt) */
#define GTMPSC_MMCR_HI_SEDG_RISE (1 << 30) /* rising edge */
#define GTMPSC_MMCR_HI_SEDG_FALL (2 << 30) /* falling edge */
@@ -201,61 +194,61 @@
*
* XXX these belong in sdmareg.h ?
*/
-#define SDMA_CSR_RX_PE BIT(0) /* Parity Error */
-#define SDMA_CSR_RX_CDL BIT(1) /* Carrier Detect Loss */
-#define SDMA_CSR_RX_RESa BIT(2)
-#define SDMA_CSR_RX_FR BIT(3) /* Framing Error */
-#define SDMA_CSR_RX_RESb BITS(5,4)
-#define SDMA_CSR_RX_OR BIT(6) /* Data Overrun */
-#define SDMA_CSR_RX_RESc BITS(8,7)
-#define SDMA_CSR_RX_BR BIT(9) /* Break Received */
-#define SDMA_CSR_RX_MI BIT(10) /* Max Idle */
-#define SDMA_CSR_RX_ADDR BIT(11) /* Address */
-#define SDMA_CSR_RX_AMATCH BIT(12) /* Address match */
-#define SDMA_CSR_RX_CT BIT(13) /* Transparency Control char */
-#define SDMA_CSR_RX_C BIT(14) /* Control char */
-#define SDMA_CSR_RX_ES BIT(15) /* Error Summary */
-#define SDMA_CSR_RX_L BIT(16) /* Last */
-#define SDMA_CSR_RX_F BIT(17) /* First */
-#define SDMA_CSR_RX_RESd BITS(22,18)
-#define SDMA_CSR_RX_EI BIT(23) /* Enable Interrupt */
-#define SDMA_CSR_RX_RESe BITS(29,24)
-#define SDMA_CSR_RX_AUTO BIT(30) /* Auto Mode */
-#define SDMA_CSR_RX_OWN BIT(31) /* Owner */
+#define SDMA_CSR_RX_PE __BIT(0) /* Parity Error */
+#define SDMA_CSR_RX_CDL __BIT(1) /* Carrier Detect Loss */
+#define SDMA_CSR_RX_RESa __BIT(2)
+#define SDMA_CSR_RX_FR __BIT(3) /* Framing Error */
+#define SDMA_CSR_RX_RESb __BITS(5,4)
+#define SDMA_CSR_RX_OR __BIT(6) /* Data Overrun */
+#define SDMA_CSR_RX_RESc __BITS(8,7)
+#define SDMA_CSR_RX_BR __BIT(9) /* Break Received */
+#define SDMA_CSR_RX_MI __BIT(10) /* Max Idle */
+#define SDMA_CSR_RX_ADDR __BIT(11) /* Address */
+#define SDMA_CSR_RX_AMATCH __BIT(12) /* Address match */
+#define SDMA_CSR_RX_CT __BIT(13) /* Transparency Control char */
+#define SDMA_CSR_RX_C __BIT(14) /* Control char */
+#define SDMA_CSR_RX_ES __BIT(15) /* Error Summary */
+#define SDMA_CSR_RX_L __BIT(16) /* Last */
+#define SDMA_CSR_RX_F __BIT(17) /* First */
+#define SDMA_CSR_RX_RESd __BITS(22,18)
+#define SDMA_CSR_RX_EI __BIT(23) /* Enable Interrupt */
+#define SDMA_CSR_RX_RESe __BITS(29,24)
+#define SDMA_CSR_RX_AUTO __BIT(30) /* Auto Mode */
+#define SDMA_CSR_RX_OWN __BIT(31) /* Owner */
#define SDMA_CSR_RX_RES (SDMA_CSR_RX_RESa|SDMA_CSR_RX_RESb|SDMA_CSR_RX_RESc \
|SDMA_CSR_RX_RESd|SDMA_CSR_RX_RESe)
/*
* SDMAx Command/Status Register bits for UART Mode, TX
*/
-#define SDMA_CSR_TX_RESa BIT(0)
-#define SDMA_CSR_TX_CTSL BIT(1) /* CTS Loss */
-#define SDMA_CSR_TX_RESb BITS(14,2)
-#define SDMA_CSR_TX_ES BIT(15) /* Error Summary */
-#define SDMA_CSR_TX_L BIT(16) /* Last */
-#define SDMA_CSR_TX_F BIT(17) /* First */
-#define SDMA_CSR_TX_P BIT(18) /* Preamble */
-#define SDMA_CSR_TX_ADDR BIT(19) /* Address */
-#define SDMA_CSR_TX_NS BIT(20) /* No Stop Bit */
-#define SDMA_CSR_TX_RESc BITS(22,21)
-#define SDMA_CSR_TX_EI BIT(23) /* Enable Interrupt */
-#define SDMA_CSR_TX_RESd BITS(29,24)
-#define SDMA_CSR_TX_AUTO BIT(30) /* Auto Mode */
-#define SDMA_CSR_TX_OWN BIT(31) /* Owner */
+#define SDMA_CSR_TX_RESa __BIT(0)
+#define SDMA_CSR_TX_CTSL __BIT(1) /* CTS Loss */
+#define SDMA_CSR_TX_RESb __BITS(14,2)
+#define SDMA_CSR_TX_ES __BIT(15) /* Error Summary */
+#define SDMA_CSR_TX_L __BIT(16) /* Last */
+#define SDMA_CSR_TX_F __BIT(17) /* First */
+#define SDMA_CSR_TX_P __BIT(18) /* Preamble */
+#define SDMA_CSR_TX_ADDR __BIT(19) /* Address */
+#define SDMA_CSR_TX_NS __BIT(20) /* No Stop Bit */
+#define SDMA_CSR_TX_RESc __BITS(22,21)
+#define SDMA_CSR_TX_EI __BIT(23) /* Enable Interrupt */
+#define SDMA_CSR_TX_RESd __BITS(29,24)
+#define SDMA_CSR_TX_AUTO __BIT(30) /* Auto Mode */
+#define SDMA_CSR_TX_OWN __BIT(31) /* Owner */
#define SDMA_CSR_TX_RES \
(SDMA_CSR_TX_RESa|SDMA_CSR_TX_RESb|SDMA_CSR_TX_RESc|SDMA_CSR_TX_RESd)
/*
* MPSCx Protocol Configuration Register for UART Mode
*/
-#define GTMPSC_MPCR_RESa BITS(5,0)
-#define GTMPSC_MPCR_DRT BIT(6) /* Disable Rx on Tx */
-#define GTMPSC_MPCR_ISO BIT(7) /* Isochronous Mode */
-#define GTMPSC_MPCR_RZS BIT(8) /* Rx Zero Stop Bit(s) */
-#define GTMPSC_MPCR_FRZ BIT(9) /* Freeze Tx */
-#define GTMPSC_MPCR_UM_MASK BITS(11,10) /* UART Mode mask */
+#define GTMPSC_MPCR_RESa __BITS(5,0)
+#define GTMPSC_MPCR_DRT __BIT(6) /* Disable Rx on Tx */
+#define GTMPSC_MPCR_ISO __BIT(7) /* Isochronous Mode */
+#define GTMPSC_MPCR_RZS __BIT(8) /* Rx Zero Stop Bit(s) */
+#define GTMPSC_MPCR_FRZ __BIT(9) /* Freeze Tx */
+#define GTMPSC_MPCR_UM_MASK __BITS(11,10) /* UART Mode mask */
#define GTMPSC_MPCR_UM_NORM (0 << 10) /* Normal UART Mode */
#define GTMPSC_MPCR_UM_MDROP (1 << 10) /* Multi-Drop UART Mode */
/* other values are resvd. */
-#define GTMPSC_MPCR_CLMASK BITS(13,12) /* Character Length mask */
+#define GTMPSC_MPCR_CLMASK __BITS(13,12) /* Character Length mask */
#define GTMPSC_MPCR_CL_5 (0 << 12) /* 5 data bits */
#define GTMPSC_MPCR_CL_6 (1 << 12) /* 6 data bits */
#define GTMPSC_MPCR_CL_7 (2 << 12) /* 7 data bits */
@@ -263,42 +256,42 @@
#define GTMPSC_MPCR_SBL_1 (0 << 14) /* 1 stop bit */
#define GTMPSC_MPCR_SBL_2 (1 << 14) /* 2 stop bits */
#define GTMPSC_MPCR_FLC_NORM 0x0 /* Normal Flow Ctl mode */
-#define GTMPSC_MPCR_FLC_ASYNC BIT(15) /* Asynchronous Flow Ctl mode */
-#define GTMPSC_MPCR_RESb BITS(31,16)
+#define GTMPSC_MPCR_FLC_ASYNC __BIT(15) /* Asynchronous Flow Ctl mode */
+#define GTMPSC_MPCR_RESb __BITS(31,16)
#define GTMPSC_MPCR_RES (GTMPSC_MPCR_RESa|GTMPSC_MPCR_RESb)
/*
* MPSC Channel Register 1 for UART Mode "Break/Stuff"
*/
-#define GTMPSC_CHR1_TCS BITS(7,0) /* Constrol Stuff Character */
-#define GTMPSC_CHR1_BRK BITS(23,16) /* Break Count */
-#define GTMPSC_CHR1_RES BITS(15,8)|BITS(31,24)
+#define GTMPSC_CHR1_TCS __BITS(7,0) /* Constrol Stuff Character */
+#define GTMPSC_CHR1_BRK __BITS(23,16) /* Break Count */
+#define GTMPSC_CHR1_RES __BITS(15,8)|__BITS(31,24)
/*
* MPSC Channel Register 2 for UART Mode "Command"
*/
-#define GTMPSC_CHR2_RESa BIT(0)
-#define GTMPSC_CHR2_TEV BIT(1) /* Tx Enb. Vert. Redundancy */
-#define GTMPSC_CHR2_TPM_MASK BITS(3,2) /* Tx Parity Mode mask */
+#define GTMPSC_CHR2_RESa __BIT(0)
+#define GTMPSC_CHR2_TEV __BIT(1) /* Tx Enb. Vert. Redundancy */
+#define GTMPSC_CHR2_TPM_MASK __BITS(3,2) /* Tx Parity Mode mask */
#define GTMPSC_CHR2_TPM_ODD (0 << 2) /* Odd Tx Parity */
#define GTMPSC_CHR2_TPM_LOW (1 << 2) /* Low (always 0) Tx Parity */
#define GTMPSC_CHR2_TPM_EVEN (2 << 2) /* Even Tx Parity */
#define GTMPSC_CHR2_TPM_HIGH (3 << 2) /* High (always 1) Tx Parity */
-#define GTMPSC_CHR2_RESb BITS(6,4)
-#define GTMPSC_CHR2_TXABORT BIT(7) /* Tx Abort */
-#define GTMPSC_CHR2_RESc BIT(8)
-#define GTMPSC_CHR2_TCS BIT(9) /* Tx TCS Char */
-#define GTMPSC_CHR2_RESd BITS(16,10)
-#define GTMPSC_CHR2_REC BIT(17) /* Rx Enb. Vert. Redundancy */
-#define GTMPSC_CHR2_RPM_MASK BITS(19,18) /* Rx Parity Mode mask */
+#define GTMPSC_CHR2_RESb __BITS(6,4)
+#define GTMPSC_CHR2_TXABORT __BIT(7) /* Tx Abort */
+#define GTMPSC_CHR2_RESc __BIT(8)
+#define GTMPSC_CHR2_TCS __BIT(9) /* Tx TCS Char */
+#define GTMPSC_CHR2_RESd __BITS(16,10)
+#define GTMPSC_CHR2_REC __BIT(17) /* Rx Enb. Vert. Redundancy */
+#define GTMPSC_CHR2_RPM_MASK __BITS(19,18) /* Rx Parity Mode mask */
#define GTMPSC_CHR2_RPM_ODD (0 << 18) /* Odd Rx Parity */
#define GTMPSC_CHR2_RPM_LOW (1 << 18) /* Low (always 0) Rx Parity */
#define GTMPSC_CHR2_RPM_EVEN (2 << 18) /* Even Rx Parity */
#define GTMPSC_CHR2_RPM_HIGH (3 << 18) /* High (always 1) Rx Parity */
-#define GTMPSC_CHR2_RESe BITS(22,20)
-#define GTMPSC_CHR2_RXABORT BIT(23) /* Rx Abort */
-#define GTMPSC_CHR2_RESf BIT(24)
-#define GTMPSC_CHR2_CRD BIT(25) /* Close RX Descriptor */
-#define GTMPSC_CHR2_RESg BITS(30,26)
-#define GTMPSC_CHR2_EH BIT(31) /* Enter Hunt */
+#define GTMPSC_CHR2_RESe __BITS(22,20)
+#define GTMPSC_CHR2_RXABORT __BIT(23) /* Rx Abort */
+#define GTMPSC_CHR2_RESf __BIT(24)
+#define GTMPSC_CHR2_CRD __BIT(25) /* Close RX Descriptor */
+#define GTMPSC_CHR2_RESg __BITS(30,26)
+#define GTMPSC_CHR2_EH __BIT(31) /* Enter Hunt */
#define GTMPSC_CHR2_RES \
(GTMPSC_CHR2_RESa|GTMPSC_CHR2_RESb|GTMPSC_CHR2_RESc| \
GTMPSC_CHR2_RESd|GTMPSC_CHR2_RESe|GTMPSC_CHR2_RESf| \
@@ -306,51 +299,51 @@
/*
* MPSC Channel Register 3 for UART Mode "Max Idle"
*/
-#define GTMPSC_CHR3_MIR BITS(15,0) /* Max Idle Char count */
-#define GTMPSC_CHR3_RES BITS(31,16)
+#define GTMPSC_CHR3_MIR __BITS(15,0) /* Max Idle Char count */
+#define GTMPSC_CHR3_RES __BITS(31,16)
/*
* MPSC Channel Register 4 for UART Mode "Control Filtering"
*/
-#define GTMPSC_CHR4_CFR BITS(7,0) /* Control bit compare enable */
-#define GTMPSC_CHR4_RES BITS(31,8)
+#define GTMPSC_CHR4_CFR __BITS(7,0) /* Control bit compare enable */
+#define GTMPSC_CHR4_RES __BITS(31,8)
/*
* MPSC Channel Registers 5..8 for UART Mode "UART Control Character"
*
* NOTE: two 16 bit CHRCC fields exist in each of Channel Registers 5..8
*/
#define GTMPSC_CHRCC_SHIFT 16
-#define GTMPSC_CHRCC_CHAR BITS(7,0) /* the control character */
-#define GTMPSC_CHRCC_RES BITS(11,8)
-#define GTMPSC_CHRCC_INT BIT(12) /* Interrupt */
-#define GTMPSC_CHRCC_CO BIT(13) /* ISO 3309 Control Octet */
-#define GTMPSC_CHRCC_R BIT(14) /* Reject */
-#define GTMPSC_CHRCC_V BIT(15) /* Valid */
+#define GTMPSC_CHRCC_CHAR __BITS(7,0) /* the control character */
+#define GTMPSC_CHRCC_RES __BITS(11,8)
+#define GTMPSC_CHRCC_INT __BIT(12) /* Interrupt */
+#define GTMPSC_CHRCC_CO __BIT(13) /* ISO 3309 Control Octet */
+#define GTMPSC_CHRCC_R __BIT(14) /* Reject */
+#define GTMPSC_CHRCC_V __BIT(15) /* Valid */
/*
* MPSC Channel Register 9 for UART Mode "Address" (for multidrop operation)
*/
-#define GTMPSC_CHR9_AD1 BITS(7,0) /* address #1 */
-#define GTMPSC_CHR9_RESa BITS(14,8)
-#define GTMPSC_CHR9_MODE1 BIT(15) /* mode #1 */
-#define GTMPSC_CHR9_AD2 BITS(23,16) /* address #2 */
-#define GTMPSC_CHR9_RESb BITS(30,24)
-#define GTMPSC_CHR9_MODE2 BIT(31) /* mode #2 */
+#define GTMPSC_CHR9_AD1 __BITS(7,0) /* address #1 */
+#define GTMPSC_CHR9_RESa __BITS(14,8)
+#define GTMPSC_CHR9_MODE1 __BIT(15) /* mode #1 */
+#define GTMPSC_CHR9_AD2 __BITS(23,16) /* address #2 */
+#define GTMPSC_CHR9_RESb __BITS(30,24)
+#define GTMPSC_CHR9_MODE2 __BIT(31) /* mode #2 */
#define GTMPSC_CHR9_RES (GTMPSC_CHR9_RESa|GTMPSC_CHR9_RESb)
/*
* MPSC Channel Register 10 for UART Mode "Event Status"
*/
-#define GTMPSC_CHR10_CTS BIT(0) /* Clear To Send */
-#define GTMPSC_CHR10_CD BIT(1) /* Carrier Detect */
-#define GTMPSC_CHR10_RESa BIT(2)
-#define GTMPSC_CHR10_TIDLE BIT(3) /* Tx in Idle State */
-#define GTMPSC_CHR10_RESb BIT(4)
-#define GTMPSC_CHR10_RHS BIT(5) /* Rx in HUNT State */
-#define GTMPSC_CHR10_RESc BIT(6)
-#define GTMPSC_CHR10_RLS BIT(7) /* Rx Line STatus */
-#define GTMPSC_CHR10_RESd BITS(10,8)
-#define GTMPSC_CHR10_RLIDL BIT(11) /* Rx IDLE Line */
-#define GTMPSC_CHR10_RESe BITS(15,12)
-#define GTMPSC_CHR10_RCRn BITS(23,16) /* Received Control Char # */
-#define GTMPSC_CHR10_RESf BITS(31,24)
+#define GTMPSC_CHR10_CTS __BIT(0) /* Clear To Send */
+#define GTMPSC_CHR10_CD __BIT(1) /* Carrier Detect */
+#define GTMPSC_CHR10_RESa __BIT(2)
+#define GTMPSC_CHR10_TIDLE __BIT(3) /* Tx in Idle State */
+#define GTMPSC_CHR10_RESb __BIT(4)
+#define GTMPSC_CHR10_RHS __BIT(5) /* Rx in HUNT State */
+#define GTMPSC_CHR10_RESc __BIT(6)
+#define GTMPSC_CHR10_RLS __BIT(7) /* Rx Line STatus */
+#define GTMPSC_CHR10_RESd __BITS(10,8)
+#define GTMPSC_CHR10_RLIDL __BIT(11) /* Rx IDLE Line */
+#define GTMPSC_CHR10_RESe __BITS(15,12)
+#define GTMPSC_CHR10_RCRn __BITS(23,16) /* Received Control Char # */
+#define GTMPSC_CHR10_RESf __BITS(31,24)
#define GTMPSC_CHR10_RES \
(GTMPSC_CHR10_RESa|GTMPSC_CHR10_RESb|GTMPSC_CHR10_RESc \
|GTMPSC_CHR10_RESd|GTMPSC_CHR10_RESe|GTMPSC_CHR10_RESf)
Index: src/sys/dev/marvell/gtsdmareg.h
diff -u src/sys/dev/marvell/gtsdmareg.h:1.5 src/sys/dev/marvell/gtsdmareg.h:1.6
--- src/sys/dev/marvell/gtsdmareg.h:1.5 Wed Apr 28 13:51:56 2010
+++ src/sys/dev/marvell/gtsdmareg.h Fri Jan 15 12:09:15 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: gtsdmareg.h,v 1.5 2010/04/28 13:51:56 kiyohara Exp $ */
+/* $NetBSD: gtsdmareg.h,v 1.6 2016/01/15 12:09:15 joerg Exp $ */
/*
* Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
@@ -46,13 +46,6 @@
#ifndef _GTSDMAREG_H
#define _GTSDMAREG_H
-#ifndef BIT
-#define BIT(bitno) (1U << (bitno))
-#endif
-#ifndef BITS
-#define BITS(hi, lo) ((~((~0) << ((hi) + 1))) & ((~0) << (lo)))
-#endif
-
#define GTSDMA_BASE(u) ((u) == 0 ? 0x4000 : 0x6000)
#define GTSDMA_SIZE 0x1000
@@ -77,48 +70,48 @@
/*
* SDMA Configuration Register
*/
-#define SDMA_SDC_RFT BIT(0) /* RX FIFO Threshold */
-#define SDMA_SDC_SFM BIT(1) /* Single Frame Mode */
-#define SDMA_SDC_RC_MASK BITS(5,2) /* Re-TX count */
+#define SDMA_SDC_RFT __BIT(0) /* RX FIFO Threshold */
+#define SDMA_SDC_SFM __BIT(1) /* Single Frame Mode */
+#define SDMA_SDC_RC_MASK __BITS(5,2) /* Re-TX count */
#define SDMA_SDC_RC_SHIFT 2
-#define SDMA_SDC_BLMR BIT(6) /* RX Big=0 Lil=1 Endian mode */
-#define SDMA_SDC_BLMT BIT(7) /* TX Big=0 Lil=1 Endian mode */
-#define SDMA_SDC_POVR BIT(8) /* PCI Override */
-#define SDMA_SDC_RIFB BIT(9) /* RX Intr on Frame boundaries */
-#define SDMA_SDC_RESa BITS(11,10)
-#define SDMA_SDC_BSZ_MASK BITS(13,12) /* Maximum Burst Size */
+#define SDMA_SDC_BLMR __BIT(6) /* RX Big=0 Lil=1 Endian mode */
+#define SDMA_SDC_BLMT __BIT(7) /* TX Big=0 Lil=1 Endian mode */
+#define SDMA_SDC_POVR __BIT(8) /* PCI Override */
+#define SDMA_SDC_RIFB __BIT(9) /* RX Intr on Frame boundaries */
+#define SDMA_SDC_RESa __BITS(11,10)
+#define SDMA_SDC_BSZ_MASK __BITS(13,12) /* Maximum Burst Size */
#define SDMA_SDC_BSZ_1x64 (0 << 12) /* 1 64 bit word */
#define SDMA_SDC_BSZ_2x64 (1 << 12) /* 2 64 bit words */
#define SDMA_SDC_BSZ_4x64 (2 << 12) /* 4 64 bit words */
#define SDMA_SDC_BSZ_8x64 (3 << 12) /* 8 64 bit words */
-#define SDMA_SDC_RESb BITS(31,14)
+#define SDMA_SDC_RESb __BITS(31,14)
#define SDMA_SDC_RES (SDMA_SDC_RESa|SDMA_SDC_RESb)
/*
* SDMA Command Register
*/
-#define SDMA_SDCM_RESa BITS(6,0)
-#define SDMA_SDCM_ERD BIT(7) /* Enable RX DMA */
-#define SDMA_SDCM_RESb BITS(14,8)
-#define SDMA_SDCM_AR BIT(15) /* Abort Receive */
-#define SDMA_SDCM_STD BIT(16) /* Stop TX */
-#define SDMA_SDCM_RESc BITS(22,17)
-#define SDMA_SDCM_TXD BIT(23) /* TX Demand */
-#define SDMA_SDCM_RESd BITS(30,24)
-#define SDMA_SDCM_AT BIT(31) /* Abort TX */
+#define SDMA_SDCM_RESa __BITS(6,0)
+#define SDMA_SDCM_ERD __BIT(7) /* Enable RX DMA */
+#define SDMA_SDCM_RESb __BITS(14,8)
+#define SDMA_SDCM_AR __BIT(15) /* Abort Receive */
+#define SDMA_SDCM_STD __BIT(16) /* Stop TX */
+#define SDMA_SDCM_RESc __BITS(22,17)
+#define SDMA_SDCM_TXD __BIT(23) /* TX Demand */
+#define SDMA_SDCM_RESd __BITS(30,24)
+#define SDMA_SDCM_AT __BIT(31) /* Abort TX */
#define SDMA_SDCM_RES \
(SDMA_SDCM_RESa|SDMA_SDCM_RESb|SDMA_SDCM_RESc|SDMA_SDCM_RESd)
/*
* SDMA Interrupt Cause and Mask Register bits
*/
#define U__(bits,u) ((bits) << (((u) % 2) * 8))
-#define SDMA_INTR_RXBUF(u) U__(BIT(0),u) /* SDMA #0 Rx Buffer Return */
-#define SDMA_INTR_RXERR(u) U__(BIT(1),u) /* SDMA #0 Rx Error */
-#define SDMA_INTR_TXBUF(u) U__(BIT(2),u) /* SDMA #0 Tx Buffer Return */
-#define SDMA_INTR_TXEND(u) U__(BIT(3),u) /* SDMA #0 Tx End */
-#define SDMA_INTR_RESa BITS(7,4)
-#define SDMA_INTR_RESb BITS(31,12)
+#define SDMA_INTR_RXBUF(u) U__(__BIT(0),u) /* SDMA #0 Rx Buffer Return */
+#define SDMA_INTR_RXERR(u) U__(__BIT(1),u) /* SDMA #0 Rx Error */
+#define SDMA_INTR_TXBUF(u) U__(__BIT(2),u) /* SDMA #0 Tx Buffer Return */
+#define SDMA_INTR_TXEND(u) U__(__BIT(3),u) /* SDMA #0 Tx End */
+#define SDMA_INTR_RESa __BITS(7,4)
+#define SDMA_INTR_RESb __BITS(31,12)
#define SDMA_INTR_RES (SDMA_INTR_RESa|SDMA_INTR_RESb)
-#define SDMA_U_INTR_MASK(u) U__(BITS(3,0),u)
+#define SDMA_U_INTR_MASK(u) U__(__BITS(3,0),u)
/*******************************************************************************
@@ -140,17 +133,17 @@ typedef struct sdma_desc {
} sdma_desc_t;
#define SDMA_RX_CNT_BCNT_SHIFT 0 /* byte count */
-#define SDMA_RX_CNT_BCNT_MASK BITS(15,0) /* " " */
+#define SDMA_RX_CNT_BCNT_MASK __BITS(15,0) /* " " */
#define SDMA_RX_CNT_BUFSZ_SHIFT 16 /* buffer size */
-#define SDMA_RX_CNT_BUFSZNT_SIZE_MASK BITS(31,19) /* " " */
-#define SDMA_RX_CNT_BUFP_MASK BITS(31,3) /* buffer pointer */
-#define SDMA_RX_CNT_NEXT_MASK BITS(31,4) /* next desc. pointer */
+#define SDMA_RX_CNT_BUFSZNT_SIZE_MASK __BITS(31,19) /* " " */
+#define SDMA_RX_CNT_BUFP_MASK __BITS(31,3) /* buffer pointer */
+#define SDMA_RX_CNT_NEXT_MASK __BITS(31,4) /* next desc. pointer */
#define SDMA_TX_CNT_SBC_SHIFT 0 /* shadow byte count */
-#define SDMA_TX_CNT_SBC_MASK BITS(15,0) /* " " " */
+#define SDMA_TX_CNT_SBC_MASK __BITS(15,0) /* " " " */
#define SDMA_TX_CNT_BCNT_SHIFT 16 /* byte count */
-#define SDMA_TX_CNT_BCNT_MASK BITS(31,16 /* " " */
-#define SDMA_TX_CNT_NEXT_MASK BITS(31,4) /* next desc. pointer */
+#define SDMA_TX_CNT_BCNT_MASK __BITS(31,16 /* " " */
+#define SDMA_TX_CNT_NEXT_MASK __BITS(31,4) /* next desc. pointer */
#endif /* _GTSDMAREG_H */
